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1 PF SED520 SED520 Series Dot Matrix LCD SSC5000Series Controller Driver Ultra Low Power Consumption Built-in Video RAM DESCRIPTION The SED520 family of dot matrix LCD drivers are designed for the display of characters and graphics. The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM. The drivers are available in two configurations The SED520 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages. These features give the designer a flexible means of implementing small to medium size LCD displays for compact, low power systems. The SED520 which is able to drive two lines of twelve characters each. The SED52 which is able to drive 80 segments for extention. The SED522 which is able to drive one line of thirteen characters each. FEATURES Fast 8-bit MPU interface compatible with 80- and 68-family microcomputers Many command set Total 80 (segment + common) drive sets Low power 30 µw at 2 khz external clock Wide range of supply voltages VSS: 2.4 to 7.0 V V5: 3.5 to 3.0 V Low-power CMOS LINE-UP Product Clock Frequency Number Number Applicable Driver of SEG of CMOS Duty Name On-Chip External Drivers Drivers 8 khz 8 khz SED520 0, SED /6, /32 8 khz SED520 0, SED /8 to /32 8 khz 8 khz SED522 0, SED /8, /6 2 khz SED520 A, SED52 A 6 6 /6, /32 2 khz SED520 A, SED522 A 80 0 /8 to / /8, /6 SED520 0 SED52 0 SED522 0 SED520 A SED52 A SED522 A 2 khz SED522 A, SED52 A Package code (For example SED520) SED520T SED520F : PKG QFP5-00pin (plastic): SED520F A QFP5-00pin (plastic): SED520F C SED520D : Die form Al pad: SED520D A Au bump: SED520D B

2 BLOCK DIAGRAM An example of SED520 AA: LCD drive circuit Common counter Display data latch circuit Display start line register Line counter Line address decoder Display data RAM (2560-bit) I/O buffer Column address decoder CL Display timing generator circuit Column address counter Column address register Low-address register Command decoder Status Bus holder MPU interface D0~D7 A0,CS RD,WR (E,R/W) RES V,V2,V3,V4,V5 COM0 to COM5 SEG0 to SEG60 VSS 2

3 PACKAGE CONFIGURATION QFP5-00pin DB DB0 VSS R/W (WR) E (RD) CL (OSC2) CS (OSC) A0 SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG20 SEG2 INDEX 50 SEG22 SEG23 SEG24 SEG25 SEG26 45 SEG27 SEG28 SEG29 SEG30 SEG3 40 SEG32 SEG33 SEG34 SEG35 SEG36 35 SEG37 SEG38 SEG39 SEG40 SEG4 COW5 COW6 COW7 COW8 COW9 COW0 COW COW2 COW3 COW4 COW4 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG5 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG DB2 DB3 DB4 DB5 DB6 85 DB7 RES V5 90 V3 V2 V4 V 95 COW0 COM COM2 COM3 COM4 00 QFP5-00pin VSS DB0 DB DB2 DB3 DB4 DB5 DB6 DB7 RES V5 V3 V2 V4 V COM0 COM COM2 COM3 COM4 COM5 COM6 75 SEG20 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG4 SEG42 SEG43 SEG44 COM7 COM8 COM9 COM0 COM COM2 COM3 COM4 COM5 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG5 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 R/W (WR) E (RD) CL (OSC2) CS (OSC) A0 SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG INDEX Note: This is an example of SED520F pin assignment. The modified pin names are given below. Product Pin/Pad Number Name to 00, to SED520F0A OSC OSC2 COM0 to COM5 V4 V SED52F0A CS CL SEG76 to SEG6 SEG79 SEG78 SEG77 SED522F0A OSC OSC2 COM0 to 7, SEG68 to 6 V4 V SED520FAA CS CL COM0 to COM5 V4 V SED52FAA CS CL SEG76 to SEG6 SEG79 SEG78 SEG77 SED522FAA CS CL COM0 to 7, SEG68 to 6 V4 V SED520: SED522: Common outputs COM0 to COM5 of the master LSI correspond to COM3 to COM6 of the slave LSI. Common outputs COM0 to COM5 of the master LSI correspond to COM5 to COM8 of the slave LSI. 3

4 PAD LAYOUT Chip specifications of AL pad package Chip size: mm Pad pitch: µm Chip specifications of gold bump package Chip size: mm Bump pitch: 99 µm (Min.) Bump height: 22.5 µm (Typ.) Bump size: 32 µm (±20 µm) for mushroom model 6 92 µm (±4 µm) for vertical model Y 70 5 (0, 0) X mm D520D AA mm Note: An example of SED520DAA die numbers is given. These numbers are the same as the bump package. 4

5 PAD ARRANGEMENT An example of SED520DA pin names is given. The asterisk () can be A for AL pad package or B for gold bump package. SED520DAB Pad Center Coordinates Pad Pin Pad Pin Pad Pin X Y X Y No. Name No. Name No. Name X Y COM SEG SEG COM SEG SEG COM SEG SEG COM SEG SEG COM SEG A COM SEG CS COM SEG CL COM SEG E (RD) COM SEG R/W (WR) COM SEG VSS COM SEG DB SEG SEG DB SEG SEG DB SEG SEG DB SEG SEG DB SEG SEG DB SEG SEG DB SEG SEG DB SEG SEG SEG SEG RES SEG SEG SEG SEG V SEG SEG V SEG SEG V SEG SEG SEG SEG V SEG SEG V SEG SEG COM SEG SEG COM SEG SEG COM SEG SEG COM SEG SEG COM SEG SEG SEG SEG The other SED520 series packages have the different pin names as shown. Package/Pad No to 00, to SED520D0 OSC OSC2 COM0 to COM5 V4 V SED522D0 OSC OSC2 COM0 to 7, SEG68 to 6 V4 V SED522DA OSC OSC2 COM0 to 7, SEG68 to 6 V4 V SED52D0 CS CL SEG76 to SEG6 SEG79 SEG78 SEG77 SED52DA CS CL SEG76 to SEG6 SEG79 SEG78 SEG77 5

6 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage () VSS 8.0 to +0.3 V Supply voltage (2) V5 6.5 to +0.3 V Supply voltage (3) V, V4, V2, V3 V5 to +0.3 V Input voltage VIN VSS 0.3 to +0.3 V Output voltage VO VSS 0.3 to +0.3 V Power dissipation PD 250 mw Operating temperature Topr 40 to +85 C Storage temperature Tstg 65 to +50 C Soldering temperature time at lead Tsol 260, 0 C, sec Notes:. All voltages are specified relative to = 0 V. 2. The following relation must be always hold V V2 V3 V4 V5 3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional operation under these conditions is not implied. 4. Moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to avoid thermally stressing the package during board assembly. DC Characteristics (Ta = 20 to 75 C, = 0 V unless stated otherwise) Characteristic Symbol Condition Min. Typ. Max. Unit Applicable Pin Operating Recommended voltage () VSS V VSS. Allowable Recommended V5 V5 V Operating Allowable voltage (2) Allowable V, V2 0.6 V5 V V, V2 Allowable V3, V4 V5 0.4 V5 V V3, V4 VIHT VSS+2.0 2, 3 VIHC 0.2 VSS High-level input voltage VIHT VSS = 3 V 0.2 VSS 2, 3 VIHC VSS = 3 V 0.2 VSS V VILT VSS VSS+0.8 2, 3 VILC VSS 0.8 VSS Low-level input voltage VILT VSS = 3 V VSS 0.85 VSS 2, 3 VILC VSS = 3 V VSS 0.8 VSS High-level output voltage VOHT IOH = 3.0 ma VSS+2.4 OSC2 VOHC IOH = 2.0 ma VSS+2.4 V 4, 5 VOHC2 IOH = 20 µa 0.2 VSS VOHT VSS = 3 V IOH = 2 ma 0.2 VSS 4, 5 VOHC VSS = 3 V IOH = 2 ma 0.2 VSS V OSC2 VOHC2 VSS = 3 V IOH = 50 µa 0.2 VSS (continued) 6

7 DC Characteristics (Cont d) (Ta = 20 to 75 C, = 0 V unless stated otherwise) Characteristic Symbol Condition Min. Typ. Max. Unit Applicable Pin Low-level output voltage VOLT IOL = 3.0 ma VSS+0.4 VOLC IOL = 2.0 ma VSS+0.4 V VOLC2 IOL = 20 µa 0.8 VSS VOLT VSS = 3 V IOL = 2 ma 0.8 VSS VOLC VSS = 3 V IOL = 2 ma 0.8 VSS V VOLC2 VSS = 3 V IOL = 50 µa 0.8 VSS Input leakage current ILI.0.0 µa 6 Output leakage current ILO µa 7 OSC2 4, 5 4, 5 OSC2 V5 = 5.0 V SEG0 to 79, LCD driver ON resistance RON Ta = 25 C kω COM0 to 5, V5 = 3.5 V Static current dissipation IDDQ CS = CL = µa fcl = 2 khz During display Rf = MΩ µa V5 = 5.0 V 2, 3, 4 fcl = 8 khz IDD () During display fcl = 2 khz Dynamic current dissipation V5 = 5 V µa 2, 3 VSS = 3 V Rf = MΩ During access tcyc = 200 khz IDD (2) VSS = 3V, µa During access tcyc = 200 khz Input pin capacitance CIN Ta = 25 deg. C, f = MHz pf All input pins Rf =.0 MΩ ±2%, VSS = 5.0 V Oscillation frequency fosc khz 9 Rf =.0 MΩ ±2%, 6 2 VSS = 3.0 V RES Reset time tr.0 µs 5 Notes:. Operation over the specified voltage range is guaranteed, except where the supply voltage changes suddenly during CPU access. 2. A0, D0 to D7, E (or RD), R/W (or WR) and CS 3. CL,, and RES 4. D0 to D A0, E (or RD), R/W (or WR), CS, CL, and RES 7. When D0 to D7 and are high impedance. 8. During continual write acess at a frequency of tcyc. Current consumption during access is effectively proportional to the access frequency. 9. See figure below for details 0. See figure below for details. For a voltage differential of 0. V between input (V,, V4) and output (COM, SEG) pins. All voltages within specified operating voltage range. 2. SED520 A and SED52 A and SED522 A only. Does not include transient currents due to stray and panel capacitances. 3. SED520 0 and SED522 0 only. Does not include transient currents due to stray and panel capacitances. 4. SED52 0 only. Does not include transient currents due to stray and panel capacitances. 5. tr (Reset time) represents the time from the RES signal edge to the completion of reset of the internal circuit. Therefore, the SED520 series enters the normal operation status after this tr. 7

8 LCD PANEL CONNECTION EXAMPLE SED520F0A SED520F0A/SED522F0A SED522F0A SED520F0A SED520F0A Master Slave OSC OSC2 OSC OSC2 VSS Rf SED520FAA SED520FAA/SED522FAA SED522FAA SED520FAA SED520FAA Master CL Slave CL VSS External Clock SED520F0A/SED522F0A SED52F0A (See note ) SED520F0A SED52F0A Master OSC OSC2 Slave OSC OSC2 Rf 2 8

9 SED520FAA SED52FAA SED520FAA SED52FAA CL CL External Clock Notes:. The duty cycle of the slave must be the same as that for the master. 2. If a system has two or more slave drivers a CMOS buffer will be required. LCD PANEL CONNECTION EXAMPLE (The full-dot LCD panel displays a character in 6 8 dots.) /6 duty: 0 characters 2 lines LCD SEG COM SED520F /6 duty: 23 characters 2 lines LCD SEG SEG COM SED520F SED52F 9

10 /32 duty: 33 characters 4 lines 6 LCD SEG SEG SEG COM SED520F SED52F SED520F COM The SED52F can be omitted (the dot display mode is selected). Note: A combination of AB or AA type chip (that uses internal clocks) and 0B or 0A type chip (that uses external clocks) is NOT allowed. NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Morever, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. IBM is registered trademark of International Business Machines Corporation, U.S.A. Seiko Epson Corporation 994 All right reserved. DEVICE MARKETING DEPARTMENT IC Marketing & Engineering Group 42-8 Hino, Hino-shi, Tokyo 9, JAPAN Phone: FAX: International Marketing Department I (Europe, U.S.A.) 42-8 Hino, Hino-shi, Tokyo 9, JAPAN Phone: FAX: International Marketing Department II (ASIA) 42-8 Hino, Hino-shi, Tokyo 9, JAPAN First issue December, 994 Phone: FAX: Printed in Japan 0 S