PSEC-4: Review of Architecture, etc. Eric Oberla 27-oct-2012

Transcription

1 PSEC-4: Review of Architecture, etc. Eric Oberla 27-oct-2012

2 PSEC-4 ASIC: design specs LAPPD Collaboration Designed to sample & digitize fast pulses (MCPs): Sampling rate capability > 10GSa/s Analog bandwidth > 1 GHz (challenge!) Relatively short buffer size Medium event-rate capability (up to 100 KHz) 130 nm CMOS 10/27/2012 2

3 PSEC-4 ASIC: an overview GSa/a Waveform Sampling ASIC Designed as part of the Large-Area Picosecond Photo-Detector (LAPPD) project ACTUAL PERFORMANCE Sampling Rate GSa/s # Channels 6 Sampling Depth Input Noise 256 points ( ns) per channel <1 mv RMS Analog Bandwidth 1.5 GHz (f 3dB ) ADC conversion (ramp-compare) Dynamic Range Readout Latency Up to 12 bit (10 ENOB) 1.6 GHz V 2 µs (min) 16 µs (max) 6-channel PSEC-4 evaluation board in use at LAPPD micro-channel plate (MCP) test stand Signals from the large-area MCP tile are acquired from a 50-ohm transmission line anode. The relative timing between signals captured at both terminals of the microstrip anode is used to determine the position of a detector event. Dual-end readout of LAPPD 20x20 cm 2 MCP w/ 10 GSa/s -- left anode strip -- right anode strip

4 PSEC-4 ASIC: target application 10/27/2012 4

5 Architecture Overview & functional control Design requires (mostly) parallel control via FPGA/external DACs future serial interface/internal DACs? 10/27/2012 5

6 Architecture: pinout Decent separation of digital/analog signals future, better isolation is probably a good idea when considering board 10/27/ design/power plane separation

7 PSEC-4 timing diagram* *PSEC-3 timing shown (roughly the same), though PSEC-4 can run readout 2x faster future move (some) state machine control inside ASIC? 10/27/2012 7

8 Switched capacitor array sampling: analog down-conversion Write pointer passed along array - generates sampling window (~5-10 switches closed at once): LAPPD Collaboration [GHz sampling MHz readout: useful in most triggered event applications] Input 20fF Timing generation with a delay locked loop (DLL): Tiny charge: 1mV ~ 100e - Phase Comparator Charge pump To switched capacitor array sample & hold locked 10GSa/s w/ on chip DLL 10/27/2012 8

9 Delay Line Unit T(N)0-2 L/W determines sampling rate range. PSEC-4 delay line made from 256 of these units. A dual (rising & falling edge) phase comparator and charge pump (+digital logic) were implemented to delay-lock the input and 10/27/2012 output clocks for continuous sampling 9

10 PSEC-4 sampling rate Sampling rates GSa/s possible, BUT best jitter performance is when delay line is running fastest Should target sampling rate to application. Slow down (shift plot lower) if necessary -Continue 10/27/ using on-chip DLL?

11 Sampling Window Generation (8x delay stage) The sampling strobe is fixed to 8x the individual delay stage (i.e GSPS). Allowed plenty of time for RC settling on sampling cell. -How correlated are samples? - In future, should generate both the sampling strobe and its complement at the source to reduce timing calibrations 10/27/

12 Sampling Window Generation (8x delay stage) Bench testing: Indicative of correlation The sampling strobe is fixed to 8x the individual between delay adjacent stage (i.e. sample GSPS). Allowed plenty of time for cells RC settling if noise is on purely white sampling cell. -How correlated are samples? - In future, should generate both the sampling strobe and its complement at the source to reduce timing calibrations 10/27/

13 Sampling Cell Array (1 unit) Current design is extremely simple and robust. C_sample~20fF including parasitics. Input coupling > 2GHz. Future design enhancements? 10/27/

14 Sampling Cell Array (1 unit) Current design is extremely simple and robust. C_sample~20fF including parasitics Future design enhancements? 10/27/

15 Wilkinson Comparator (integrated w/ sampling cell) Excellent dynamic range (~1V) and linearity. However, NOT compact. Will need to consider options in a large analog storage array design 10/27/

16 Analog Bandwidth Bandwidth was carefully considered in PSEC-4 design. Probably reached limit of irreducible parasitics with current architecture. Shorter sampling array? 10/27/

17 Analog Bandwidth Bandwidth was carefully considered in PSEC-4 design. Probably reached limit of irreducible parasitics with current architecture. Shorter sampling array? 10/27/

18 Analog Bandwidth Bandwidth was carefully considered in PSEC-4 design. Probably reached limit of irreducible parasitics with current architecture. Shorter sampling array? 10/27/

19 ADC (Wilkinson) 12 bit asynch. counter + 1 level of digital storage per bit. Start/stop logic latched to comparator output + clocked by on-chip (per channel) ring oscillator 10/27/

20 ADC ring oscillator 5 stage ring oscillator using same delay units as delay line. Dedicated monitor circuit monitored with FPGA for frequency servo-control. Digital fan-out of clock on a per-channel basis 10/27/

21 ADC speed and power 10/27/

22 Linearity 10/27/

23 Linearity ADC scale determined by ramp slope (C_ext, Ramp_bias) and ring 10/27/2012 oscillator target frequency (firmware controlled) 23

24 Noise What s PSEC-4 s dominant noise source? 10/27/

25 Readout Slow (~40MHz tested), token readout architecture in PSEC-4 to a chip-wide 12 bit data bus. Limited by data bus capacitance. Completely replace in a new design. Fast serial readout (shift register) to LVDS drivers off-chip 10/27/

26 Readout Slow (~40MHz tested), token readout architecture in PSEC-4 to a chip-wide 12 bit data bus. Limited by data bus capacitance. Completely replace in a new design. Fast serial readout (shift register) to LVDS drivers off-chip. Send clock w/ data. 10/27/

27 Self-triggering Works ok. A bit of work to optimize bias parameters. PSEC-4 sends a trigger out bit for each channel. -Add amplifier stage before discriminator? (more robust triggering for low thresholds) -Encode trigger out bits? (save pins) 10/27/

28 Oscilloscope on a Chip? Not quite a modified approximation: LAPPD Collaboration + For example, a raw PSEC-3 readout (10 GS/s) of 120 MHz, 150 mv rms sine wave: 10/27/

29 Waveform Digitizer (Voltage) Calibration LAPPD Collaboration + Fixed cell-tocell pedestal variations ADC countto-voltage LUT = Straightforward to implement these corrections in an FPGA (need to apply these calibrations in order to further process data) 10/27/

30 Further Calibrations LAPPD Collaboration Time base correction: Keep overall sampling rate constant (or correct for drift) DONE w/ on-chip DLL Correct for cell-to-cell variations in sampling rate (nominal 10 Gsa/s) ~13% spread in Δt values 240 MHz sine with all calibrations applied (PSEC-4) Ready to go 10/27/

31 Summary Consolidate future design considerations prioritize design changes/needed simulations With a deeper buffer (a required upgrade), an overall new architecture is likely necessary. Certain design units potentially can be resused (trigger, delay unit, ADC register, etc ) 10/27/

32 10/27/

33 PSEC-3 persistence ( ghost pulses ) Varied sampling window size, and observed residual pulse 1,2, and 3 cycles after initial trigger. 10/27/

34 PSEC-3 persistance ( ghost pulses ) 10/27/