MICROPROCESSOR TECHNOLOGY

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1 MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 16 Ch.7 The and Microprocessors 21-Apr-15 1

2 System Descriptors The system descriptor defines information about the system s tables, tasks, and gates. There are 16 system descriptor types (Table Page 186) Some are defined for the (0001, 0011, 0100, 0101, 0110, and 0111) Some are new (1011, 1110, and 1111) Some are invalid Some are reserved for future Intel products 21-Apr-15 2

3 Descriptor Tables The descriptor tables define all the segments used in the when it operates in the protected mode. There are three types of descriptor tables: 1. Global descriptor table (GDT) 2. Local descriptor table (LDT) 3. Interrupt descriptor table (IDT) Registers used by the to address these tables are (GDTR, LDTR, and IDTR) 21-Apr-15 3

4 The Task State Segment (TSS) The TSS descriptor contains information about the location, size, and privilege level of the task state segment. The TSS described by the TSS descriptor does not contain data or code. It contains the state of the task and linkage The TSS descriptor is addressed by the task register (TR) The contents of the TR can be modified using the LTR instruction. 21-Apr-15 4

5 Moving to Protected Mode The following steps accomplish the switch from real mode to protected mode: 1. Initialize the IDT so that it contains valid interrupt gates for at least the first 32 interrupt time numbers. 2. Initialize the GDT so that it contains a null descriptor at descriptor 0, and valid descriptors for at least one code, one stack, and one data segment. 21-Apr-15 5

6 Moving to Protected Mode 3. Switch to protected mode by setting PE=1 in CR0 4. Perform a near JMP to flush the internal instruction queue and load the TR with the base TSS descriptor. 5. Load all segment registers with their initial selector values. See Fig Page Apr-15 6

7 Virtual 8086 Mode It is designed so that multiple 8086 real-mode software can execute at one time. The PC operates in this mode for DOS applications. It can be used to share one µp with many users by partitioning the memory so that each user has its own DOS partition. 21-Apr-15 7

8 Virtual 8086 Mode The system software can share the µp between users by switching from one to another to execute software. In this mode, 1Mb can be accessed from location 00000H FFFFFH This mode is entered by changing the VM bit in the EFLAG register to logic 1 It can be entered via an IRET instruction if the privilege level is Apr-15 8

9 The Memory Paging Mechanism The Page Directory: It contains the location of up to 1024 page translation tables. Each page translation table translates a logic address into a physical address The page directory is stored in memory and accessed by the page descriptor address register CR3 The page directory occupies one 4KB memory page 21-Apr-15 9

10 The Page Directory (Cont.) The page table directory control bits have the following functions: D: Dirty is provided for use by the OS only A: Accessed is set when the µp accesses the page directory entry. R/W and U/S: Read/Write and User/Supervisor are used in protection (Table P. 194) P: Present, if a logic 1, indicates that the entry can be used in address translation. 21-Apr-15 10

11 Introduction to Microprocessor The µp contains over 1.2 million transistors It contains an MMU, a numeric coprocessor compatible with the 80387, a high speed level one (L1) cache 8KB memory. It is available at 25, 33, 50, 66, or 100 MHz The 66 MHz version is double clocked The 100 MHz version is triple clocked Advanced Micro Devices (AMD) has produced a 40, 80, and 120 MHz versions. 21-Apr-15 11

12 M / IO Introduction to Microprocessor There are two versions: 80486SX and 80486DX The 80486SX does not contain the numeric coprocessor, which reduces its price. The coprocessor is available as a separate component for the 80486SX µp. There are few differences between the and the The most notable differences apply to the cache memory system and parity generator. 21-Apr-15 12

13 Pin-out of the 80486DX Microprocessor The is packaged in a 168 pin PGA +5V power supply ± 10% 650 ma for the 33 MHz version Logic 0 outputs allow up to 4 ma of current, and logic 1 outputs allow up to 1 ma. Pin Definitions: A2 A31: Address outputs 21-Apr-15 13

14 Pin Definitions A20M: Address bit 20 Mask, cause the to warp its address around from location 000FFFFF to This provides a memory system like the 1 MB real memory system in ADS: Address Data Strobe = 0 to indicate that the address bus contains a valid memory address. AHOLD: Address Hold input causes the µp to place its address bus connections at their high impedance state. 21-Apr-15 14

15 Pin Definitions BE0 BE3: Byte Enable select a bank of the memory system when information is transferred between the µp and its memory and I/O space. (BE0 enables D0 D7, BE1 enables D8 D15, ) BLAST: The Burst Last output shows that the burst bus cycle is complete on the next activation of the BRDY signal. BRDY: The Burst Ready input is used to signal the µp that a burst cycle is complete. 21-Apr-15 15

16 Pin Definitions BOFF: The Back-Off input = 0, causes the µp to place its buses at high impedance state (hold state) during the next clock cycle. BREQ: Bus Request output indicates that the has generated an internal bus request. BS8: Bus Size 8 input causes the µp to access byte-wide memory and I/O components. BS16: Bus Size 16 input causes the µp to access word-wide memory and I/O components. 21-Apr-15 16

17 Pin Definitions CLK: The Clock input provides the with its basic timing signal. If the µp works at 25MHz, the clock rate must be 25MHz. D0 D31: Data bus (D0 D7 are used to accept the interrupt vector type number) D/C: Data Control output indicates whether the current operation is a data transfer or control cycle (See table 7.3 Page 200) 21-Apr-15 17

18 Pin Definitions DP0 DP3: Data Parity I/O provides even parity for a write operation and check parity for a read operation. EADS: External Address Strobe input is used with AHOLD to signal that an external address is used to perform a cache invalidation cycle. FERR: Floating-point Error output indicates that the coprocessor has detected an error condition (It maintains compatibility with DOS software) 21-Apr-15 18

19 Pin Definitions FLUSH: The cache flush input forces the µp to erase the contents of its 8KB internal cache. HOLD: Hold input HLDA: Hold Acknowledge output IGNNE: Ignore Numeric Error input causes the coprocessor to ignore floating point errors and to continue data processing. INTR: Interrupt Request LOCK: Lock output 21-Apr-15 19

20 Pin Definitions KEN: Cache Enable input causes the current bus to be stored in the internal cache. M/IO: Memory/Input-Output NMI: Non-Maskable Interrupt input requests a type 2 interrupt. PCD: Page Cache Disable output reflects the state of the PCD bit in page table entry. PCHK: Parity Check output indicates that a parity error was detected during a read operation on the DP0 DP3 pins. 21-Apr-15 20

21 Pin Definitions PLOCK: Pseudo Lock output indicates that the current operation requires more than one bus cycle to perform. PWT: Page Write Through output indicates the state of the PWT bit in the page table entry. RDY: Ready input indicates that a non-burst bus cycle is complete. RESET: Initializes the W/R: Write/Read signals that the current bus cycle is read or write. 21-Apr-15 21

22 Basic Architecture The most prominent difference between the and the is that almost half of the instructions execute in 1 clocking period instead for 2 periods for the The contains 8 general-purpose 32 bit registers It also contains six 16-bit segment registers The IP addresses the program located within the 1 MB of memory in combination with CS. The EIP addresses 4GB of memory system 21-Apr-15 22

23 Basic Architecture It contains also global, local, and interrupt descriptor table registers and MMU (like 80386) The EFLAGS register contains a new flag bit (AC- Alignment Check bit) The AC-bit is used to indicate that the µp has accessed a word at an odd address or a double word stored at a non-double word boundary. 21-Apr-15 23

24 80486 Memory System The major change to the memory system is internal in the form of an 8-KB cache which speeds the execution of instructions. Another addition is the built-in parity checker generator which indicates if data are correctly read from a memory location. The parity is generated by the during each write cycle as even parity. The parity check bits appear on pins DP0 DP3 21-Apr-15 24

25 80486 Memory System Cache Memory: Cache is organized as a 4-way set associative cache It operates as a write-through cache The cache changes only if a miss occurs. CR0: is used to control the cache with 2 new control bits: CD and NW CD: If Cache Enable bit = 1, all cache operations are inhibited. It is set only for debugging software. 21-Apr-15 25

26 80486 Memory System NW: Non-cache Write-through bit is used to inhibit cache write-through operation. Cache filling is accomplished with a burst cycle which is a special memory where four 32-bit numbers are fetched from the memory system in five clocking periods. 21-Apr-15 26

27 Memory Read Timing For a non-burst systems, two clocking periods are used to transfer data. Clocking period T1 provides the memory and control signals. Clocking period T2 is where the data are transferred between the memory and the µp. Access time = 2 clocking periods address setup time data setup time NOTE: The 33, 66, and 100 MHz processors all access bus data at a 33 MHz rate. 21-Apr-15 27

28 80486 Memory Management The paging system can be disabled for caching sections of translated memory pages, while the can not. The page table entry contains two new control bits (PWT and PCD). PWT controls how the cache functions for a write operation of the external cache memory. PCD controls the on-chip cache (PCD=0 enabled) 21-Apr-15 28

29 Cache Test Registers TR3 (Cache data register) is used to access either the cache fill buffer for a write test operation or the cache read buffer for a read test operation. (Used for testing the cache) The contents of the set select field in TR5 (cache control register) determine which internal cache line is written or read through TR3. TR4 (Cache status register) holds the cache tag, LRU bits, and a valid bit. 21-Apr-15 29

30 Thank You With all best wishes!! 21-Apr-15 30

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