_ V1.3. Motorola 68HC11 AE/AS POD rev. F. POD Hardware Reference

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1 _ V1.3 POD Hardware Reference Motorola 68HC11 AE/AS POD rev. F Ordering code IC81049 Thank you for purchasing this product from isystem. This product has been carefully crafted to satisfy your needs. Should any questions arise, do not hesitate to contact your local distributor or isystem directly. Our technical support personnel will be happy to answer all your technical support questions. All information, including contact information, is available on our web site Feel free also to explore our alternative products. isystem constantly yields for development and therefore certain pictures in this documentation may vary slightly from the actual product you received. The differences should be minor, but should you find more serious inconsistencies of the product with the documentation, please contact your local distributor for more information. This document and all documents accompanying it are copyrighted by isystem and all rights are reserved. Duplication of these documents is allowed for personal use. For every other case a written consent from isystem is required. Copyright 2003 isystem, GmbH. All rights reserved. All trademarks are property of their respective owners. isystem, August /12

2 _ POD Hardware Reference In-Circuit Emulation PODs The following elements of interest are located on all In-Circuit emulation PODs: emulation CPU - acts on behalf of target's CPU. On some PODs you must use the same CPU on the POD as it is used on the target (see your POD reference page). In such cases, remove the CPU from the POD and insert the CPU that you use in the target system, in its place. red LED (D3) - lit when CPU is running green LED (D4) - lit when Emulator is ready for emulation a connector, mostly marked ST3 - contains signal lines, some of which are hardware configuration lines (such as bank select signals), others you can use for signal generation (pattern generator outputs). Here are some common signals found on the signal connector, commonly marked as ST3: GND Ground BPE External breakpoint input. Active high. RESO/RO Reset output. Connect to target to reset peripherals. TRES/TR Target reset input. AUXn AUX signal inputs (same as inputs on Emulator/trace) Note: On PODs that support synchronization between two or more Emulators (currently only the HC(S)12 Family, see the Synchronization section in the Hardware User's Guide for more information) AUX0 and AUX1 are cut short with Run/Stop synchronization line, and AUX2, AUX3 with RESET synchronization line. You should use these pins to connect to other PODs or target CPUs. PAT0-2 Pattern generator output on 16-bit POD OC4-6 Pattern generator output on 8-bit POD Note: The signal connector can also have other markings, like P1, U1, etc. Please refer to the POD-specific documentation for the signal connector name and signals present. isystem, August /12

3 For every POD the following information is given: Ordering code. If there are different speed versions of a POD the ordering code is modified by appending the speed in MHz (IC for the 16 MHz 8031 POD) information on available speed versions and required Emulator access time POD size and position of PIN1 on the target adapter relative to bottom left corner. The memory range specifies the range of addresses that a POD can address. If this specification is omitted the default 1MB is assumed. Note: The In-Circuit Emulator can emulate a processor or a microcontroller. Beside the CPU, additional logic is integrated on the POD. The amount of additional logic depends on the emulated CPU and the type of emulation. A buffer on a data bus is always used (minimal logic) and when rebuilding ports on the POD, maximum logic is used. As soon as a POD is inserted in the target instead of the CPU, electrical and timing characteristics are changed. Different electrical and timing characteristics of used elements on the POD and prolonged lines from the target to the CPU on the POD contribute to different POD characteristics. Consequently, signal cross-talks and reflections occur, capacitance changes, etc. Beside that, pull-up and pull-down resistors are added to some signals. Pull-up/pull-down resistors are required to define the inactive state of signals like reset and interrupt inputs, while the POD is not connected to the target. Because of this, the POD can operate as standalone without the target. Final Target Application Test After the application is being more or less debugged and final application test is performed, it is recommended to remove all breakpoints and to close all debug windows (memory, SFR, watch...) to eliminate any possible influence of the emulator on the CPU execution. There were cases where the target application has been behaving differently with the target CPU inserted or the POD connected. If the debugger is configured to update some debug windows in real-time, the user may not be aware of that the CPU execution may be slightly disturbed. However, when the monitor access type is configured to update debug windows while the CPU is running, the CPU execution is disturbed significantly, depending on the necessary number of memory accesses to update opened debug windows. There are cases when internal peripheral device requires read access of the particular register during the device configuration. The user has had SFR window opened and the necessary read access was actually performed by the debugger and not by the application as it would be correct. Therefore, the application was working fine with the emulator, but a standalone application didn't work correctly, as the peripheral device was not configured properly. For Better Understanding of the Hardware Reference: PIN 1 locations There are several references to pin 1 in the manual and many jumper settings, CPU and pinout orientations rely on the correct location of pin 1. If sometimes the location of pin 1 is not clear, check the markings on the POD. If there are no markings, check the PCB board of the POD. Pin 1 is always marked on the PCB with a square pin (the other pins are round). The pin 1 location is also visible on the board in the hardware reference, if not any other way it can be identified by searching for the square pin. isystem, August /12

4 _ POD Hardware Reference Motorola 68HC11 AE/AS POD rev. F Ordering code IC81049 POD Speed (MHz) 4 Emulator Speed (ns) 90 Exchange CPU YES Bank switch support YES Before connecting the POD, make sure you have read the technical notes on Motorola 68HC11 Family in the Hardware User's Guide. This PODs is an 8-bit PODs that can be used on ic181, ic1000 and the PowerEmulator unit. Bank switching is supported. POD Layout This POD can be used for single-chip and expanded mode applications. For expanded mode applications, the PGA52 adapter shipped with the POD must be used. For single-chip applications an appropriate single-chip adapter must be used. The below table identifies the adapter. isystem, August /12

5 Emulated CPU 68HC11A0 68HC11A1 68HC11A7 68HC11A8 68HC11E0 68HC11E1 68HC811E2 68HC11E8 68HC11E9 68HC711E9 68HC11E20 Single Chip Adapter N/A N/A HC11apru or HC11axaf HC11apru or HC11axaf N/A N/A HC11apru or HC11axaf HC11apru or HC11axaf HC11apru, HC11axaf or HC11exaf HC11apru, HC11axaf or HC11exaf HC11apru or HC11axaf Jumper Settings Jumper J1 determines the voltage level for the CPU. Position Set (*) Removed CPU voltage 5 V 3.3 V Jumper selector JX connects target and CPU XTAL. Jumper J1 settings (* - factory default) Position Set (*) Removed CPU target XTAL Connected Not Connected Jumper JX settings (* - factory default) If clock from the emulator is used and there is an crystal in the target, this jumper should be removed, if problems with the clock occur. Electrical Differences and Rebuilt Ports In general, when emulating the single chip mode, some ports have to be rebuilt on the POD because original ports are used for emulation typically ports used as address and data bus in extended mode. Special devices, so called port replacement units, provided already by the CPU vendor or other standard integrated circuits are used to rebuilt "lost" ports. Rebuilt ports are logically 100% compatible with original CPU s ports, but electrical characteristics may differ. If special device (port replacement unit) is available, electrical characteristics don t differ much and usually the user doesn t have to pay attention. The differences may become relevant when standard integrated circuits are used and operating close to electrical limits, e.g. when input voltage level is close to specified maximum voltage for low input level ( 0 ) or specified minimum voltage for high input level ( 1 ). When emulating the single chip mode, original ports B and C are used for the emulation and rebuilt by standard integrated circuits on the POD. Therefore, electrical characteristics are changed. Using the emulator, the port registers (Port Registers and Port Data Direction Registers) belonging to the rebuilt ports must be mapped to the target when emulating the single-chip mode. Special logic is present on the IRQ, RESET, XIRQ, R/W and E signals and therefore electrical characteristics are changed when emulating single-chip or extended mode. isystem, August /12

6 Whenever operating close to electrical limits and having problems with rebuilt ports please check pull-up and pull-down resistors. They shouldn t be too strong, neither too weak. Check the voltage level. Try to withdraw from voltage limits. Single-Chip Adapters and Emulation Notes HC11exaf and HC11axaf adapters are used to emulate single chip mode. In this mode port B and port C are rebuilt by a so called Port Replacement Unit (PRU) designed by Motorola. Both adapters have some limitations which originate from Motorola's PRU device. When using port B and POD with HC11exaf adapter the user should write appropriate value into the port B data direction (DDRB) or to the adequate address (0x1006) when there is no DDRB register. Some MCUs supported by HC11exaf adapter have DDRB and some don't. For proper PRU operation the user must always write to DDRB (0x1006) prior to use port B as output. Tip: To define port B as output you can add single write of value 0xFF to address 0x1006 in the 'Initialization' tab in the 'Hardware/In-circuit emulation' dialog. This sequence will be executed always when the system will be reseted for the first time or when the download will be executed. Of course the user can add this sequence in his user program instead to the 'Initialization' dialog. For E9 CPUs the single chip adapter must be chosen according to application requirements and adapter limitations. When using HC24 PRU (HC11axaf adapter), the I/O capabilities of Port B on E9 can not be fully used, since the port is output only, on the other hand, the STRA and STRB signals are supported. When using the HC27 PRU (HC11exaf adapter), the I/O capabilities of Port B are available for input and output, but the STRA and STRB signals are not available. HC11axaf single-chip adapter (shipped with POD) This adapter uses the HC24 PRU on which the port B is output only. isystem, August /12

7 HC11exaf single-chip adapter (shipped with POD) This adapter uses the HC27 PRU on which STRA and STRB are not available. Jumper selector J1A connects CPU AS (Address strobe) to target. Position Set (*) Removed CPU target AS Connected Not Connected Jumper selector J2A connects CPU R/W to target. Jumper J1A settings (* - factory default) Position Set (*) Removed CPU target R/W Connected Not Connected Jumper J2A settings (* - factory default) Note: the HC27 PRU presets registers to address 0. The Emulator will set those to the default (1000h). This can however not be achieved with the Reset and run command. If this command is used. The registers must be moved to 1000 explicitly by the target application, by writing 1 into low 4 bits of the INIT (3Dh) register. isystem, August /12

8 Assembly Instructions for Extended Mode and Single-Chip Applications When purchasing the 68HC11 AE/AS POD (IC81049), it is delivered with the PGA52 adapter, assembled by default. The POD is ready for use when emulating the expanded mode. The 68HC11 AE/AS POD with the standard PGA52 adapter When emulating the single chip mode, one of available single chip adapters must be used, either HC11 axaf or HC11 exaf adapter. The adapters have some limitations, which differ and have been discussed above. Single-chip adapters: on the left side HC11axaf, on the right side HC11exaf isystem, August /12

9 When a single chip adapter is used, first the PGA52 adapter must be removed from the POD and then the HC11 axaf or HC11 exaf adapter inserted. The POD is ready to emulate the single chip mode. The PGA52 adapter, removed from the POD on the left and the 68HC11 AE/AS POD with a Single-Chip adapter on the right General HC11 Emulation Notes MODA/LIR CPU pin Check the MODA/LIR signal. The signal MODA/LIR must be connected to the target by pull-up or pull-down resistor, depending on the mode that your application runs in (single chip or extended). The signal must be available for in-circuit emulator for proper operation. You must not tie the signal directly to the GND or Vcc since the signal becomes output when the CPU is released from the reset. Wait Mode, Stop Mode Both of them are supported. When the CPU is in one of the mode, it generates (random) dummy cycles, the debugger looses the control over it and HALTED status is displayed in winideatm. The CPU can be brought out of the mode by the external IRQ and external RESET. COP Internal watchdog must be disabled during the debugging, otherwise the emulation fails. Internal RAM, Internal EEPROM If the CPU provides a capability to write to the internal RAM or EEPROM via memory window (no specific programming sequence required), the download file can be loaded to the internal RAM or EEPROM using the Target Download option. The debugger downloads the code to the internal memory after reset via the CPU. If the CPU requires some registers to be configured before the CPU is able to write in the EEPROM area, the user must configure the necessary registers respectively, using the initialization dialog. Any sequence, added in the initialization dialog, is executed immediately after reset, before the download is performed. At HC11 family pay attention to the configuration of the BPROT register (if available on the CPU used), that can prevent write access to the EEPROM. If you want to modify the contents of the EEPROM within your debugging session, you should disable the BPROT protection. Refer to the CPU datasheets for more information. Note that debugging is limited while executing the program in the internal EEPROM or RAM. While the CPU accesses internal memory resources, the in-circuit emulator (ICE) loses the control over the CPU since the external bus is not active. Therefore, breakpoints cannot be set and the user's program cannot be stopped or isystem, August /12

10 stepped when executing in the internal EEPROM/RAM. Additionally, debug windows cannot be updated as well. Normally, in the target application the CPU executes the program in the internal or external ROM. Using the ICE, ROM memory is overlaid by the emulation memory and consequently the program can be debugged without restrictions. But, sometimes, there is a need to execute some short routines in the CPU internal memory. Using the ICE, the user can run such a routine, but he cannot debug it. Clock Clock source can be either used internal from the emulator or external from the target. It is recommended to use the internal clock when possible. When using the clock from the target, it may happen that the emulator cannot initialize any more. It is dissuaded to use a crystal in the target as a clock source during the emulation. It is recommended that the oscillator is used instead. Normally, a crystal and two capacitors are connected to the CPU's clock inputs in the target application as stated in the CPU datasheets. A length of clock paths is critical and must be taken into consideration when designing the target. During the emulation, the distance between the crystal in the target and the CPU (on the POD) is furthermore increased, therefore the impedance may change in a manner that the crystal doesn't oscillate anymore. In such case, a standalone crystal circuit, oscillating already without the CPU must be built or oscillator used. Checksum When performing any kind of checksum in the emulated (code) area, note that all breakpoints must be removed before, otherwise the results are distorted. Note that the emulator forces "breakpoint" instruction on the data bus when executing the code at the address where breakpoint is set. Exchanging the CPU Standard CPUs are inserted on all HC11 PODs. When it is necessary to exchange the CPU, note that internal ROM and COP must be disabled, otherwise the emulation fails. Internal ROM is disabled by programming the ROMON bit in the CONFIG register. Refer to the hardware user's guide - chapter 'Technical Notes/HC11 family' for more information isystem, August /12

11 The Signal Connector Two signal connectors are available on the POD, marked ST3A and ST3B BSC PD0 PD1 PD2 PD3 PD4 BANK GND BS0 BS1 BS2 BS3 BS4 TA ST3A signal connector pinout Signal PD0 PD4 BS0 BS4 BSC BANK TA15 Description Port D output pins. Can be bridged with BS pins for memory banking through D port. Bank select lines for memory banking. CODE Bank size select. Open: <=32 KB; Bridged to GND: 64 KB If 32KB banks area used then this pin determines the position of the bank. If bank area is placed from 0 to 7FFFh, leave this pin not connected, otherwise (bank 8000h-FFFFh) bridge this pin with GND pin. For testing purposes only, A15 CPU Line ST3A Connector signal description Pin Signal Signal Description 1 GND Ground 2 GND Ground 3 BPE External Breakpoint Input 4 RO Reset Output 5 TR Target Reset Input 6 AU0 AUX Signal Input 7 AU1 AUX Signal Input 8 AU2 AUX Signal Input 9 AU3 AUX Signal Input ST3B Signal Connector Target Adapters isystem offers various adapter solutions for this POD. Please refer to the adapter documentation for more details. isystem, August /12

12 POD Target Layout The POD target layout is T_PLCC T_PLCC52 Top POD view The POD comes shipped with a standard PGA52 adapter PGA52 Top adapter view PGA52 (left) and T_PLCC52 (right) dimensions isystem, August /12