SCALING DGEMM TO MULTIPLE CAYMAN GPUS AND INTERLAGOS MANY-CORE CPUS FOR HPL

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2 SCALING DGEMM TO MULTIPLE CAYMAN GPUS AND INTERLAGOS MANY-CORE CPUS FOR HPL Matthias Bach and David Rohr Frankfurt Institute for Advanced Studies Goethe University of Frankfurt

3 I: INTRODUCTION 3 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

LOEWE-CSC An AMD based supercomputer 786 GPU compute nodes 2 x 2.1 GHz 12-core AMD Opteron 1 AMD Radeon 5870 GPU 40 high density compute nodes 4 x 2.1 GHz 12 core AMD Opteron 32 GiB RAM / CPU 16.

4 LOEWE-CSC An AMD based supercomputer 786 GPU compute nodes 2 x 2.1 GHz 12-core AMD Opteron 1 AMD Radeon 5870 GPU 40 high density compute nodes 4 x 2.1 GHz 12 core AMD Opteron 32 GiB RAM / CPU 16.5 TB/s bisectional network bandwidth 1.62 PB local storage New HPL version and own DGEMM kernel 299 Gflops overall # 22 Top 500 November 2010 # 8 Green 500 November Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

5 DGEMM AND LINPACK Optimizing Step by Step The given optimization problems LINPACK Usually HPL Solves A * x = b Gaussian Elimination with partial pivotization Performance dominated by DGEMM DGEMM General Matrix Multiply C = alpha * A * B + beta * C The Optimization Steps GPU DGEMM Kernel DGEMM on a one GPU system DGEMM on a multi-gpu system Moving from Cypress to Cayman Tuning HPL for a GPU DGEMM Using Interlagos in the Future 5 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

6 II: DGEMM KERNELS 6 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

DGEMM KERNELS Matrix Blocking DGEMM = General Matrix Multiply C = alpha * A * B + beta * C A * B on GPU A: nxk Matrix, B: kxm Matrix, C: nxm Matrix Complexity: 2 * m * n * k Floating Point Operations

7 DGEMM KERNELS Matrix Blocking DGEMM = General Matrix Multiply C = alpha * A * B + beta * C A * B on GPU A: nxk Matrix, B: kxm Matrix, C: nxm Matrix Complexity: 2 * m * n * k Floating Point Operations 2 * m * n * k Memory Fetches Blocking: Ail = ax1 matrix; Blj = 1Xb matrix; Cij = axb matrix Caching Ai and Bj reduces memory fetches One block per thread More registers required for larger blocking (e.g. 41 for 8x8) Block size vs. Wavefront count Larger Blocking reduces memory fetches Smaller Blocking increases number of Wavefronts 7 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

8 KERNEL TUNING Parameters of an optimal kernel Assume square C matrix for simplicity Optimal kernel parameters determined Experimentally 4 x 4 blocking B matrix transposed, A matrix not transposed Pixel Shader kernel and no Compute Shader Output using Color Buffers not MemExport Output buffer located either in host or GPU Memory (Depends on GPU and Chipset) Loop unrolled with an unrolling factor of two Texture cache is used in tiled mode Hardcoded K = 1024 Identical for Cypress and Cayman 8 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

9 MATRIX SIZE DEPENDENCE OF THE KERNEL Cypress Kernel Performance depends on: K = Length of scalar product H = # of lines / rows in C matrix calculated per kernel launch Cypress prefers large values for both Good: K = 1024, H >= 1024 (best >= 3072) H can be chosen depending on M and N of A and B. Kernel Peak Performance: 494 Gflop/s 9 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

10 MATRIX SIZE DEPENDENCE OF THE KERNEL Cayman Kernel Performance depends on: K = Length of scalar product H = # of lines / rows in C matrix calculated per kernel launch Cypress prefers large values for both Good: K = 1024, H >= 1024 (best >= 3072) Cayman prefers smaller values values for both Larger matrices must be cut into blocks Kernel Peak Performance: 617 Gflop/s 10 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

11 III: DGEMM SYSTEM PERFORMANCE 11 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

FULL DGEMM Feeding work to the GPU C Matrix does not fit in GPU memory Divide problem into blocks Chose perfect problem sizes for GPU Remainder from block construction processed by CPU For each

12 FULL DGEMM Feeding work to the GPU C Matrix does not fit in GPU memory Divide problem into blocks Chose perfect problem sizes for GPU Remainder from block construction processed by CPU For each A-submatrix, all B-submatrices are iterated over this fixed A-submatrix. The B-submatrices stay on the GPU, submatrices of A are not necessarily stored. (halves memory need) Still, each matrix is transferred exactly once. 12 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

GPU SCHEDULING A simple approach GPU only calculates A * B + C done on host GPU requires special memory layout Pre and post processing required DivideBuffer Transform A and B as

13 GPU SCHEDULING A simple approach GPU only calculates A * B + C done on host GPU requires special memory layout Pre and post processing required DivideBuffer Transform A and B as required MergeBuffer Add GPU result (A*B) and C Performance loss due to GPU idle time 13 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

blocks of B over fixed A Minimize PCIe transfers 14 Scaling DGEMM to

14 GPU SCHEDULING Building a pipeline Pipeline minimizes GPU idle time One Divide + one merge DMA must be started before kernel Iterate blocks of B over fixed A Minimize PCIe transfers 14 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

15 DGEMM SYSTEM PERFORMANCE Hiding PCIe 15 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

16 DGEMM KERNELS Matrix Tiling Using the CPU only for the remainder part of the tiling wastes CPU power. Distribute workload among GPU/CPU Phase 1b: Remainder Part Phase 1a: Large rectangular Block (size chosen such that CPU finishes slightly before GPU) Phase 2: Second rectangular Block Phase 3: Single Tiles (Work Stealing) Size of rectangular blocks chosen based on vacant matrix size and performance estimations. Processing larger rectangular blocks increases CPU DGEMM performance compared to single tiles. CPU / GPU DGEMM performance continuously monitored. Monitored performance data used to improve estimations for next DGEMM call. 16 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

17 DGEMM SYSTEM PERFORMANCE Matrix size effects 17 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

18 IV: MULTI-GPU DGEMM 18 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

After the first GPU has processed its part, the remaining tiles are processed in a

19 MATRIX DISTRIBUTION Matrix distribution among n GPUs B Matrix split in n parts. Each GPU processes only one part of B. Buffer requirement reduced. After the first GPU has processed its part, the remaining tiles are processed in a round-robin fashion. 19 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

20 DUAL-GPU PERFORMANCE Analysis of dual-gpu version Accumulated Max. Perf. is the accumulated DGEMM performance of all contributing processing elements. The accumulated Max. Perf. is corrected for the CPU cores for GPU pre- and postprocessing to approximate performance of best case implementation. The efficiency is the ratio of the achieved performance and this best case performance. 20 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

21 MULTI-GPU BANDWIDTH REQUIREMENTS Multi-GPU DGEMM has tremendous memory and PCI-Express throughput requirements Reading from and writing to the C-matrix requires at least: (g Performance in Gflop/s, s size of Element in bytes, i.e. 8 for double precision floating point) p(k) = g * s / 2k m(k) = 2 g * s / k p(1024) = 1.82 * n [GB/s] p(2048) = 0.91 * n [GB/s] m(1024) = 7.27 * n [GB/s] m(2048) = 3.63 * n [GB/s] Additional throughput required for concurrent CPU DGEMM. PCI performance sufficient, even for two GPUs via PCI-express switch. Memory performance possibly insufficient, depends on k. 21 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

22 MULTI-GPU PERFORMANCE Multi-GPU performance depends greatly on k Larger k decreases memory bandwidth requirements. Performance becomes constant for large k. Predictions for Quad-GPU and more The k parameter gets even more critical. GPU memory requirement scales linearly with k. Bounded k range due to GPU memory limitations. 22 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

23 TRIPPLE-GPU PERFORMANCE Speed scales almost linearly to three GPUs The faster 5870 GPU core scales worse than the two slower 9350 and The 5970 works like two Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

CPU UTILIZATION CPU utilization per core during DGEMM and HPL Core 0 performs

One core sufficient for preprocessing and management of up to two GPUs.

Preprocessing multithreaded for more then two GPUs.

24 CPU UTILIZATION CPU utilization per core during DGEMM and HPL Core 0 performs preprocessing and management of DMA transfer. One core sufficient for preprocessing and management of up to two GPUs. Postprocessing multithreaded for slow CPU / dual GPU Optimized Implementation Preprocessing multithreaded for more then two GPUs. Threads for pre- and postprecissing pinned to the CPU die with closest connection to the GPU. 24 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

25 DGEMM PERFORMANCE Maximum DGEMM performance achieved: 5870 GPU, GPU only 465 Gflop/s Two Magny-Cours 6172 CPUs, 5870 GPU 625 Gflop/s 8 Nehalem cores 2.26 GHz, 5970 GPU 832 Gflop/s Two Magny-Cours 6174 CPUs, three 5870 GPUs 1432 Gflop/s 25 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

26 V: GOING FROM CYPRESS TO CAYMAN 26 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

(round-robin use) 27 Scaling DGEMM to Multiple Cayman

27 CAYMAN & DMA Multiple Buffers for B-Matrix Two Buffers for A Matrix (round-robin use) Three Buffers for Output (round-robin use) 27 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

28 CAYMAN & DMA Multiple Buffers for B-Matrix Two Buffers for A Matrix (round-robin use) Three Buffers for Output (round-robin use) Transfer to GPU performed by DMA Engine Two additional page locked buffers per input matrix on host side (round robin use) 28 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

29 CAYMAN & DMA Multiple Buffers for B-Matrix Two Buffers for A Matrix (round-robin use) Three Buffers for Output (round-robin use) Transfer to GPU performed by DMA Engine Two additional page locked buffers per input matrix on host side (round robin use) Addition of DGEMM done by host PROBLEM: Cayman shows poor performance when using DMA engine. 29 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

30 CAYMAN & DMA DMA Performance (GPU to CPU) Kernel must write to 128 bit buffer. Kernel can write directly to host memory in 128 bit format bypassing the DMA engine. 30 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

31 CAYMAN & DMA DMA Performance (CPU to GPU) Cayman shows full DMA speed for 64 bit transfers. Kernel must read from 128 bit buffer for full performance. Different DMA Path (1b) introduced. DMA Performance (GPU to CPU) Kernel must write to 128 bit buffer. Kernel can write directly to host memory in 128 bit format bypassing the DMA engine. Using 64 bit conversion Infeasible. 31 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

32 CAYMAN & DMA Multi-GPU All buffers replicated on each device. Processing split along B-Matrix. Each GPU caches only a part of the B- Matrix. 32 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

33 VI: HPL 33 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

34 HPL (HIGH PERFORMANCE LINPACK) Linpack iteratively factorizes a dense system of linear equations. Each iteration consists of: Panel factorization Panel broadcast Line swapping & U-broadcast U-matrix update (DTRSM) C-matrix update (DGEMM) HPL utilizes BLAS routines Major contribution to workload by DGEMM. (95.6% of total execution time) 34 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

As only DGEMM has a considerable contribution to the overall calculation effort, the HPL performance is

35 NAIVE HPL-GPU IMPLEMENTATION First naive HPL-GPU implementation offloads the large DGEMM for C-matrix update to GPU. GPU-DGEMM makes up 78% of total execution time. GPU is idling at 22% of the time. As only DGEMM has a considerable contribution to the overall calculation effort, the HPL performance is limited to 78% of DGEMM performance. 35 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

HIDING FACTORIZATION AND BROADCAST TIME (LOOKAHEAD) Factorization requires only the first NB colums of the previous iteration to finish Factorization and broadcast for next iteration can be processed

36 HIDING FACTORIZATION AND BROADCAST TIME (LOOKAHEAD) Factorization requires only the first NB colums of the previous iteration to finish Factorization and broadcast for next iteration can be processed in parallel with the DGEMM. Two issues occur: Running pre- and postprocessing in parallel with factorization leads to memory congestion. During broadcast, only one CPU core is active. 36 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

37 IMPROVED LOOKAHEAD CPU DGEMM split in two parts to improve utilization during broadcast. CPU cores idle by intention during factorization to avoid memory congestion and ensure full GPU DGEMM performance. Binary patch of the AMD driver changes memory policies and decreases page fault rate. 37 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

38 HIDING PIVOTIZATION TIME (LOOKAHEAD 2) Also pivotization time can be hidden HPL performance improves significantly with lookahead. 38 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

39 HPL PERFORMANCE Multi-node and single node performance is constantly higher with lookahead. 39 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

40 SINGLE GPU PEAK PERFORMANCES Peak performance achieved at LOEWE-CSC. Two 6172 Magny-Cours CPU 2.1 GHz, GPU. Multi node per node performance achieves 93.6% of single-node performance. Discipline Performance Peak Efficiency DGEMM Kernel % GPU DGEMM System % GPU/CPU DGEMM System % Single-node HPL % Multi-node HPL % 40 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

41 MULTI-GPU HPL Concept More threads used for pre and post processing. Dynamic factorization thread count improves performance, especially for k = NB >= Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

42 MULTI-GPU HPL Benchmarks First multi-gpu benchmarks: (2 * 6174 CPU, 3 * 5870 GPU) HPL: 1114 Gflop/s DGEMM: 1432 Gflop/s Multi GPU Efficiency: (2 * 6174 CPU, 3 * V7800 GPU) HPL: 1230 Gflop/s / Watt Efficiency optimized version offloads as much workload as possible to the GPU, even if this leaves the CPU idling. 42 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

43 VII: INTERLAGOS 43 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

44 INTERLAGOS Looking ahead Expectations Optimized BLAS libaries achieve peak performance for any CPU. Since two cores of a module share floating point unit, DGEMM may not have to run on all cores. These cores can be used for GPU pre/postprocessing. No big changes necessary, CPU contribution to overall performance small, at least for multi-gpu. Problems Support for 3DNow! dropped. GotoBLAS no longer adopted to new CPUs. Patches to GotoBLAS for CPU core reservation need to be ported to another BLAS library. 44 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

systems LOEWE-CSC already heterogenous Quad nodes without GPU 45 Scaling

45 HETEROGENEOUS SYSTEMS Work Distribution Interlagos as update option For LOEWE-CSC as additional nodes Traditional distribution targets homogeneous systems LOEWE-CSC already heterogenous Quad nodes without GPU 45 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

Skip process rows during allocation 46 Scaling DGEMM to

46 HETEROGENEOUS SYSTEMS Work Distribution Groups nodes into performance classes Size submatrices according to performance Skip process rows during allocation 46 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

HETEROGENEOUS SYSTEMS Benchmarks Benchmarks on 6 node setup 2 Quads + 2 GPUs

25% granularity loss Optimized version ~ 3 % granularity loss 47 Scaling

47 HETEROGENEOUS SYSTEMS Benchmarks Benchmarks on 6 node setup 2 Quads MHz MHz Original version speed ~ 6 times Quad speed ~ 25% granularity loss Optimized version ~ 3 % granularity loss 47 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

48 SUMMARY 48 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

49 SUMMARY High Performance DGEMM Kernels 494 Gflops % of peak High Performance CPU/GPU DGEMM Automatic load balancing 625 Gflops 84% of peak Modified HPL Keeping GPU busy 563 Gflops 76% of peak Scaling to multi-gpu nodes Scaling to many nodes Minimum granularity loss on heterogeneous systems Open Source: Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

50 QUESTIONS 50 Scaling DGEMM to Multiple Cayman GPUs and Interlagos Many-core CPUs for HPL June 15, 2011

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Technical Report, CALDGEMM and HPL

Technical Report, CALDGEMM and HPL David Rohr, Matthias Kretz, Matthias Bach Frankfurt Institute for Advanced Studies, University of Frankfurt, Germany December 9, 21 Abstract The LOEWE-CSC cluster at