Dariusz Makowski Department of Microelectronics and Computer Science tel

Transcription

1 Dariusz Makowski Department of Microelectronics and Computer Science tel

2 Lecture Agenda Microprocessor Systems, ARM Processors Family Peripheral Devices ARM Processor as Platform for Embedded Programs Methodology of Designing Interfaces in 2

3 Interfaces in 3

4 Fundamental Definitions Computer Memory Electronic or mechanic device used for storing digital data or computer programs (operating system and applications). Peripheral Device Electronic device connected to processor via system bus or computer interface. External devices are used to realise dedicated functionality of the computer system. Internal devices are mainly used by processor and operating system. Computer Bus Electrical connection or subsystem that transfers data between computer components: processors, memories and peripheral devices. System bus is composed of dozens of multiple connections (Parallel Bus) or a few single serial channels (Serial Bus). Interface Electronic or optical device that allows to connect two or more devices. Interface can be parallel or serial. 4

5 Connectivity of Processor and Peripheral Devices Interfaces used in : Parallel Interface PIO (usually 8, 16 or 32 bits), Serial interfaces: Universal Serial Asynchronous Receiver-Transmitter (USART), Serial Peripheral Interface (SPI), Synchronous Serial Controller (SSC) I2C, Two-wire Interface (TWI), Controlled Area Network (CAN), Universal Serial Bus (USB), Ethernet 10/100 Mbits (1 Gbit), Debug/programming interface (EIA RS232, JTAG, SPI, DBGU). 5

6 Interfaces available in AT91SAM9263 Parallel Interface PIO (configurable 32 bits), Serial interfaces: Debug interface (DBGU), Universal Serial Asynchronous Receiver-Transmitter (USART), Serial Peripheral Interface (SPI), Synchronous Serial Controller (SSC), I2C, Two-wire Interface (TWI), Controlled Area Network (CAN), Universal Serial Bus (USB, host, endpoint), Ethernet 10/100 Mbits, Programming interface (JTAG). 6

7 Universal Asynchronous Receiver/Transmitter Module 7

8 EIA RS232 Serial Interface 8

9 UART Transceiver Shift register TxD D0-D7 transmitter Clk D0-D7 Receiver RxD Clk 9

10 Data Frame of UART (1) Mark Space 10

11 Data Frame of UART (2) Send data: b = 0x4B 11

12 Synchronous vs asynchronous transmission Transmitter Receiver Data Clock Transmitter Receiver Internal clock Internal clock Similar reference frequency 12

13 Electrical specification of EIA RS232c 13

14 Null-Modem Cabel EIA

15 Hardware Flow Control Symbol Circuit Line state Remarks Computer ready Modem ready Request to send Ready to send Start transmission DTE Data Terminal Equipment terminal, PC DCE - Data Circuit-terminating Equipment Modem DSR - Data Set Ready - modem DTR - Data Terminal Ready terminal RTS - Request to Send Data CTS - Clear to Send - ready to send data 15

16 Null-Modem Cabel EIA 232 with Hardware flow Control 16

17 Voltage Levels of EIA RS232 Processor output EIA RS

18 Voltage Levels Translator MAX 232 (5 V) MAX 3232 (3,3 V) 18

19 Software for EIA RS232 communication Hyper terminal Minicom ssh Terminal ( 19

20 AT91SAM9263 debug module DBGU (chapter 30) 20

21 Serial interface as Diagnostic Tool Features of DBGU port (DeBuG Unit): Asynchronous data transmission compatible with RS232 standard (8 bits, single parity bit can be switched off), Single system interrupt, shared with PIT, RTT, WDT,DMA, PMC, RSTC, MC, Frame correctness analysis, RxD buffer overflow signal, Diagnostic modes: external loopback, local loopback and echo, Maximum transmission baudrate 1 Mbit/s, Direct connectivity to debug module buildin ARM core (COMMRx/COMMTx). 21

22 Block diagram of DBGU transmission module Input-Output ports Serial Transceiver Interrupt signal 22

23 Transmission speed Reference clock generator is responsible for Baud Rate. Baud rate can be calculated using formula: Baud Rate = MCK / (16 x CD), where CD Clock Divisor can be found in DBGU_BRGR register 23

24 Transmission errors Receiver Buffer Overflow (BGU_RHR) Parity Error (PE) Frame Error (FE) 24

25 Configuration of DBGU transceiver static void Open_DBGU (void){ 1. Deactivate DBGU interrupts (register AT91C_BASE_DBGU->DBGU_IDR) 2. Reset and turn off receiver (register AT91C_BASE_DBGU->DBGU_CR) 3. Reset and turn off transmitter (register AT91C_BASE_DBGU->DBGU_CR) 4. Configure RxD i TxD DBGU as input peripheral ports (registers AT91C_BASE_PIOC->PIO_ASR and AT91C_BASE_PIOC->PIO_PDR) 5. Configure throughput (e.g kbps, register AT91C_BASE_DBGU->DBGU_BRGR) 6. Configure operation mode (e.g. 8N1, register AT91C_BASE_DBGU->DBGU_MR, flags AT91C_US_CHMODE_NORMAL, AT91C_US_PAR_NONE) 7. Configure interrupts if used, e.g. Open_DBGU_INT() 8. Turn on receiver (register AT91C_BASE_DBGU->DBGU_CR), 9. Turn on transmitter if required (register AT91C_BASE_DBGU->DBGU_CR), } 25

26 Read and write via DBGU port Interrupts are disabled. void dbgu_print_ascii (const char *Buffer) { while ( data_are_in_buffer ) { while ( TXRDY... ){}; /* wait intil Tx buffer busy check TXRDY flag */ DBGU_THR =... /* write a single char to Transmitter Holding Register */ } } void dbgu_read_ascii (const char *Buffer, unsigned int Size){ do { While (...RXRDY... ){}; /* wait until data available */ Buffer[...] = DBGU_RHR; /* read data from Receiver Holding Register */ } while ( read_enough_data... ) } 26

27 AT91SAM9263 USART (rozdział 34) 27

28 Serial port USART Features of Universal Synch. Asynch. Receiver-Transmitter: Asynchronous or synchronous data transfer, Programmable frame length, parity, stop bits, Single system interrupt (shared with: PIT, RTT, WDT,DMA, PMC, RSTC, MC), Analysis of correctness of received frames, Buffer overflow error TxD or RxD, Elastic buffer possibility of receiving frames with different length (uses additional counter), Diagnostic modes: external loopback, local loopback and echo, Maximum transmission speed 1 Mbit/s, Hardware flow control, Support for Multidrop transmission data and address, Available Direct Memory Access channel, Support for RS485 differential transmission mode and infrared systems (build-in IrDA modulator-demodulator). 28

29 Block diagram of USART transceiver 29

30 Serial Peripheral Interface 30

31 Serial Peripheral Interface Features of SPI: Serial synchronous transmission, Full duplex, master-slave or master-multi-slave transfers, High data transmission speed (>12 Mbit/s), Application: External peripheral devices (ADC, DAC, RTC, EEPROM, thermometers, etc...), Auxiliary control, e.g. CCD matrix with high speed parallel interface, SPI used for configuration, Memory cards, e.g. SD/SDHC/MMC. 31

32 Serial Peripheral Interface Master Output Slave Input Master Input Slave Output CS Master Slave 32

33 SPI Protocol Clock signal configuration: Clock polarisation: Negative CPOL = 0 (low level, 8 clock signals), Positive CPOL = 1 (high level, 8 clock signals), Clock phase: Zero clock phase (data sampled on first clock slope), Delayed clock phase (data sampled on second clock slope). 33

34 Thermometer with SPI TMP 121: SOT 23-6 package, Maximum clock speed 15 MHz SPI-Compatible Interface Resolution: 12-Bit + Sign, 0,0625 C Accuracy: ±1.5 C for temp. 25 C C Current consumption in sleep mode: 50μA (max.) Power supply: 2,7V to 5,5V 3 mm 34

35 SPI Frame of TMP121 Thermometer 35

36 SPI Module of ARM AT91SAM9263 processor (1) Features of SPI: Support for Master or Slave mode, Receiver and transmitter buffers, Data transfers: from 8 to 16 bits, Four programmable outputs for SPI devices selection (max. 15 devices), Programmable delay between transfers, Programmable clock phase and polarity. 36

37 SPI Module of ARM AT91SAM9263 processor (2) 37

38 SPI Module of ARM AT91SAM9263 processor (3) 38

39 Exam Dates Exam # Exam # Exam # No lecture

40 I2C Bus Standard 40

41 I2C Bus Standard developed by Philips company on early 80s, Two wire synchronous interface (SDA data line, SCL clock line), Bidirectional master-slave (multi-master) transfers, 8-bit frames, Transmission speed: 100 kbps (standard mode), 400 kbps (fast mode), 3,4 Mbps (high-speed mode), 7-bit or 10-bits device address, Synchronisation allows to use devices with different speeds (autonegotiation), Number of devices connected to I2C bus limited by bus capacitance (C=400 pf), Arbitration used for multi-master transmission. 41

42 Application of I2C Bus I²C standard is applied to various digital and analogue devices: PCF8563/8583 clock, calendar, alarm, timer and NVRAM, PCF bit IO expander, PCF8576, PCF8577 LCD controllers, PCF EEPROM memory, 256 bajts (1, 2, 4 kb,... MB), PCF bit, 4-channels ADC/DAC converter. 42

43 I2C Bus Signals Master device initialize transmission, generates clock signal Slave device analyse signals on bus, read address and data 43

44 Transmission Start and Stop Transmission start START signal (falling slope on SDA, change from 1 to 0, during valid clock signal, SCL = 1 ). Signal generated by Master. Transmission end STOP (rising edge on SDA bus, change from 0 to 1 during valid clock signal, SCL = 1 ). Signal generated by Master. 44

45 I2C Protocol A) Transmission initialised by Master, START condition. B) Transmission of 8 bits (7 address bits, 1 R/W bit). C) After 8 bit (clk signals) SDA bus is controlled by Slave (9th clk). Acknowledge is generated to confirm address receive ACK = '0' or not (ACK = 1 ). E) Data read or write phase Master or Slave sends 8 data bits. F) Transmission is finished when ACK signal is generated by data receiver (Master or Slave). Master generates Stop condition. 45

46 I2C Read or Write Master write n-bytes of data 7-bit Master reads n-bytes of data 7-bit 46

47 Two-Wire Interface standard compatible with I2C? ARM processors are equipped with TWI interface compatible with developed by Philips I2C (I2C interface was patented by Philips). Features of TWI interface: Compatible with I2C, Master, Multimaster or Slave modes, IO voltage equal to 3,3 V, Maximum transmission speed: 400 khz, Transfers triggered with interrupts, Automatically Slave mode activated when collision detected on I2C bus (Arbitration-lost interrupt), Interrupt triggered when I2C slave address recognised, Automatic bus busy recognition, Support for 7 and 10-bits addresses. 47

48 Block diagram of TWI module 48

49 Real Time Clock Features of DS1629: Real Time Clock, Build-in thermometer C, Thermometer resolution: 9 bits, Thermometer accuracy +/- 2 C, Thermostat mode, 32 bytes of SRAM, Power Supply 2,2 5,5 V, Interface compatible with I2C (400 khz). 49

50 Real Time Clock 50

51 Real Time Clock I2C Transmission 51

52 Serial Interfaces - comparison 100 m 10 m EIA RS232 1m I2C 10 cm SPI 1 cm 1 kbps 10 kbps 100 kbps 1 Mbps 10 Mbps 100 Mbps 52

53 Universal Serial Bus 53

54 Universal Serial Bus 54

55 Features of USB Asynchronous, serial, differential data transmission, Automatic recognition of connected/disconnected devices, automatic configuration, Single, standardized connector, Up to 127 devices on single bus, Automatic detection and errors correction, Transmission speed: LOW 1.5 Mb/s, specification USB >1.1, FULL 12 Mb/s, specification USB >1.1, HIGH 480 Mb/s, specification USB 2.0, Specification USB 3.0 => 5 Gb/s. 55

56 Data layers of USB Application Device function Data pipe USB driver Control pipe USB interface Logical device USB interface Signal wires USB is designed as a star bus. USB model is composed of three layers: Physial layer, Logical layer, Functional layer. 56

57 Data flow in USB Virtual channels (Pipes) Control channel (EP0) Data channels EP1 EP30 (End Points) 57

58 Physical Layer Differential transmission, half-duplex. Included power supply bus 5 V/500 ma Mini USB USB A and B type 58

59 USB Frame 59

60 Available Transfer Modes 60

61 Bulk and Interrupt Transfer 61

62 Isochronous Transfer 62

63 Control Transfer 63

64 Configuration Enumeration configuration of devices connected to USB bus after connection to disconnection of devices from bus. Enumeration is performed by Master node (address 0). Master assigned individual address to devices connected to USB and configures basic parameters: Device address in USB area, Transfer mode, Transfer direction (read, write, read-write), Size of data packet, Transmission speed, Allocates buffers for virtual channels, Allocated power for connected devices. 64

65 USB Hubs 65

66 USB to I2C converter 66

67 Universal converter RS 232, parallel, SPI, CAN to USB 67

68 USB and ColdFire processors Low\Full speed: MCF 527X (72-75) MCF 5221X (72-75) MCF 5222X (72-75) MCF 527X (72-73) MHz 80 MHz 80 MHz 240 MHz 68HCS08JW32 8 MHz High Speed: MCF 547X (72-75) MCF 548X (82-85) MCF 537X (77-79) MCF MHz MHz 240 Mhz 140 MHz 68

69 Motorola 68HC908JW32 Features of USB module of HC908: Interface compatible with USB 2.0 full speed, 12 Mbps data rate, Build-in 3.3 V regulator, Endpoint 0 with 8-bytes Tx/Rx buffers 64 bytes buffer for endpoints

70 Cypress Processor with USB CY7C68013A Features of CY7C68013: Compatible with USB 2.0 USB-IF high speed, Based on 8051 core, Integrated 16 kb RAM (SRAM) Memory can be loaded from USB, Memory can be loaded from external EEPROM. Four programmable endpoints (BULK/INTERRUPT/ISOCHRONOUS) Additional 64 bytes endpoint (BULK/INTERRUPT), Parallel 8- or 16-bits external interface, DMA channel, GPIF (General Programmable Interface) 70

71 Cypress CY7C68013A processor 71

72 72

73 USB 3.0 Serial high speed, full-duplex interface Data transmission speed: 5 Gb/s (10 more than USB 2.0) Compatible with USB 2.0 (drivers and connector), however significantly differ from USB 2.0 Two channels for full-duplex, power supply Intelligent power supply control, lower power consumption Physical and data layers similar to PCI express

74 Physical Layer of USB