AT17A Series FPGA Configuration EEPROM Memory. Application Note. FPGAs. AT17A Series Conversions from Altera FPGA Serial Configuration Memories

Transcription

1 ATA Series Conversions from Altera FPGA Serial Configuration Memories Introduction The Atmel ATA FPGA Configuration EEPROM () is a serial memory that can be used to load SRAM based FPGAs. This application note describes use of the Atmel in place of the EPC, EPC3, EPC, EPC and EPC devices when used with Altera FPGAs. The Atmel Advantage There are several advantages the Atmel provides, as shown in Table. Table. Having the ability to be In-System Programmed allows changes to designs without incurring the cost of an OTP device after each design modification. This translates into a reduction in development time, cost savings from flexible inventory control and easy field updates. Memory Requirements Memory requirements to program the Altera FLEX000 series of FPGAs is shown in Table. The Atmel ATA Series s have a broader density offering than the Altera EPC family so a more efficient (smaller) Atmel memory can be used in several cases. Atmel ATA Altera EPC () In-System Programmable (ISP) Yes No (3) Reprogrammable Yes No (3) 3.3V Device Availability Yes Yes 3.3V In-System Programming Yes No (3) -pin DIP Yes () Yes () 0-pin PLCC Yes () Yes Cascadable Yes Yes Available as K x Yes No Notes:. Source: Altera Databook (EPC, EPC3, EPC and EPC devices only.). Atmel s 0-pin PLCC ATA Series s are directly pin-compatible with the EPC devices. 3. Reprogrammability limited to EPC device.. Not available for EPC.. The Atmel AT family matches the Altera pinout for -pin DIP. ATA Series FPGA Configuration EEPROM Memory Application Note FPGAs Rev. 0B /

2 Table. Altera FLEX000 to Atmel Device Cross Reference FLEX000 Configuration Bits Altera OTP EPROM Atmel ISP EEPROM EPF 0K EPC ATC/LV(A) EPF K EPC3 ATC/LV(A) EPF3 K EPC3 ATC/LV(A) EPF0 K EPC3 ATC/LV(A) EPF K EPC3 ATC/LV(A) EPF0 0K EPC3 x ATC/LV(A) Note:. To order the -lead PDIP version refer to FPGA Configuration EEPROM: K, K and K (Doc. # 03). Table 3 shows the memory requirements to program the Altera FLEXK series of FPGAs. Table 3. Altera FLEXK to Atmel Device Cross Reference FLEXK Configuration Bits Altera OTP EPROM Atmel ISP EEPROM EPFK K EPC ATC/LVA EPFK0 K EPC ATC/LVA EPFK30 3K EPC ATC/LVA EPFK0 K EPC ATC/LVA EPFK0 0K EPC ATC/LV0A EPFK0 K EPC ATC/LV0A EPFK0 K EPC or EPC x ATC/LV00A or ATC/LV0A x EPFK30 3K EPC or EPC x ATC/LV00A or ATC/LV0A x EPFK00 TBD EPC x or EPC x 3 ATC/LV00A x or ATC/LV0A x 3 EPFK0 TBD EPC x or EPC x ATC/LV00A x or ATC/LV0A x Note:. The EPC is only a,,0 x -bit device; whereas, the ATC/LV00A is a,0, x -bit (true M-bit) device. For the Altera FLEXK series of FPGAs, Table shows the memory requirements for programming using Atmel ATA Series s. Table. Altera FLEXK to Atmel Device Cross Reference FLEXK Configuration Bits Altera OTP EPROM Atmel ISP EEPROM EPF0 K EPC ATC/LVA EPF0 0K EPC ATC/LVA EPF0 0K EPC ATC/LVA

3 Pin Compatibility (-pin DIP) The AT Series s and the Altera EPC/EPC3 parts are pin-compatible in the -pin DIP package. () Following correct device programming, the Atmel can be used in the EPC/EPC3 socket directly without any printed circuit board modifications. Table shows the Atmel configurator pin name against the Altera device pin name. Figure is a pictorial comparison of both -pin DIP packages. Note:. To order the -lead PDIP version, refer to FPGA Configuration EEPROM: K, K and K (Doc # 03). Table. Pin Comparison -pin DIP Device Pin Number Altera -pin DIP Name Atmel -pin DIP Name Compatibility Notes Pin-compatible CLK Pin-compatible 3 (WP) (WP) RESET/ Pin-compatible when Reset polarity is programmed active Low ( active High) in Atmel part CE Pin-compatible GND GND - ncasc CEO (A) Pin-compatible VPP (programming pin) OTP EPROM Programming pin used for ISP in ATA Series s - Figure. The (a) Altera -pin DIP and (b) AT -pin DIP packages ALTERA PINOUT ATMEL PINOUT (WP) 3 VPP ncasc GND CLK (WP) RESET/ CE 3 CEO (A) GND (a) (b) 3

4 Pin Compatibility (0-pin PLCC) The ATC00A/ATC0A/ATCA are pin-compatible with the EPC/EPC/EPC devices. The ATCA/ATCA/ATCA are pin-compatible with the EPC/EPC3 devices. Table. Pin Comparison 0-pin PLCC Device Pin Number Altera 0-pin PLCC Atmel 0-pin PLCC Compatibility Notes TDO - Optional feature in Altera EPC part Pin-compatible 3 TCK - Optional feature in Altera EPC part Pin-compatible WP Optional feature in Atmel part A/0A SEL - Optional feature in Altera EPC part Pin-compatible when reset polarity is programmed active Low ( active High) in Atmel part Pin-compatible GND GND TDI - Optional feature in Altera EPC part ncasc ncasc (A) Pin-compatible 3 ninit_conf - Optional feature in Altera EPC part VPPSEL - Optional feature in Altera EPC part READY Optional feature in Atmel part VPP (programming pin) OTP EPROM programming pin used for ISP in ATA Series s TMS - Optional feature in Altera EPC part 0 Figure. The (a) Altera 0-pin PLCC and (b) ATA Series 0-pin PLCC packages. 3 0 GND ncasc 3 ALTERA WP 3 0 ATMEL "A" PARTS READY GND (A) ncasc 3 (a) (b) Notes:. ATC/LVA and ATC/LV0A devices are only available in the 0-pin PLCC package outline.. The reset polarity of the Atmel device must be programmed active Low ( active High) for use in Altera FPGA applications. 3. Altera pinout applies to EPC//3/ and mandatory features of EPC only.. WP is available on ATCA/ATC0A.

5 Replacing Altera s EPC OTP EPROMs with the ATA Series Configuration EEPROMs The Altera EPC devices can be replaced by Atmel ATA Series Configuration EEPROMs by translating the Altera programming files for use with Atmel programming algorithms. To facilitate this process, Atmel provides a conversion utility, CPS (available free of charge from which supports Windows, Windows, and Windows NT operating systems. This software outputs an Intel (MCS-) Hex file which can be read into industry-standard programmers. The software, in conjunction with Atmel s ATDH00E Programming Kit, can be used to download an Altera programming file directly to Atmel (s). Drop-in Applications The ATA Series s can be used directly in Altera FPGA applications. The examples shown in the following pages demonstrate the ease with which Atmel s can be used in place of Altera OTPs for the primary benefit of reprogrammability. Each of the Drop-in Applications (Figure 3, Figure and Figure ) are similar to those corresponding to the use of the Altera OTP parts. Exceptions exist in Figure and Figure, where an RC delay is recommended for use on the input to the pin; in order to emulate the 0 ms to 00 ms delay normally introduced on the line by the Altera OTP. This delay allows the system voltage to rise to within the normal operating range before allowing an FPGA configuration session. Figure 3. Drop-in Replacement of the EPC/EPC3 in an Altera FLEXK Application ns/p EPFK 0 ATC(A)/(A)/(A) ATLV(A)/(A)/(A). Reset polarity must be set active Low.

6 Figure. Drop-in Replacement of the EPC/EPC/EPC in an Altera FLEXK/K Application nce EPFK 0 ATCA/0A/00A ATLVA/0A/00A. Applicable to EPFK. 3. Reset polarity must be set active Low.. RC filter recommended for input to to delay configuration until is stable. ( can instead be connected to an active Low system reset signal.) Figure. Drop-in Replacement of Cascaded EPC/EPC/EPC OTPs in an Altera FLEXK Application nce EPFK 0 ATCA/0A/00A ATLVA/0A/00A Device ncasc ATCA/0A/00A ATLVA/0A/00A Device. Reset polarity must be set active Low. 3. RC filter recommended for input to to delay configuration until is stable. ( can instead be connected to an active Low system reset signal.)

7 In-System Programming Applications The ATA Series s are In-System (re)programmable (ISP). The examples shown in the following pages support the following programmer functions:. Read the Manufacturers Code and the Device Code (K and M parts only). Program the device 3. Verify the device. Set the Reset Polarity option While Atmel s FPGA s can be programmed from various sources (e.g., on-board microcontrollers or PLDs), the applications shown here are designed to facilitate users of our ATDH00 programming board and CF.exe download utility. For in-system programming (ISP), the ATDH00 board is used as a programming interface between the PC and the target board. Instead of populating the CXXX socket, the configurator(s) would be located on the target board. Communication to and from the configurator(s) would be accomplished via an ISP cable connected between the target board and the U header. File conversion and download is performed similar to the procedure described in the previous sections, but may require user intervention and additional chip select decoding circuitry/logic when targeting three or more devices on a given target board. The standard ISP system is shown below. Figure. ATDH00 ISP Programming Interface Board PC Target System Parallel Port Parallel Cable ATDH00 FPGA FPGA DB-M DB-F -pin Ribbon Cable In-System Programming Connector Header ATA

8 Altera Applications Altera FLEX devices (e.g., EPFK, EPFK, EPFK) can be configured with any ATA Series s. However, high-density ATA Series s (K and M-bit storage) introduce a simplified 3-wire interface that is highly desirable for ISP applications. For high-density or a-chained FPGAs, the ATA s can be cascaded to provide the necessary memory. Figure and Figure employ the low-density ATA for a single EPFK and EPFK device, respectively. The multiplexer IC (HC(T)) connects the configurator signals to either the FPGA or the ISP header. The pull-down resistor on the A input pin of the configurator provides the required addressing for the incoming bitstream messages during programming. To target a specific configurator on the shared serial bus, the A bit from the programmer must match the level on the A input pin of the intended recipient. For users of Atmel s CF utility, the A bit can be modified using the /J <L H> switch. Next, serves as a control signal for the multiplexer select input and determines the operational mode of the EEPROM. For the low-density ATA s, control of the and pins is necessary for the programming of user data and setting of the reset polarity. Figure. ISP of the ATC(A)/(A)/(A) in an Altera FLEXK Application ATC(A)/(A)/(A) ATLV(A)/(A)/(A) EPFK Y Y 3Y Y E HC(T) S A B A B 3A 3B A B 3 3 ncasc (A) ns/p 0 3. Reset polarity must be set active Low.

9 Figure. ISP of the ATC(A)/(A)/(A) in an Altera FLEXK Application ATC(A)/(A)/(A) ATLV(A)/(A)/(A) EPFK Y Y 3Y Y E HC(T) S A B A B 3A 3B A B 3 3 ncasc (A) nce MSEL 0 3 EXT_CLK. Applicable to EPFK. 3. Reset polarity must be set active low.. RC filter recommended for input to to delay configuration until is stable. ( can instead by connected to an active Low system reset signal.)

10 While the input pin can be connected directly to, we recommend the use of an RC delay or connection to an active Low system reset signal for Altera FLEXK/K applications. This ensures that the has entered into the normal operating levels prior to the start of configuration. Since the low-density ATA Series s cannot provide the necessary clock signal (i.e. act as system master) during configuration, a clock must be supplied externally or from the FPGA. The complexity of the ISP circuit is significantly reduced with the high-density ATA s as shown in Figure and Figure. The diode connection between the EPFK s pin and the signal allows the external programmer to force the FPGA into a reset state during ISP. This eliminates the potential for contention on the line. The READY pin (optional feature) of the configurator can also be connected to the FPGA s pin to force the FPGA to remain in a reset state as the configurator completes its power on reset cycle. For the Altera FLEXK application in Figure, the internal oscillator of the high-density ATA must be disabled. This needs only to be performed once before device insertion, or during ISP by connecting to the ISP header (not shown). Figure. ISP of the ATCA/0A in an Altera FLEXK Application 3 EPFK ATCA/0A ATLVA/0A ns/p 0 READY. The internal oscillator of the ATA is disabled. 3. Reset polarity must be set active Low.. Use of the READY pin is optional.

11 Figure. ISP of the ATCA/0A/00A in an Altera FLEXK/K Application 3 nce EPFK 0 ATCA/0A/00A ATLVA/0A/00A ncasc(a) READY. Applicable to EPFK. 3. Reset polarity must be set active Low.. Use of the READY pin is optional.. RC filter recommended for input to to delay configuration until is stable. ( can instead be connected to an active Low system reset signal.). The pull-up resistor on ncasc (A) is required only for the ATC/LV00A; it is otherwise optional.

12 The dedicated WP pin for the ATCA/0A if left unconnected, has a weak internal pull-down resistor that safely disables the write protection feature of these configurators. Similarly, an external pull-down resistor is not required on the A input during ISP since there is a weak internal pull-down resistor present on that pin. In simple cascaded configurator applications involving two EEPROMs (Figure ), the A input can be used as an addressing pin (set to logic level 0 for one EEPROM and logic level for the other EEPROM). The programming utility can then modify the A bit sent in the bitstream messages to target either of the two EEPROMs. Applications involving more than two EEPROMs must use the A input pin as a chip select. Pull-up resistors on each A input is required, in addition to an external decoder circuit which must be able to selectively drive each A input Low. For further details please refer to the Programming Cascaded s application note. Figure. ISP of Two Cascaded ATCA/0As in an Altera FLEXK Application 3 nce EPFK 0 ATCA/0A ATLVA/0A Device ncasc (A) READY ATCA/0A ATLVA/0A Device ncasc (A) READY. Use of the READY pin is optional. 3. Reset polarity must be set active Low.. RC filter recommended for input to to delay configuration until is stable. ( can instead be connected to an active Low system reset signal.). This circuit cannot be used with the ATC/LV00A

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