NX-51 V2 plus experiment board Documentation 1. NX-51 V2 plus. P89V51RD2 microcontroller Eexperiment board. Documentation

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1 NX- V plus experiment board Documentation NX- V plus PVRD microcontroller Eexperiment board Documentation

2 NX- V plus experiment board Documentation

3 NX- V plus experiment board Documentation. About PVRD microcontroller The PVRD is an 0C microcontroller with kb Flash and 0 bytes of data RAM. A key feature of the PVRD is its X mode option. The design engineer can choose to run the application with the conventional 0C clock rate ( clocks per machine cycle) or select the X mode ( clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to benefit from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the EMI. The Flash program memory supports both parallel programming and in serial In- System Programming (ISP). Parallel programming mode offers gang-programming at high speed, reducing programming costs and time to market. ISP allows a device to be reprogrammed in the end product under software control. The capability to field/update the application firmware makes a wide range of applications possible. The PVRD is also In-Application Programmable (IAP), allowing the Flash program memory to be reconfigured even while the application is running. Features of PVRD can detail as : 0C Central Processing Unit V Operating voltage from 0 to 0 MHz kb of on-chip Flash program memory with ISP (In-System Programming) and IAP (In-Application Programming) Supports -clock (default) or -clock mode selection via software or ISP SPI (Serial Peripheral Interface) and enhanced UART functions PCA (Programmable Counter Array) with PWM and Capture/Compare Four -bit I/O ports with three high-current Port pins ( ma each) Three -bit timers/counters Programmable Watchdog timer (WDT) Eight interrupt sources with four priority levels Second DPTR register Low EMI mode (ALE inhibit) TTL- and CMOS-compatible logic levels Brown-out detection Low power modes Power-down mode with external interrupt wake-up Idle mode PDIP0, PLCC and TQFP packages

4 NX- V plus experiment board Documentation The pin assignment of PVRDBN is shown in figure. P.0/T 0 +Vcc P./TEX P0.0/AD0 P./ECI P0./AD P./CEX0 P0./AD P./CEX P0./AD P./CEX P0./AD P./CEX P0./AD P/CEX P0./AD RESET P0./AD P.0/RxD P./TxD 0 PVRD 0 EA/Vpp ALE/PROG P./INT0 PSEN P./INT P./A P./T0 P./A P./T P./A P./WR P./A P./RD P./A XTAL P./A0 XTAL P./A GND 0 P.0/A Figure PVRD pin assignmet in DIP package

5 NX- V plus experiment board Documentation Pin name Pin Type Description Vcc 0 Input Supply GND 0 Input Ground P0.0-P0. - Input/Output Port 0 is an -bit open drain bi-directional I/O port. Port 0 pins that have s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. In this application, it uses strong internal pull-ups when transitioning to s. Port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode verification. External pull-ups are required during program verification or as a general purpose I/O port. P.0-P. - Input/Output Port is an -bit bi-directional I/O port with internal pull-ups. As inputs, Port pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. P., P., P. have high current drive of ma. Port also receives the low-order address bytes during the external host mode programming and verification. - Timer adn SPI (Serial Peripheral Interface) port function as : T (P.0 : pin ) External count input to Timer/Counter or Clock-out from Timer/Counter TEX (P. : pin ) Timer/Counter capture/reload trigger and direction control ECI (P. : pin ) External clock input. This signal is the external clock input for the PCA. CEX0 (P. : pin ) Capture/compare external I/O for PCA Module 0. CEX/SS (P. : pin ) Capture/compare external I/O for PCA Module and Slave Select in SPI CEX/MOSI (P. : pin ) Capture/compare external I/O for PCA Module and SPI Master Output Slave Input CEX/MISO (P. : pin ) Capture/compare external I/O for PCA Module and SPI Master Input Slave Outpu CEX/SCK (P. : pin ) Capture/compare external I/O for PCA Module and SPI clock P.0-P. - Input/Output Port is an -bit bi-directional I/O port with internal pull-ups. P.0-P. 0- Input/Output P. with internal pull-up Port is an -bit bidirectional I/O port with internal pull-ups. Port pins are pulled HIGH by the internal pull-ups when s are written to them and can be used as inputs in this state. As inputs, Port pins that are externally pulled LOW will source current (IIL) IIL) because of the internal pull-ups. Port also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. - Support many special function port as : RxD (P.0 : pin 0) serial input port TxD (P. : pin ) serial output port INT0 (P. : pin ) external interrupt 0 input INT (P. : pin ) external interrupt input T0 (P. : pin ) external count input to Timer/Counter 0 T (P. : pin ) external count input to Timer/Counter WR (P. : pin ) external data memory write strobe RD (P. : pin ) external data memory read strobe RESET Input Reset by the external logic "" at least machine cycle. While the oscillator is running. ALE 0 Output ALE is the output signal for latching the low byte of the address during an access to external memory. PSEN Output PSEN is the read strobe for external program memory. When the device is executing from internal program memory, PSEN is inactive (HIGH). When the device is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. A forced HIGH-to-LOW input transition on the PSEN pin while the RST input is continually held HIGH for more than 0 machine cycles will cause the device to enter external host mode programming. - For PVRD connect this pin to ground, apply logic "" at P. and apply at EA/Vpp pin. EA/Vpp Input EA must be connected to VSS in order to enable the device to fetch code from the external program memory. EA must be strapped to VDD for internal program execution. However, Security lock level will disable EA, and program execution is only possible from internal program memory. The EA pin can tolerate a high voltage of V. XTAL Input Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL Output Output from the inverting oscillator amplifier. Table - Summary of pin function of PVRDBN microcontroller

6 NX- V plus experiment board Documentation. NX- Vplus : PVRD MCS- microcontroller experiment board. Features : Support Philips s PC(V)Rx (PVRDBN on-board) Clock.0MHz In -system programming via serial port Select PROGRAM with a switch On-board x LCD module -LEDs and -digit LED segments Piezo speaker x Matrix switch Relay and stepper motor driver circuit DS0 -wire Temperature IC DS0 Real-time clock IC -Interrupt switch l RS- interface PCFA I/O expander IC C SEEPROM on-board D/A converter R-R ladder I C bus-based ADC ch. and DAC by PCF Connecter for Timer and PCA module Port can select mode : P or Timer and PCA Use with DC adapter+v 00-00mA Polarity protection circuit

7 NX- V plus experiment board Documentation LED RUN LED PGM R 00k C./0V IC C 0.0/0V RST C 0./0 0 IC DS0 K SERIAL PORT K DC INPUT + - R.k C-C 0/0V C K ANALOG OUTPUT ~ ~ + - C R 0k R 0k R 0k R 0k R 0k R 0k R0 0k R 0k BD N00 x C C 0/ R 0k R 0k R 0k R 0k R 0k D R 0k C IC MAX R 0kD R 0k S MODE D D D D D D0 0 C 0./0 R 0 R 0 C R-R 0k x INT0 INT GND K INTERRUPT INPUT K0 TIMER0 INPUT IC 0 S-S Keypad x T0 GND 0 Q Q Q Q Q Q Q Q0 R S * 0 # D D D D D D D D0 0 IC0 HC C 0./0 S RESET C 0./0 R S R-R k x R P0. P0. P0. P0. P0. P0. P0. P0.0 R-R select R.k R 0 LED POWER R R0 TxD RxD INT0\ INT\ T0 R EA/Vpp P. 0 P.0 P. P. P. R 0 C pf PSEN P. P.0 P. P. P. P. P. P. P0. P0. P0. P0. P0. P0. P0. P0.0 IC PCRD P. P. P. P. P. P. P.0 P. XTAL.0MHz P. P. P. C pf C 0./0V P0. P0. P0. P0. P0. P0. P0. P0.0 IC HC P0. P0. P0. P0. P0. P0. P0. C 0./0 P0.0 IC HC DRIVER select D D D D D D D D0 0 0 D D D D D D D D0 0 0 DSP common line JP JP JP DSP ECI (PCA) SDA T TEX CEX ECI K PCA PORT R 0k x Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q0 DQ DQ DQ DQ DQ0 R k R k R/W E R-R 0x R 0 DQ T T EX RS D D D D D D D D BATT V GND K TIMER PORT dp g f e d c b a R-R 0x +B DSP LCD x SP PIEZO C pf SDA LED LED LED LED LED LED LED LED VR 0k DSP-DSP LED SEGMENTS COMMON CATHODE DSP IC DS0 com XTAL.kHz Q BC SDA C0 pf VR-VR 0k x R k CLK DSP com Q BC A0 A A IC PCF AG I I I I DQ DQ DQ DQ DQ0 SDA 0 Aout IC PCFA +V +Vref JP-JP ADC test R-R k SDA A A A0 SDA A A A0 C 0./0 +V RY RELAYV WP + - IC ULN00 +V (+Vmotor) PHASE K PHASE STEPPER MOTOR PHASE OUTPUT PHASE GND JP DRIVER ENABLE P P P P P P P P0 0 K ANALOG OUTPUT K ANALOG INPUT R/ k x R/ k x R R R R0 R-R0 0 x IC C/LC D D D D0 D D D D0 S DIP SW. x LED LED0 LED LED SDA GND NO K C RELAY OUTPUT NC K I C BUS Figure NX- V plus experiment board schematic diagram. Flash Magic software The ISP software that use with NX- V plus board is Flash Magic V.0 or higher. You can download the latest version at After downloaded, install to your computer that have Windows SE or higher. Before using this software, must connect the experiment board with computer s serial port. The figure shows the main window of Flash Magic software. The main window has setting boxes. Each box has number indentify. This number means step of operation. You must set in the order from box to. Start by select the interface COM port, select the eraseing memory, select the target file, select some option and click the start button. in the last. However you can select the operation via menu bar. Read mre information in the PDF file manual in same folder that contain this software.

8 NX- V plus experiment board Documentation ร ปท - หน าต างหล กของโปรแกรม Flash Magic Figure The main window of Flash Magic software in PVRD selection. How to use Flash Magic with NX- v plus experiment board () Connect the experiment board with RS- serial port by serial cable. If your computer has only USB port, do not worry. You can use USB to serial port adapter. We recommend UCON- board. See more detail at () Make sure not have any software that operate with Computer s serail port. () Because using PVRDBN on this experiment board, the MODE switch does not use. You must set the switch into RUN mode only. A green LED will on. () Run the Flash Magic software. The title page will appear in a moment. After that the main window will appear and has the message Attempting to connect... at status bar in the bottom of window. If the error dialogue box in the figure appears, it means the experiment board cannot interface with flash Magic software. Click the Cancel button to continue.

9 NX- V plus experiment board Documentation Figure The error dialogue box about interface between PVRD microcontroller and Flash Magic software () At the Setting Box, select the COM port interface, Baudrate as 00 and select Microcontroller number to VRD. memory. () At the Setting BOX, check the Erase all flash box for erasing all flash program () Select the target HEX file in the Setting Box.

10 0 NX- V plus experiment board Documentation () In the Setting Box, user can select any parameter or not select. However suggess to select at the Verify after programming. For PVRD microcontroller that bundled with NX- V plus experiment board will pre-programmed the clks/cycle mode from manufacturer. Thus, all timing in your code must adjust to relate with clks/cycle. It means the speed will faster time compare the 0 original. PVRD cannot select back to clks/cycle via ISP procudure. If you need to set back must use the Parallel programmer such as ALL- from Hi-Lo system. () Select all P SELECTION jumpers to suitable circuit. () Click Start button in the Setting Box to start the downloading. The warning dialogue box in the figure will apeear. The box infrom you to reset the experiment board to enter the ISP mode. Apply the supply voltage in this moment or if the board is applied the supply voltage before, press RESET switch on the experiment board instead. Do not click Cancel button. After that that dialogue box will close automatically and enter to ISP mode with the download process will happen suddenly. (0) After the downloading is finished, press RESET switch on the experiment board agin to run the program.

11 NX- V plus experiment board Documentation Figure The Reset Device dialogue appear at the middle of main window to inform user to reset the hardware for entering ISP mode.. The MCS- CD-ROM information The CD-ROM that bundled with NX- V plus experiemnt board is contained many software and experiment codes.. Code for Experiment folder : contains all experiment, for PVRD experiment enter to folder VLab_sourcecode. You will found experiment.. INCLUDE folder - contains all header and library that use in all.. Lxxxx - xxxx means number of experiment file. Start from 00 to 0. All C project file of all experiment developed with Rkit- by Raisonance. You can download evaluation version free of charge at All experiment can compile under the evaluation version.. Software folder : contains the variety of software tool for develope MCS- microcontroller. The softwares that use in all experiment code from.. are :.. RKIT BN folder - contains Rkit- in evaluation version... FlashMagic.xx - contains the Flash Magic V. or higer.

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