RL78 Serial interfaces

Transcription

1 RL78 Serial interfaces Renesas Electronics A

2 Introduction Purpose This course provides an introduction to the RL78 serial interface architecture. In detail the different serial interfaces and their usage are explained. Objective Learn about the RL78 serial interface structure and their capabilities. Content 28 pages (including this page) x questions Learning Time 20 minutes 2

3 Serial Array Unit 3

4 Serial Array Unit overview The serial array unit is the unique serial interface supporting CSI clock synchronous interface UART Simplified I2C Up to three Serial Array Units are available Each serial array unit has up to four channels Channels could be used independently for CSI and simplified I 2 C or in combination in case of UART R5F100LE The access by the DMA Controller is supported 4

5 Serial Array Unit usage example The number of serial interfaces available on each device may differ depending on the flash size and the pin count of the device. Below you will find examples of the usage for a R5F100LE (64 pin,64k) 2 x UART and 2 x CSI 1 x UART and 2 x CSI and 2 x simplified I2C 3 x UART R5F100LE 5

6 Serial Array Unit Block diagram Block Diagram Global clock select Global control block Channel n 6

7 Serial Array Unit CSI mode 3-wire serial I/O Data transmission/reception Data length of 7 or 8 bits Phase and Level control of transmit/receive data MSB/LSB first selectable Clock control Master/slave selection Phase control of I/O clock Setting of transfer period by prescaler and internal counter of each channel Max speed fclk /2 for master mode CSI00 Max speed fclk /6 for slave mode CSI00 Interrupt function Transfer end interrupt Buffer empty interrupt Error detection flag Overrun error 7

8 Serial Array Unit UART UART Full-duplex UART communication can be realized by using two channels, one dedicated to transmission (even channel) and the other to reception (odd channel) Data transmission/reception Data length of 7,8 or 9 bits Select the MSB/LSB first Level setting of transmit/receive data Parity bit appending and parity check functions Stop bit appending Interrupt function Transfer end interrupt/buffer empty interrupt Error interrupt in case of framing error, parity error, or overrun error 8

9 Serial Array Unit baud rate setting Baud rate will be defined by Operation clock fmck of target channel and Upper 7 bits of the SDR register Example of baud rate 32MHz 9

10 Serial Array Unit I 2 C Simplified I 2 C Designed for single communication with a device such as an external EEPROM, some RF parts, Master mode only (No support for Slave mode) No wait state detection Data transmission/reception Master transmission, master reception ACK output and ACK detection functions Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) Manual generation of start condition and stop condition Interrupt function / Error detection flag Transfer end interrupt / Parity error (ACK error) Functions not supported by simplified I 2 C Slave transmission, slave reception Arbitration loss detection function Wait detection functions 10

11 Serial Array Unit Snooze Mode The serial array unit is supporting the SNOOZE mode on the following channels SNOOZE mode capable >= 96K devices will also support SNOOZE mode on UART2 Snooze Mode allows data reception directly from the stop mode Baud rate is limited to 9600 baud (target) Wake up in case of valid reception Directly back into STOP mode in case of reception error 11

12 Serial Array Unit Snooze Mode example Wake up from SNOOZE by valid reception 12

13 Serial Array Unit LIN support LIN-bus functions UART2 Wakeup signal detection Sync break field (SBF) detection Sync field measurement for baud rate calculation External interrupt (INTP0) and timer array unit TAU0 channel 7 is used Connections are prepared internally ISC register 13

14 Serial Array Unit DMA support DMA can be used for a background block transfer with the serial interface Example of an high speed CSI transfer CPU 1. Setup data 3. Start DMA 5. Interrupt to CPU that block transfer is 2. Start interface finished Data0 DataX RAM Data to be sent DMA 0 4. Interrupt trigger DMA To receive /sent next data SDR Serial Array Unit SCK SO SI DMA 1 SDR 14

15 Serial Array Unit CSI and DMA example Example for Master Transmit/Receive mode Single Transmission/Reception mode Start of transmission directly by CPU INTCSI will trigger DMA and process receive and transmitt data CPU not involved 15

16 IICA Interface 16

17 Features of IICA interface Number of channels depends on the device I 2 C features Supports Master Slave Multi-master mode Compliant to I 2 C-bus specification Wake up from STOP mode Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0 requires pull-up resistors for the serial clock line and the serial data bus line. 17

18 I2C Interface Block Diagram 18

19 I2C Interface Since the SCL0 and SDA0 pins are open drain outputs, IIC0 requires pull-up resistors for the serial clock line and the serial data bus line 19

20 Thank You Renesas Electronics Europe