AT90SO72 Summary Datasheet

Transcription

1 AT90SO Summary Datasheet

2 Features General High-performance, Low-power -/-bit Enhanced RISC Architecture Microcontroller - Powerful Instructions (Most Executed in a Single Clock Cycle) Low Power Idle and Power-Down Modes Internal Variable Frequency Oscillator up to Mhz Bond Pad Locations Conforming to ISO - ESD Protection up to ± 000V Operating Range:.V to.v Operating Temperature: -0 C to +0 C Available in Wafers, Modules and standard ROHS packages: - 0-QFN (RoHS compliant) mm x mm - -SOIC (RoHS compliant) mm x mm Memory K Bytes of ROM Program Memory including K Bytes of Crypto ROM K Bytes of EEPROM, including OTP Bytes and Bit-addressable Bytes - to -byte Program / Erase - ms Program / ms Erase - Typically 00,000 Write / Erase Cycles at a Temperature of C - Typically 00,000 Write / Erase Cycles at a Temperature of 0 C - 0 Years Data Retention K Bytes of RAM Memory (K Bytes of RISC CPU RAM, K Bytes of Cryptographic Accelerator RAM, shared with the RISC CPU core) Communication USB.0 Full Speed Interface - Programmable Endpoints with IN or OUT Directions for Bulk, Interrupt or Isochronous Transfers ( endpoints with double buffering of x bytes) - DMA ler for fast transfers between internal DPRAM to RAM - MHz clock for Full-speed Bus Operation USB.0 Low Speed Interface - No external resonator required Master / Slave SPI Serial ler I²C (Two Wire Interface) up to 00 Kbits/s - Multiple Masters supported Other Peripherals Hardware Communication Interface Detection Up to General Purpose I/Os multiplexed with SPI and I²C interfaces Programmable Internal Oscillator (Up to MHz for CPU and Crypto Accelerator) Two -bit Timers Random Number Generator (RNG) -level Interrupt ler Hardware DES/TDES Engine DPA/DEMA Resistant Hardware AES /9/ Engine DPA/DEMA Resistant Checksum Accelerator CRC & Engine (Compliant with ISO / IEC 09) -bit Cryptographic Accelerator (Ad-X for Public Key Operations) - RSA, DSA, ECC, Diffie-Hellman, Key Generation (thanks to Crypto Toolbox Library) 9CS Sep AT90SO Summary

3 Security Dedicated Hardware for Protection Against SPA/DPA/SEMA/DEMA Attacks Advanced Protection Against Physical Attack, including Active Shield, Enhanced Protection Object, CStack Checker, Slope Detector, Parity Errors Environmental Protection Systems Voltage Monitor Frequency Monitor Temperature Monitor Light Protection Secure Memory Management/Access Protection (Supervisor Mode) Development Tools Voyager Emulation Platform (ATV+) to Support Software Development IAR Embedded Workbench V.0 Debugger or Above Software Libraries and Application Notes Certifications / Standards CC EAL+ (Ready) USB.0 Description The AT90SO is a low-power, high-performance, -/-bit microcontroller with ROM program memory, EEPROM memory, based on RISC architecture microcontroller. By executing powerful instructions in a single clock cycle, the AT90SO achieves throughputs close to MIPS per MHz. Its Harvard architecture includes general-purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one single instruction executed in one clock cycle. In addition to the K Bytes of embedded ROM, the AT90SO includes K Bytes of high density EEPROM. The ability to map the EEPROM in the code space allows parts of the program memory to be reprogrammed in-system. This technology combined with the versatile /-bit CPU on a monolithic chip provides a highly flexible and cost-effective solution to many applications. The USB V.0 Full Speed controller provides a dynamic pull-up attachment and detachment and a host detection mechanism. The AT90SO features also a USB.0 Low Speed interface which does not require an external resonator. The USB interface provides six configurable data transfer endpoints, each with its own DPRAM in the memory area. The data transfer type for each endpoint is configured by software. A DMA controller allows a fast communication rate between the RAM of the CPU and the DPRAM. The SPI interface, when configured as a master, provides a clock up to 0MHz thanks to the dedicated internal VFO clock system. The SPI controller features three sources of interrupt (Byte Transmitted, Time-out and Reception Overflow) and a programmable clock and inter-bytes (guardtime) delays. The I²C interface interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 00 Kbits per second, based on a byte-oriented transfer format. It is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. Arbitration of the bus is performed internally and puts the I²C in slave mode automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. 9CS Sep AT90SO Summary

4 Figure AT90SO RISC RISC CPU Core Architecture Data Bus -bit AES DES/TDES Reset Circuit RST OTP EEPROM User Memory Access RNG Ad-X Crypto Processor Secure PC CRYPTO ROM Program Memory Instruction Register Instruction Decoder Lines General Purpose Registers X Y Z ALU Status Registers Access RAM Data Memory Interrupt Unit USB.0 ler I²C ler SPI ler SCL SS VDD_osc (.V max) XOUT SDA / GPIO0 SS / SCL / GPIO MOSI / GPIO MISO / GPIO / A SCK / GPIO / A GPIO 0.. GPIO (input only) / A0 Timer 0 Timer GPIO (input only) / ISO_CLK CRC CSM DPA Counter Measures List of pins A0, A, A I²C address bits (A0 as input only) Ground (reference voltage) GPIOx General Purpose Input or Output ISO_CLK Clock signal input to internal clock operating circuit MISO SPI Master Input / Slave Ouput MOSI SPI Master Output / Slave Input RST Reset pin SCL Clock Signal for Serial (I²C) SDA Input or Output for serial data (I²C) SS SPI Slave Select SCK Clock signal for the SPI USB differential data USB differential data Power supply input VDD_osc Power supply input for Internal Oscillator (.V max) Oscillator signal input to generate internal clock operating circuit (.V max) Resonator signal input to generate internal clock operating circuit XOUT Resonator signal output to generate internal clock operating circuit Ordering information Reference Description xxx : Chip Personalization Number* AT90SO-xxx-P P = Z : QFN0 Package R : Package * For more details about the Chip Personalization Number, please contact your local INSIDE Secure sales office. 9CS Sep AT90SO Summary

5 Pinouts & Packages Pinouts Information Configuration Interfaces available (multiplexed) Package - USB Full Speed (External Resonator required) - USB Low Speed - USB Low Speed - USB Full Speed (External Oscillator required) - USB Low Speed - USB Full Speed (External Resonator required) - SPI - USB Full Speed - SPI - SPI - ISO QFN0 QFN0 Figure AT90SO pinout configuration Figure AT90SO pinout configuration GPIO GPIO / SCL GPIO / SCL GPIO0 / SDA AT90SO XOUT GPIO0 / SDA AT90SO (.V max) 9CS Sep AT90SO Summary

6 Figure AT90SO pinout configuration Figure AT90SO pinout configuration XOUT 0 9 AT90SO QFN0 GPIO0 / SDA GPIO / SCL / SS GPIO / MISO GPIO / MOSI GPIO / SCK GPIO / MOSI GPIO / SCL / SS AT90SO GPIO / MISO 9 0 GPIO0/ SDA GPIO / SCK Figure AT90SO pinout configuration Figure AT90SO pinout configuration 0 9 ISO_CLK / GPIO GPIO GPIO0 AT90SO GPIO VDD_osc GPIO / A0 GPIO / A AT90SO QFN0 A / GPIO SDA / GPIO0 SCL / GPIO 9 0 The photographs and information contained in this document are not contractual and may be charged without notice. Brand and product names may be registered trademarks or trademarks of their respective holders. Note: This is a summary document. A complete document will be available under NDA. For more information, please contact your local WiseKey sales office. 9CS Sep AT90SO Summary