Optimal Management of System Clock Networks

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2 Optimal Management of System Networks 2002

3 Introduction System Management Is More Challenging No Longer One Synchronous per System or Card Must Design Source-Synchronous or CDR Interfaces with Multiple Domains Higher Speeds Increase Importance of Timing & Jitter Analysis

4 Agenda Examine Communications Line Card Design Examples Identify & Solve ing Challenges Examine System ing Schemes Jitter Discussion

5 Line Card Example FPGA Takes on Central Interface Role Host Processor HyperTransport Optical/ Electrical Converter SFI-4 Framer SPI-4.2 w/dpa FPGA XAUI Backplane Connector DDR Interface SDRAM

6 Line Card Example (Con t) FPGA Takes on Central Interface Role HyperTransport Interface Data Host Processor Optical/ Electrical SPI-4.2 Converter Interface Data SFI-4 Framer SPI-4.2 w/dpa FPGA Custom Logic HyperTransport Data XAUI Backplane XAUI Connector Interface Data SDRAM DDR SDRAM Interface DDR Interface

7 Stratix ing Solutions Stratix Device Incorporates up to 48 Trees Implement FIFOs with TriMatrix Memory HyperTransport Interface Data Data FIFO Data SPI-4.2 Interface FIFO Custom Logic FIFO XAUI Interface FIFO Data DDR SDRAM Interface

8 System Schemes Source-Synchronous Interface SFI-4 (SERDES-to-Framer Interface Level 4) HyperTransport Technology Dynamic Phase Alignment (DPA) SPI-4.2 (System Physical Interface Level 4.2) -Data Recovery XAUI (10 Gigabit Attachment Unit Interface)

9 Source-Synchronous ing Signal Transmitted with Data Board Skew Reduces System Performance Source Data Data Destination

10 Source-Synchronous Benefits Source-Synchronous ing Enables Data Transfer at High Speeds Performance No Longer Limited by t CO, t PD & t SU Maximum Performance Factors Edge Rate of Driver Skew between Data Signals & Signals

11 Source-Synchronous Drawbacks Every Chip-to-Chip Data Transfer Introduces New Domain Receiver Must Manage Multiple Domains Performance Affected by Board Skew Skew Reduction Complicates Board Design

12 Source-Synchronous Interfaces Transmission Line Type HyperTransport SFI-4 SPI-4 RapidIO Channel Data Rate 1.6 Gbps MBPS MBPS 2.0 Gbps 800 MHz MHz MHz 1.0 GHz

13 Need for DPA In -Forwarding System, -Data Skew Reduces Performance SPI-4.2 Sample Timing Budget Allocates 150 ps for Skew: ~1 Inch Meeting Skew Spec May Require Vias Connector Adds More Skew TX Board Layout Differences Cause Timing Skew RX

14 Dynamic Phase Alignment Receiver Self-Corrects for System Skew Individual Adjustment for Each Channel May Align At Power-Up or Continuously Two Basic Approaches Vary Delay of Data into Capture Register Vary Delay/Phase of Driving Capture Register Varying Phase Is Best to Avoid PVT Effects t t

15 Stratix GX Solution DPA Implemented In Hard Circuitry Truly Dynamically Adjustable Input Data Dynamic Phase Selector Aligned Deserializer 10 Phase Comp. FIFO Data Re-aligner 10 8 J Enable Receiver Fast PLL Core To Cor Fast PLL Outputs 8 Phases of Data-Rate Dynamic Phase Selector Chooses Appropriate Phase Based on Input Data

16 DPA Applications SPI 4.2 Specification Includes DPA Option Other Source-Synchronous Interfaces Can Benefit HyperTransport RapidIO Proprietary

17 Data Recovery (CDR) Reference Is Used Trace Lengths Need Not Match Each Source & Destination May Have Individual Source Data Data Destination

18 Stratix GX CDR Implementation Encoded into Data Stream PLL Recovers from Data Transitions Serial-to- Parallel Recovery Unit Pattern Detector & Word Aligner Recovered to Core Rate Matcher & Channel Aligner 8B/10B Decoder Synchronizer Reference Rx PLL Implements All Blocks Needed for XAUI PHY

19 CDR Benefits Receiver Recovers Individual s from Each Incoming Data Channel Each Channel Can Have Phase Variation Transmitters Can Operate on Multiple Crystals Each Channel Can Have Limited Frequency Variation

20 CDR Drawbacks Encoding Schemes Used to Ensure Maximum Run Length Transitions Required for Recovery Some Data Channel Bandwidth Used to Encode the Data Gbit Bandwidth Used for 2.50-Gbit Data Data Buffering Required to Accommodate Frequency Variation Channel-to-Channel Alignment Logic Required

21 CDR Application: XAUI 10 Gigabit Attachment Unit Interface (XAUI) IEEE Specification Versatile Standard: Chip-to-Chip via PCB Board-to-Board via Backplane

22 XAUI Implementation Blue Boxes Ideally Implemented in Hard Logic in FPGA for Maximum Performance Transmitter Receiver System Logic 8B10B Encoding & TX State Machine SERDES SERDES SERDES SERDES CDR CDR CDR CDR 8B10B Decoding, RX State Machine, Channel De-skew & Synchronization System Logic 4 Lanes at 3.125

23 PLL Jitter Characteristics 2002

24 Jitter Classes Random Probabilistic Timing Variations Caused by Random Thermal Effects Deterministic Repeatable Timing Variations Caused by Specific Issues Signal Modulation, Crosstalk Total Jitter = Random + Deterministic

25 Jitter Transfer Definition Input Jitter May Be Reduced or Amplified Transfer Curve Shows Performance > 0 db: Amplification < 0 db: Reduction Deterministic & Random Jitter Transfer May Be Different

26 Deterministic Jitter Transfer PLL Can Reduce Deterministic Jitter Delay-Locked Loop (DLL) Amplifies Deterministic Jitter Lab Results: Jitter Transfer (db) DJ Transfer Input clk = 128 MHz; RMS Input Jitter = 45 ps PLL DLL 77% Jitter Amplification 44% Jitter Reduction , ,000 Jitter Frequency (KHz)

27 Random Jitter Transfer PLL Reduces Random Jitter PLL Input PLL Output

28 Jitter Summary Jitter Limits System Performance Use PLL To Reduce Jitter & Enhance System Timing Margin

29 Summary Advanced Systems Present Difficult - Management Challenges Use Source-Synchronous, DPA, or CDR Interfaces to Achieve High-System Data Rates Consider Jitter Effect On System

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