440GX Application Note

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1 Migrating to PowerPC 440GX from 440GP: Hardware Considerations January 18, 2008 Abstract The AMCC PowerPC 440GX processor contains several new features that significantly improve its performance over the 440GP processor: Increased static random access memory (SRAM) An expanded Ethernet controller interface A transmission control protocol and internet protocol (TCP/IP) assist hardware unit An extended peripheral component interconnect (PCI-X) messaging unit. This application note highlights the hardware features of the PowerPC 440GX processor. It also describes the hardware changes between the 440GX and 440GP processors. Refer to the PPC440GX Embedded Processor User s Manual, listed in Related Documents on page 19, for detailed information. Overview The 440GX processor offers 440GP customers the advantage of enhanced performance in speed and communication, as outlined in Table 1. No circuit-board modifications are required to accommodate the 440GX package size, which is the same as the 440GP package size. All the 440GX signal locations are the same as the 440GP signal locations. Therefore, the 440GX processor should support existing board layouts with minor modifications. Although the 440GX processor is package-compatible with the 440GP processor, there are some additional signals in the 440GX processor. These additional signals account for most of the hardware differences between the 440GX and 440GP processors; thus, they are the focal point of this note. From a software perspective, porting an application from the 440GP processor to the 440GX processor involves new register settings for parity, machine check handling, and clock configuration strapping. Another software consideration is a new value for the processor version register (PVR) register. For information on software modifications, see the Software Considerations When Migrating to the PowerPC 440GX Processor from the 440GP Processor application note, listed in Related Documents on page 19. Table 1: Comparison of 440GP Processor to 440GX Processor Features 440GP Processor 440GX Processor Technology 0.18 μm 0.13 μm CPU Speed 400 to 500 MHz 500 to 667 MHz Double Data Rate (DDR) Clock Speed Maximum: 133 MHz (DDR266) Maximum: 166 MHz (DDR333) SRAM On-chip: 8 KB On-chip: 256 KB I/O Voltage 3.3 V Ethernet/DMA/Trace 2.5 V Memory 3.3 V 2.5 V Memory/Ethernet/DMA/Trace Core Voltage 1.8 V 1.5 V Typical Power Less than MHz Estimate: MHz Ethernet Two 10/100 Mbps interfaces Two 10/100/1000 Mbps interfaces Two 10/100 Mbps interfaces External Interrupts 13 programmable interrupts 18 programmable interrupts Package 25 x 25 mm, 552-ball ceramic ball grid array (CBGA) 25 x 25 mm, 552-ball CBGA Revision 1.01 Application Note (Proprietary) AN2006

2 Hardware Differences A primary hardware difference between the 440GP and 440GX processors is the voltage levels of some I/O signals. In particular, the voltage levels of the Ethernet, direct memory access (DMA), and some trace and general purpose input/output (GPIO) signals have changed. To support up to four Ethernet ports, there is signal multiplexing on the following: Ethernet pins Trace and GPIO signals Some external bus master interface (EBMI) signals The two reserved pins on the 440GP processor By multiplexing these signals, the designers were able to maintain the same pin count as on the 440GP processor. Another major change is the implementation of the new Ethernet controller, which increases the number of 10/100 Ethernet interfaces from two to four. Two of these Ethernet channels are capable of 1 Gbps, and support jumbo frames and TCP/IP assist. In addition, the on-chip SRAM increases from 8 KB in the 440GP processor to 256 KB in the 440GX processor. TCP/IP Assist Hardware Unit The 440GX processor has two new Ethernet interfaces that support 1 Gbps. Each has a TCP/IP assist hardware (TAH) unit that provides improved bandwidth and lower CPU utilization. For more information on the TAH, Refer to the PPC440GX Embedded Processor User s Manual, listed in Related Documents on page 19. Clocking Changes Like the 440GP processor, the 440GX processor generates its internal clocks from the system clock using an internal phase locked loop. There is a new scheme for implementing the clocking configuration that differs from the implementation in the 440GP processor. Figure 1 on page 3 illustrates this structure; Table 2 on page 3 lists the new registers used to implement the various clocking configurations. In the 440GP processor, there is a series of individually addressable device-configuration registers (DCRs) that are called CPC0_xxx. The 440GX processor splits these DCRs into two groups of registers, the clocking and power-on reset registers (CPRs), and the system DCR registers (SDRs). In the 440GP processor, different bit fields resided in the same configuration register. The new scheme implemented in the 440GX processor allows more logical partitioning (see the Software Considerations When Migrating to the PowerPC 440GX Processor from the 440GP Processor application note for more information about register settings). The firmware that is ported from the 440GP processor to the 440GX processor still needs to be changed. However, the use of these common registers and bit and field definitions provides a simpler migration path for future generations of firmware. The system clock provided to the 440GX processor has a higher maximum frequency than the 440GP processor. The maximum frequency has increased from MHz for the 440GP processor to MHz for the 440GX processor. Both parts have a minimum frequency of MHz. From a system-clock hardware perspective, one board should be able to support either the 440GP processor or the 440GX processor. A clean clock that has relatively low jitter must be provided. For details on jitter limitations, see the PowerPC 440GX Embedded Processor Datasheet, listed in Related Documents on page 19. Other configuration changes are modifications for the new software registers. The Software Considerations When Migrating to the PowerPC 440GX from the 440GP application note documents these changes. 2 Application Note (Proprietary) Revision 1.01

3 Figure 1: 440GX Processor Clocking Structure CPRD_PLLDn(FWDVA) Clock Mux SYSCLK feedback divider selected feedback CPR0_PLLCn(SEL) PLL V CO CPR0_PLLDn(FBDV) SYSCLK forward A forward PLLOUTA divider A divider CPR0_PLLDn(ENG) forward B divider PLLOUTB SYSCLK other clocks forward B divider external feedback clock CPR0_PLLDn(EFBOV) 1 0 Primary A Divider 0 CPR0_PRIMBDn(PRBDV0) Primary B Divider 0 CPR0_PLLDn(FWDVB) PLLOUTB CPU PLB Divider CPR0_OPBDn(OPBDV0) Divider OPB MAL PLLOUTA CPR0_PLLCn(SRC) CPRO_PERDn(PERDV0) Divider PER Table 2: 440GX Processor Register Mnemonic Name DCR Address (0:9) Bit Usage (0:15) (16:31) CPR_CFGADDR Clock / Power-On-Reset Configuration Address Register x 00C Reserved Offset CPR_CFGDATA Clock / Power-On-Reset Configuration Data Register x 00D Read or write data SDR_CFGADDR System DCR Configuration Address Register x 00E Reserved Offset SDR_CFGDATA System DCR Configuration Data Register x 00F Read or write data Revision 1.01 Application Note (Proprietary) 3

4 Default Strapping Comparison During a system reset, both the 440GP and 440GX processors are configured using the strapping (pull-up or pulldown) resistors on various I/Os. Table 3, Table 4, Table 5, and Table 6 beginning on page 4 show the default strapping for the 440GX processor. Refer to the PowerPC Embedded Processor User s Manuals for detailed information on programming other strapping options for these processors. Bit 0Value strapped on pin UART0_DCD_N Bit 1Value strapped on pin UART0_DRSR_N Bit 2Value strapped on pin GMC1TxCtl The values in the following tables assume a system reference clock of 33 MHz. Vary the reference clock and use the same default values to obtain different frequencies. Table 3: Default Settings for the 440GX Processor: 8-Bit ROM Option 0x1 Serial device is not enabled. Use the following defaults: Voltage controlled oscillator (VCO) = 933 MHz, central processing unit (CPU) = 466 MHz, processor local bus (PLB) = 133 MHz, on-chip peripheral bus (OPB) = 66 MHz, peripheral (PER) = 66 MHz Strap Bits 012 Register Name Bit(s) Field Name Default Value Description 1 PLL Engage 1 CPR0_PLLC0 2 PLL FB Src 0 PLLOutA 5:7 PLL FB Selection 000 PLL Output Strap 0 CPR0_PLLD0 22:31 PLL Tune Bits < M < 40 (Our M equals 28) 3:7 PLL Divider (MULT) MULT equals :15 FWSDVA (RangeA) 0010 VCO equals 933 MHz. CPU (VCO / 2) equals 466 MHz. 21:23 FWDVB (RangeB) 111 VCO equals 933 MHz. PLB (VCO / 7) equals 133 MHz. CPR0_PRIMBD0 5:7 OUTB Div 001 CPR0_OPDD0 6:7 OPB Div 10 OPB equals 66 MHz 4 Application Note (Proprietary) Revision 1.01

5 Table 3: Default Settings for the 440GX Processor: 8-Bit ROM Option (Continued) 0x1 Serial device is not enabled. Use the following defaults: Voltage controlled oscillator (VCO) = 933 MHz, central processing unit (CPU) = 466 MHz, processor local bus (PLB) = 133 MHz, on-chip peripheral bus (OPB) = 66 MHz, peripheral (PER) = 66 MHz Strap Bits 012 Register Name Bit(s) Field Name Default Value Description CPR0_PLLD0 26:31 EFBDV (Ext FB Div) CPR0_PERD0 6:7 PER Div 01 PER equals 66 MHz. CPR0_MALD0 6:7 MAL Div 10 Memory access layer (MAL)/ Ethernet media access controller (EMAC) interface equals 66 MHz. SDR0_EBC 2:3 ROM Width 00 8-bit ROM SDR0_CP ROM Loc 0 Selects 0001 external bus configuration (EBC) ROM for this field SDR0_PCIX0 0 Internal Arb En 0 1 Host Config En 0 2 Initial Seq En 0 Strap 1 3 CPU Wait En 0 4:7 PIM Sel 01 SDR0_PCIX0 8 SDR0_PCIX0 (Req64 En) 0 9:10 SDR0_PCIX0 (Freq Sel) SDR0_PCIX0 (Quick PCIX cap Detect En) 0 Quickboot Off 12 SDR0_PCIX0 (PCI Driver Mode Ctrl) 0 0 equals Multipoint SDR0_PFC1 7:9 SDR0_PFC1 (Enet Group) SDR0_PFC1 (RMII Mode) Mb MII and DMA and either CPU trace or GPIO SDR0_PFC0 23 SDR0_PFC0 (CPU Trace En) 0 SDR0_CP SDR0_CP4400 (Nto1) 0 Revision 1.01 Application Note (Proprietary) 5

6 Table 4: Default Settings for the 440GX Processor: 16-Bit ROM Option 000 Serial device is not enabled. Use the following defaults: VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz Strap Bits 012 Register Name Bit(s) Field Name Default Value Description 1 PLL Engage 1 CPR0_PLLC0 2 PLL FB Src 0 PLLOutA 5:7 PLL FB Selection 000 PLL Output Strap 0 CPR0_PLLD0 22:31 PLL Tune Bits < M < 40 (Our M = 30) 3:7 PLL Divider (MULT) MULT equals 15 12:15 FWSDVA (RangeA) 0010 VCO equals 1000 MHz. CPU (VCO / 2) equals 500 MHz. 21:23 FWDVB (RangeB) 110 VCO equals 1000 MHz. PLB (VCO / 6) equals 166 MHz. CPR0_PRIMBD0 5:7 OUTB Div 001 CPR0_OPDD0 6:7 OPB Div 10 OPB equals 83 MHz. 6 Application Note (Proprietary) Revision 1.01

7 Table 4: Default Settings for the 440GX Processor: 16-Bit ROM Option (Continued) 000 Serial device is not enabled. Use the following defaults: VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz Strap Bits 012 Register Name Bit(s) Field Name Default Value Description CPR0_PLLD0 26:31 EFBDV (Ext FB Div) CPR0_PERD0 6:7 PER Div 01 PER equals 83 MHz. CPR0_MALD0 6:7 MAL Div 10 MAL/EMAC interface equals 83 MHz. SDR0_EBC 2:3 ROM Width bit ROM SDR0_CP ROM Loc 0 Selects 0001 EBC ROM for this field SDR0_PCIX0 0 Internal Arb En 0 1 Host Config En 0 2 Initial Seq En 0 Strap 1 SDR0_PCIX0 SDR0_PFC1 3 CPU Wait En 0 4:7 PIM Sel Req64 En 0 9:10 Freq Sel Quick PCIX cap Detect En 0 Quickboot Off 12 PCI Driver Mode Ctrl 0 0 equals Multipoint 7:9 Enet Group RMII Mode Mb MII and DMA and either CPU Trace or GPIO SDR0_PFC0 23 CPU Trace En 0 SDR0_CP Nto1 0l Revision 1.01 Application Note (Proprietary) 7

8 Table 5: Default Settings for the 440GX Processor: 32-Bit ROM Option 010 Serial device is not enabled. Use the following defaults: VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz Strap Bits 012 Register Name Bit(s) Field Name Default Value Description 1 PLL Engage 1 CPR0_PLLC0 2 PLL FB Src 0 PLLOutA 5:7 PLL FB Selection 000 PLL Output Strap 0 CPR0_PLLD0 22:31 PLL Tune Bits < M < 40 (Our M = 30) 3:7 PLL Divider (MULT) MULT equals :15 FWSDVA (RangeA) 0010 VCO equals 1000 MHz. CPU (VCO / 2) equals 500 MHz. 21:23 FWDVB (RangeB) 110 VCO equals 1000 MHz. PLB (VCO / 6) equals 166 MHz. CPR0_PRIMBD0 5:7 OUTB Div 001 CPR0_OPDD0 6:7 OPB Div 10 OPB equals 83 MHz. 8 Application Note (Proprietary) Revision 1.01

9 Table 5: Default Settings for the 440GX Processor: 32-Bit ROM Option (Continued) 010 Serial device is not enabled. Use the following defaults: VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz Strap Bits 012 Register Name Bit(s) Field Name Default Value Description CPR0_PLLD0 26:31 EFBDV (Ext FB Div) CPR0_PERD0 6:7 PER Div 01 PER equals 83 MHz. CPR0_MALD0 6:7 MAL Div 10 MAL/EMAC interface equals 83 MHz. SDR0_EBC 2:3 ROM Width bit ROM SDR0_CP ROM Loc 0 Selects 0001 EBC ROM for this field. SDR0_PCIX0 0 Internal Arb En 0 1 Host Config En 0 2 Initial Seq En 0 Strap 1 SDR0_PCIX0 SDR0_PFC1 3 CPU Wait En 0 4:7 PIM Sel Req64 En 0 9:10 Freq Sel Quick PCIX cap Detect En 0 Quickboot Off 12 PCI Driver Mode Ctrl 0 0 equals Multipoint 7:9 Enet Group RMII Mode Mb MII and DMA and either CPU trace or GPIO SDR0_PFC0 23 CPU Trace En 0 SDR0_CP Nto1 0 Revision 1.01 Application Note (Proprietary) 9

10 Table 6: Default Settings for the 440GX Processor: PCI Boot Option 100 Serial device is not enabled. Use the following defaults: VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz Strap Bits 012 Register Name Bit(s) Field Name Default Value Description 1 PLL Engage 1 CPR0_PLLC0 2 PLL FB Src 0 PLLOutA 5:7 PLL FB Selection 000 PLL Output Strap 0 CPR0_PLLD0 22:31 PLL Tune Bits < M < 40 (Our M = 30) 3:7 PLL Divider (MULT) MULT equals 15 12:15 FWSDVA (RangeA) 0010 VCO equals 1000 MHz. CPU (VCO / 2) equals 500 MHz. 21:23 FWDVB (RangeB) 111 VCO equals 1000 MHz. PLB (VCO / 6) equals 166 MHz. CPR0_PRIMBD0 5:7 OUTB Div 001 CPR0_OPDD0 6:7 OPB Div 10 OPB equals 83 MHz. 10 Application Note (Proprietary) Revision 1.01

11 Table 6: Default Settings for the 440GX Processor: PCI Boot Option (Continued) 100 Serial device is not enabled. Use the following defaults: VCO = 1000 MHz, CPU = 500 MHz, PLB = 166 MHz, OPB = 83 MHz, PER = 83 MHz Strap Bits 012 Register Name Bit(s) Field Name Default Value Description CPR0_PLLD0 26:31 EFBDV (Ext FB Div) CPR0_PERD0 6:7 PER Div 0 PER equals 83 MHz. CPR0_MALD0 6:7 MAL Div 10 MAL/EMAC interface equals 83 MHz. SDR0_EBC 2:3 ROM Width 10 PCI Boot Option SDR0_CP ROM Loc 0 Selects 001 EBC ROM for this field SDR0_PCIX0 0 Internal Arb En 0 1 Host Config En 1 2 Initial Seq En 0 Strap 1 SDR0_PCIX0 SDR0_PFC1 3 CPU Wait En 1 4:7 PIM Sel Req64 En 0 9:10 Freq Sel Quick PCIX cap Detect En 0 Quickboot Off 12 PCI Driver Mode Ctrl 0 0 equals Multipoint 7:9 Enet Group RMII Mode Mb MII and DMA and either CPU trace or GPIO SDR0_PFC0 23 CPU Trace En 0 SDR0_CP Nto1 0 Revision 1.01 Application Note (Proprietary) 11

12 Ethernet Changes The 440GX processor implements two new Ethernet interfaces with larger first in/ first out queues (FIFOs). These new interfaces support Gbps operations and jumbo packets (that is, packets greater than 1518 bytes). Existing software written for the 440GP processor will execute properly on the 440GX processor. However, new software will be needed to take advantage of the faster and larger interface. The two new interfaces also require two new interrupts per interface that will drive changes into the interrupt handler routine. For more information on software requirements, see the Software Considerations When Migrating to the PowerPC 440GX Processor from the 440GP Processor application note. There is a total of four Ethernet ports, and two support the gigabit Ethernet. These controllers have several configuration options available to communicate with a device (see Table 7 for supported Ethernet port configurations on the 440GX processor). On the 440GP processor, there are only two interfaces for communications to physical devices. New signal pins are associated with the new Ethernet controllers. These pins are multiplexed with existing signals that were on the 440GP processor. Seven combinations of pin multiplexing support the different Ethernet combinations listed in Table 7. Select the desired combination by programming the Ethernet group field in the new pin function control register, SDR0_PFC1. Table 7 shows that, in gigabit mode, DMA channels 2 and 3 share pins with the ethernet media access controller pin, EMAC2. Therefore, neither of those DMA channels are available for external use when any of the EMAC pins are configured for any setting other than 10/100 Mbps in serial media independent interface (SMII) mode. Note that DMA channels 2 and 3 are still available for use within the processor by internal DMA peripherals or for memory-to-memory transfers. Also, the GPIO[27:31] and CPU trace pins are shared with the gigabit modes for EMAC3. Therefore, they cannot be used simultaneously unless EMAC3 is only configured for 10/100 Mbps SMII mode. To allow access to the trace feature when using EMAC3, the trace pins have also been multiplexed onto the external bus master interface (EBMI) signals. Note that the trace and GPIO pins multiplexed with Ethernet signals operate at 2.5 V I/O, and the trace and EBMI multiplexed signals operate at 3.3 V I/O. See Table 9 on page 15 for a list of I/O signals that are multiplexed in the 440GX processor. Table 7: Ethernet Interfaces Option Number EMAC0 EMAC1 EMAC2 EMAC3 DMA2/3 Trace/GPIO Trace on EBMI 0 MII Y Y Y 1 RMII RMII Y Y Y 2 SMII SMII SMII SMII Y Y Y 3 RMII RGMII/RTBI Y Y *4 SMII SMII RGMII/RTBI RGMII/RTBI Y 5 SMII SMII SMII RGMII/RTBI Y Y 6 SMII SMII RGMII/RTBI Y Y * The two reduced gigabit ethernet media-independent interface (RGMll) / reduced 10-bit interface (RTBl) ports can be combined into a single gigabit ethernet media-independent interface (GMll) / 10-bit interface (TBl) port, per the gigabit Ethernet chart in Table 10 on page Application Note (Proprietary) Revision 1.01

13 SRAM Changes The on-chip SRAM has increased from 8 KB on the 440GP processor to 256 KB on the 440GX processor. The 440GX SRAM is divided into four banks of 64 KB each; this requires four bank-configuration registers (SRAM0_SBxCR) for access use. On the 440GP processor, there are two banks of memory available. The 440GX SRAM parity protection is the same as that for the 440GP processor. Table 8: SRAM Comparison Four physical banks of 64 KB Parity Support 440GX Processor Memory cycles supported: - Single-beat read and write, one to 16 bytes and 64-byte burst transfers Guarded memory accesses Sustainable 2.6 GBps peak bandwidth at 166 MHz Two physical bank of 8 KB Parity support 440GP Processor Memory cycles supported: - Single-beat read and write, one to 16 bytes and 64-byte burst transfers Guarded memory accesses Sustainable 2.1 GBps peak bandwidth at 133 MHz Universal Interrupt Controller Figure 24. shows that two universal interrupt controllers (UIC) have been added for the 440GX processor. A base UIC cascades the original two UICs from the 440GP processor with a new third UIC for the additional function. The 440GP controller has 62 inputs that come from an internal chip component or external devices. There are additional cores in the 440GX processor that have their own interrupts. In order to provide backward compatibility with the 440GP processor, an additional switch allows the controller to operate in 440GP mode if desired. The switch is implemented as a bit in the miscellaneous function register, SDR0_MFR. To use this new function in the 440GX processor, set the switch to 440GX mode. In this mode, a new UIC, UIC2, is present. The inputs to UIC2 are the new components of the 440GX processor that are accessible in this mode. For details, see the Software Considerations When Migrating to the PowerPC 440GX from 440GP application note. Revision 1.01 Application Note (Proprietary) 13

14 Figure 2: Universal Interrupt Controllers 440GP Interrupt Queues UIC0 Critical Interrupt Noncritical Interrupt Base UIC GP Interrupt Queues UIC1 Critical Interrupt Noncritical Interrupt Critical Interrupt Mode Noncritical Interrupt UIC2 440GX Critical Interrupt Interrupt Queues Noncritical Interrupt Reserved 6:31 14 Application Note (Proprietary) Revision 1.01

15 I2O Messaging Unit The I2O messaging unit (IMU) is a new feature in the 440GX processor. This processor local bus (PLB) slave and master core allows messages to be transferred between two PLB masters (normally the CPU and an I/O device such as the PCI-X core). Typically, inbound messages are written from the PCI-X or I/O device to the 440GX CPU. Outbound messages are written from the CPU to the PCI-X or I/O device. There are four message registers in the 440GX processor, two for inbound messages and two outbound message. The IMU operates at the same frequency as the PLB, per the clocking configuration. The IMU core implements the following three different messaging methods: Message registers: Messages are transferred among PLB masters by writing and reading 32-bit message registers that are implemented inside the IMU core. Writing to the message registers may cause interrupts to be generated. Doorbell registers: Interrupts are generated among the PLB masters by writing to the doorbell registers. Circular queues: The PLB masters transfer messages by using four circular queues to pass message frame addresses (MFAs). The IMU core informs the destination device that messages have arrived by setting internal status bits and generating interrupts. I/O Signal Changes Although the pin count for the 440GP and 440GX processors is the same, the 440GX processor has additional signals. These additional signals are multiplexed with other signals to maintain the pin count, thus preserving the same package type as with the 440GP processor. The 440GX processor uses the 1.5 V CMOS Cu-11 technology. All Ethernet and DMA signals have changed from 3.3 V to 2.5 V. The trace and GPIO[27:31] signals have changed from 3.3 V to 2.5 V. Refer to the PowerPC 440GX Embedded Processor Datasheet for a complete pinout listing. Although the I/O signals have switched from 3.3 V to 2.5 V, the receivers are still 3.3 V tolerant. Therefore, a 3.3 V device can drive the I/O signals. The drivers are 3.3 V or 2.5 V tolerant, but there is no support for 5 V interfaces. Table 9 lists the new 440GX signals that are multiplexed with existing 440GP signals. In general, signals have been multiplexed to incorporate the enhanced Ethernet feature of the 440GX interface. Table 9: Multiplexed Ethernet Signals Ball MII I/O RMII I/O SMII I/O RGMII I/O Other I/O Other I/O L05 EMCMDIO I/O EMCMDIO I/O EMCMDIO I/O J08 EMACMDClk O EMACMDClk O EMACMD- Clk O G03 EMCRxD0 I EMC0RxD0 I EMCRxD I E01 EMCRxD1 I EMC0RxD1 I EMC1RxD I A07 EMCRxD2 I EMC1RxD0 I EMC2RxD I GMC0TxD0 O H09 EMCRxD3 I EMC1RxD1 I EMC3RxD GMC0TxD1 K01 EMCRxDV I EMC1CRSD V GMC1TxD0 O 1. MII: Media-independent interface 2. RMII: Reduced media-independent interface 3. SMII: Serial media-independent interface 4. RGMII:Reduced gigabit Ethernet media-independent interface Mbps standard transceiver interface. Revision 1.01 Application Note (Proprietary) 15

16 Table 9: Multiplexed Ethernet Signals (Continued) Ball MII I/O RMII I/O SMII I/O RGMII I/O Other I/O Other I/O J02 EMCRxClk I GMC1TxD1 O K03 EMCRxErr I EMC0RxErr I O GMC1TxD2 O K07 EMCCRS I EMC0CRSD V I O GMC1TxD3 O J06 EMCTxClk I EMCRefClk I EMCRef- Clk I J07 EMCCCD I EMC1RxErr I GMC0TxClk O C05 EMCTxErr O EMC1TxEn O L06 EMCTxEn O EMC0TxEn O EMCSync O L09 EMCTxD0 O EMC0TxD0 O EMC0TxD O K05 EMCTxD1 O EMC0TxD1 O EMC1TxD O GMC0RxCl k I J04 EMCTxD2 O EMC1TxD0 O EMC2TxD O GMC0TxD2 J03 EMCTxD3 O EMC1TxD1 O EMC3TxD GMC0TxD3 P06 GMC0RxD0 I DMAAck2 O P11 GMC0RxD1 I DMAAck3 O P16 GMC0RxD2 I EOT2 I/O M16 GMC0RxD3 I EOT3 I/O N11 GMC0RxCtl I DMAReq2 I P01 GMC0TxCtl O DMAReq3 I P03 GMC1RxCl k I TrcTS1 O GPIO27 I/O R07 GMC1RxD0 I TrcTS2 O GPIO28 I/O P09 GMC1RxD1 I TrcTS3 O GPIO29 I/O R09 GMC1RxD2 I TrcTS4 O GPIO30 I/O T06 GMC1RxD3 I TrcTS5 O GPIO31 I/O R01 GMC1TxClk O TrcTS6 O L01 GMCRefClk I P04 GMC1RxCtl I L07 GMC1TxCtl O 1. MII: Media-independent interface 2. RMII: Reduced media-independent interface 3. SMII: Serial media-independent interface 4. RGMII:Reduced gigabit Ethernet media-independent interface Mbps standard transceiver interface. 16 Application Note (Proprietary) Revision 1.01

17 Table 9: Multiplexed Ethernet Signals (Continued) Ball MII I/O RMII I/O SMII I/O RGMII I/O Other I/O Other I/O AA2 4 AA2 2 AB2 3 TrcTS1 O BusReq O TrcTS2 O ExtAck O TrcTS3 O ExtReq I Y21 TrcTS4 O HoldAck O Y23 TrcTS5 O HclReq I P21 TrcTS6 O PERR I/O 1. MII: Media-independent interface 2. RMII: Reduced media-independent interface 3. SMII: Serial media-independent interface 4. RGMII:Reduced gigabit Ethernet media-independent interface Mbps standard transceiver interface. Revision 1.01 Application Note (Proprietary) 17

18 Table 10: Gigabit Ethernet and TBI Mode Multiplexing Ball RGMII I/O GMII I/O TBI I/O RTBI I/O A07 GMC0TxD0 O GMCTxDO O TBITxD0 O RTBI0TxD0 O H09 GMC0TxD1 O GMCTxD1 O TBITxD1 O RTBI0TxD1 O K01 GMC1TxD1 O GMCTxD4 O TBITxD4 O RTBI1TxD0 O J02 GMC1TxD1 O GMCTxD5 O TBITxD5 O RTBI1TxD1 O K03 GMC1TxD2 O GMCTxD6 O TBITxD6 O RTBI1TxD2 O K07 GMC1TxD3 O GMCTxD7 O TBITxD7 O RTBI1TxD3 O J07 GMC1TxClk O GMCTxClk O TBITxClk O RTBI0Txclk O C05 GMC0RxClk I GMCRxClk I TBIRxClk0 I RTBI0RxClk I J04 GMC0TxD2 O GMCTxD2 O TBITxD2 O RTBIOTxD2 O J03 GMC0TxD3 O GMCTxD3 O TBITxD3 O RTBIORxD3 O P06 GMC0RxD0 I GMCRxD0 I TBIRxD0 I RTBIORxD0 I P11 GMC0RxD1 I GMCRxD1 I TBIRxD1 I RTBIORxD1 I P16 GMC0RxD2 I GMCRxD2 I TBIRxD2 I RTBIORxD3 I M16 GMC0RxD3 I GMCRxD3 I TBIRxD3 I RTBIORxD3 I N11 GMC0RxCtl I GMCRxDv I TBIRxD8 I RTBI0RxCtl I P01 GMC0TxCtl O GMCTxEn O TBITxD8 I RTBI0TxCtl O P03 GMC1RxClk I GMCCol I TBIRxClk1 I RTBI1RxClk I R07 GMC1RxD0 I GMCRxD4 I RBIRxD4 I RTBI1RxD0 I P09 GMC1RxD1 I GMCRxD5 I TBIRxD5 I RTBI1RxD1 I R09 GMC1RxD2 I GMCRxD6 I TBIRxD6 I RTBI1RxD2 I T06 GMC1RxD3 I GMCRxD7 I TBIRxD7 I RTBI1RxD3 I R01 GMC1TxClk O GMCCrs I RTBI1TxClk O L01 GMCRefClk I GMCRefClk I GMCRefClk I GMCRefClk I P04 GMC1RxCtl I GMCRxEr I TBIRxD9 I RTBI1RxCtl I L07 GMC1TxCtl O GMCTxEr O TBITxD9 O RTBI1TxCtl O 1. RGMII:Reduced gigabit Ethernet media-independent interface Mbps standard transceiver interface. 2. GMII: Gigabit Ethernet media-independent interface Mbps standard transceiver interface. 3. TBI: 10-bit interface. 4. RTBI:Reduced 10-bit interface. 18 Application Note (Proprietary) Revision 1.01

19 Conclusion The PowerPC 440GX processor provides a path that can enable PowerPC 440GP customers to realize improved system performance. Multiplexing additional I/O signals on the 440GX processor maintains the same package pinout as on the 440GP processor, thus minimizing the effort required to redesign existing 440GP boards. New PowerPC designs based on the 440GX processor can also use the new performance features of the 440GX processor by taking advantage of the new Ethernet core, TCP/IP hardware assist, upgraded I2O messaging unit, and increased SRAM storage capacity. Related Documents Additional information about the PowerPC 440Gx and 440GP processors is available in the following sources, located at PPC440GX Embedded Processor User s Manual. AMCC Corporation. Software Considerations When Migrating to the PowerPC 440GX Processor from the 440GP Processor Application Note. AMCC Corporation. PowerPC 440GX Embedded Processor Datasheet. AMCC Corporation. Revision 1.01 Application Note (Proprietary) 19

20 Document Revision History Revision Date Description v1.01 1/18/08 Converted layout to AMCC format. 20 Application Note (Proprietary) Revision 1.01

21 Applied Micro Circuits Corporation 6310 Sequence Dr., San Diego, CA Main Phone: (858) Technical Support Phone: (858) (800) AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright 2008 Applied Micro Circuits Corporation. I2C BUS is a registered Trademark of Philips N.V. Corporation Netherlands. Revision 1.01 Application Note (Proprietary) 21

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