McMaster University Embedded Systems. Computer Engineering 4DS4 Lecture 6 Serial Peripherals Amin Vali Feb. 2016

Transcription

1 McMaster University Embedded Systems Computer Engineering 4DS4 Lecture 6 Serial Peripherals Amin Vali Feb. 2016

2 Serial Peripherals I2C Inter-IC Bus X/Y Coord. RGB data LCD config controller LCD data controller I 2 C Horiz./vert. sync data RGB data Liquid Crystal Display (LCD) SPI Touch_en Coord_en X/Y Coord. Touch panel controller SPI Touch panel Serial Peripheral Interface Other serial communication protocols

3 Serial Peripherals I2C ("eye-squared-see") Inter-IC (integrated circuit) bus Low-bandwidth (up to 400Kbps) Pass configuration data to on-board peripherals accessed intermittently Two wires with no chip selects or arbitration logic simple in hardware SDA/SCL open drain and pulled high with a resistor (wired AND) Master Controller serial data (SDA) serial clock (SCL) Peripheral 1... Peripheral n

4 Serial Peripherals I2C Typical transaction in a single-master/multiple-slaves environments Master initiates the Start sequence Master sends the Slave Address Master sends the Read/ Write ( R/W ) 0 (read) / 1 (write) Master waits/sends the acknowledge bit ( ACK ) depending on R/W Master/slave send/receive the data byte ( Data ) depending on R/W Master/slave wait/send ACK 0 for acknowledged / 1 not acknowledge Master sends the Stop sequence. SDA A 6 A 5... A 0 R/W ACK D 7 D 0 ACK SCL Start Address R/W ACK Data ACK Stop

5 Serial Peripherals I2C Clock stretching by slave (Open Drain) slow down the speed master must wait for the SCL to be released to continue Read/write transactions Write transactions (from master to slave) Start Address W ACK Data ACK Data ACK Data ACK Stop Read transactions (from master to slave) Start Address R ACK Data ACK Data ACK Data NACK Stop Legend: Master drives SDA Slave drives SDA

6 Serial Peripherals I2C For data bits, the SDA line is always constant during the high-level of SCL it changes while SCL is 0 Start/stop sequence is different Start: falling edge on SDA while SCL is 1 Stop: rising edge on SDA while SCL is 1 Acknowledge bits 0 acknowledge/1 not acknowledge For a write transaction if the slave did not acknowledge then stop the transaction and retransmit the data For a read transaction master can choose not to acknowledge when it received enough data and then it generates the stop sequence

7 Serial Peripherals SPI Serial Peripheral Interface (SPI) Synchronous 4-wire serial interface Full-duplex communication Arbitrary message size (not in bytes) No peripheral addressing required (use select signals from the master) No slave acknowledgements Slave can generate interrupts to the master (not covered by standard) Master MOSI Controller MOSI Peripheral up to 70 MHz MOSI Master Out Slave In ( SIMO) Master In Slave Out (SOMI) Slave Select (active low)

8 Serial Peripherals SPI Data transfers are done through shift registers in master and slave controllers Depending on the particular application, the master/slave controller decides when to load/unload the shift registers If / are active more than the slave requires, then it ignores its input and it shifts back dummy bits to master Master Controller Peripheral... MOSI MOSI...

9 Serial Peripherals SPI Timing and modes - determined by clock polarity (CPOL) and clock phase (CPHA) CPOL=0 clock starts at 0 (base value) CPHA=0 - data read on rising edge and changed on falling edge CPHA=1 - data read on falling edge and changed on rising edge CPHA=0 CPHA=1... M k-1 MOSI M 0 M 1... Sk-1 M 0 M 1... M k-1 S 0 S 1 S 0 S 1... S k-1 CPOL=1 clock starts at 1 (Complement of the above) CPHA=0 read on falling edge, CPHA=1 read of rising edge,

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11 Serial Peripherals SPI Attaching multiple peripherals to the master controller multiple slave select signals from the master (most common) Master MOSI Controller n MOSI Peripheral 1 MOSI Peripheral 2... MOSI Peripheral n

12 Serial Peripherals SPI Daisy chain configuration configure a single shift register by connecting the output of one slave to the input of the next one (single slave select) Master MOSI Controller MOSI Peripheral 1 MOSI Peripheral 2... MOSI Peripheral n