Virtual Memory Nov 9, 2009"
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1 Virtual Memory Nov 9, 2009"
2 Administrivia" 2!
3 3! Motivations for Virtual Memory"
4 Motivation #1: DRAM a Cache for Disk" SRAM" DRAM" Disk" 4!
5 Levels in Memory Hierarchy" cache! virtual memory! CPU" regs" C" 8 B! a" 32 B! 4 KB! Memory! c" h" e" disk" size:! speed:! $/Mbyte:! line size:! Register " Cache" Memory" Disk Memory" 32 B! 1 ns! 8 B! 32 KB-4MB! 2 ns! $30/MB! 32 B! 1024 MB! 30 ns! $0.02/MB! 4 KB! 100 GB! 8 ms! $0.001/MB! larger, slower, cheaper! 5!
6 DRAM vs. SRAM as a Cache " SRAM" DRAM" Disk" 6!
7 Impact of Properties on Design" 7!
8 Locating an Object in a Cache " Cache " Tag" Data" Object Name! X" = X?! 0:" 1:" N-1:" D" 243" X" 17" J" 105" 8!
9 Locating an Object in Cache (cont.)" Page Table" Cache " 9! Object Name! X" D:" Location" 0" J:" On Disk" X:" 1" 0:" 1:" N-1:" Data" 243" 17" 105"
10 A System with Physical Memory Only" Physical! Addresses" Memory" 0:" 1:" CPU" 10! N-1:" Addresses generated by the CPU correspond directly to bytes in physical memory"
11 A System with Virtual Memory" Memory" Virtual! Addresses" Page Table" 0:" 1:" Physical! Addresses" 0:" 1:" CPU" P-1:" N-1:" Disk" Address Translation: Hardware converts virtual addresses to physical addresses via OS-managed lookup table (page table)" 11!
12 Page Faults (like Cache Misses )" CPU" Virtual! Addresses" Before fault" Page Table" Physical! Addresses" Memory" CPU" Virtual! Addresses" After fault" Page Table" Physical! Addresses" Memory" 12! Disk" Disk"
13 Servicing a Page Fault" (1) Initiate Block Read! Processor! Reg" (3) Read Done! Cache! Memory! Memory-I/O bus! (2) DMA Transfer! I/O! controller! disk! Disk! disk! Disk! 13!
14 Motivation #2: Memory Management" %esp" kernel virtual memory" stack" memory invisible to" user code" 14! Linux/x86 process" memory " image" 0" Memory mapped region " forshared libraries" runtime heap (via malloc)" uninitialized data (.bss)" initialized data (.data)" program text (.text)" forbidden" the brk ptr"
15 Solution: Separate Virt. Addr. Spaces" Virtual and physical address spaces divided into equal-sized blocks" blocks are called pages (both virtual and physical)" Each process has its own virtual address space" operating system controls how virtual pages as assigned to physical memory" Virtual Address Space for Process 1:! 0" N-1" VP 1" VP 2"..." Address Translation" 0" PP 2" Physical! Address! Space (DRAM)! 15! Virtual Address Space for Process 2:! 0" N-1" VP 1" VP 2"..." M-1" PP 7" PP 10" (e.g., read/only library code)"
16 Contrast: Macintosh Memory Model" P1 Pointer Table! Shared Address Space! Process P1! A" B" Handles " Process P2! P2 Pointer Table! C" D" E" 16!
17 Macintosh Memory Management" Process P1! P1 Pointer Table! Shared Address Space! B" Handles " P2 Pointer Table! Process P2! 17! A" C" D" E"
18 Mac vs. VM-Based Memory Mgmt" 18!
19 19! MAC OS X"
20 Motivation #3: Protection" Process i:" Page Tables" Read?" Write?" Physical Addr" VP 0:" Yes" No" PP 9" VP 1:" Yes" Yes" PP 4" 0:" 1:" Memory" Process j:" VP 2:" No" No" Read?" Write?" VP 0:" VP 1:" Yes" Yes" Yes" No" XXXXXXX" Physical Addr" PP 6" PP 9" N-1:" 20! VP 2:" No" No" XXXXXXX"
21 VM Address Translation" 21!
22 VM Address Translation: Hit" Processor" a" Hardware" Addr Trans" Mechanism" a'" Main" Memory" virtual address" part of the " on-chip" physical address" memory mgmt unit (MMU)" 22!
23 VM Address Translation: Miss" Processor" a" Hardware" Addr Trans" Mechanism" " a'" page fault! fault" handler" Main" Memory" virtual address" part of the " physical address" on-chip" memory mgmt unit (MMU)" Secondary memory, Disk" OS performs" this transfer" (only if miss)" 23!
24 VM Address Translation" n 1! p! p 1! 0! virtual page number! page offset! virtual address" address translation! m 1! p! p 1! 0! physical page number! page offset! physical address" Page offset bits donʼt change as a result of translation" 24!
25 Page Tables" Virtual Page" Number" Valid" 1" 1" 0" 1" 1" 1" 0" 1" 0" 1" Memory resident" page table" (physical page " or disk address)" Physical Memory" Disk Storage" (swap file or" regular file system file)" 25!
26 Address Translation via Page Table" page table base register" VPN acts as" table index" virtual address" n 1" p" p 1" 0" virtual page number (VPN)" page offset" valid" access" physical page number (PPN)" if valid=0" then page" not in memory" m 1" p" p 1" physical page number (PPN)" page offset" physical address" 0" 26!
27 27! Page Table Operation"
28 28! Page Table Operation"
29 29! Page Table Operation"
30 Integrating VM and Cache" CPU! VA! PA! miss! Trans-! Cache! lation! data! hit! Main! Memory! 30!
31 Speeding up Translation with a TLB" CPU! hit! VA! PA! miss! TLB! Cache! Lookup! Main! Memory! miss! hit! Trans-! lation! data! 31!
32 Address Translation with a TLB" n 1" p" p 1" 0" virtual page number" page offset" virtual address" valid" tag" physical page number"."."." TLB" TLB hit" =" physical address" tag" valid" tag" data" index" byte offset" Cache" cache hit" 32! =" data"
33 Simple Memory System Example" 13" 12" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" VPN" (Virtual Page Number)! VPO" (Virtual Page Offset)! 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" PPN" (Physical Page Number)! PPO" (Physical Page Offset)! 33!
34 Simple Memory System Page Table" Only show first 16 entries (no protection information)" 34!
35 Simple Memory System TLB" TLBT" TLBI" 13" 12" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" VPN" VPO" 35!
36 Simple Memory System Cache" CT" CI" CO" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" PPN" PPO" 36!
37 Address Translation Example #1" TLBT" TLBI" 13" 12" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" VPN" VPO" CT" CI" CO" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" PPN" PPO" 37!
38 Address Translation Example #2" TLBT" TLBI" 13" 12" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" VPN" VPO" CT" CI" CO" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" PPN" PPO" 38!
39 Address Translation Example #3" TLBT" TLBI" 13" 12" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" VPN" VPO" CT" CI" CO" 11" 10" 9" 8" 7" 6" 5" 4" 3" 2" 1" 0" PPN" PPO" 39!
40 Multi-Level Page Tables" Level 2" Tables" Level 1" Table"..." 40!
41 Main Themes" 41!
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