PPC34C60 Tips Background, History, Design Issues and Recommendations IEEE 1284 Detailing Interrupt and DMA Considerations By Bob Gross

Transcription

1 APPLICATION NOTE 7.4 PPC34C60 Tips Background, History, Design Issues and Recommendations IEEE 1284 Detailing Interrupt and DMA Considerations By Bob Gross General Background Circa , it became obvious that the Standard PC s, (SPP s), transfer rate was not at all adequate for the times. Several independent industry groups were formed in an effort to increase the performance of the. Of course any performance enhancements had to be compatible with all previous, legacy, devices. Eventually all of the Industry groups came together under the auspices of the IEEE Transfer rate was just one of many issues addressed by the IEEE In the end analysis, transfer rate had gone from 50 Kbytes/second, at best, to 2 MBytes/second. PPC34C60 Overview The PPC34C60, is an IEEE 1284 peripheral side controller. It is intended for use as a peripheral side companion to any IEEE 1284 Host Controller, including any of SMSC s many IEEE 1284 Compatible host I/O controllers. SMSC pioneered the implementation of an IEEE 1284 Host I/O controller in our FDC37C665. All of SMSC s Host I/O Controllers from the FDC37C665 forward, include IEEE 1284 compliant Parallel Ports. The PPC34C60 will work with any PC Compatible. There are many different types of s ranging from the Standard, (SPP), to full blown IEEE 1284 s and everything in between. The PPC34C60 will operate in several of the enhanced IEEE 1284 Host Modes. If these modes are available and utilized, a significant performance increase can be realized.

2 The PPC34C60 is intended for use in peripheral designs. It is designed to take advantage of some of the new IEEE1284 high speed modes. It allows for the design of high speed ISA peripherals and add on enhancement products. The PPC34C60 is unique in that unlike most such designs and products of this type, an internal adapter card is not required for peripheral products designed utilizing the PPC34C60. As such, the user is not required to open the box. Instead a simple Parallel Port or Printer Port cable is all that is required. This cable is connected externally just as a printer would be. This feature is most useful in the portable application where opening the box is usually not possible. PPC34C60 and the Daisy Chain The IEEE 1284 specifies the PC Compatible High Speed Port. The IEEE defines extensions to the original specification. The unratified and forever changing, IEEE defines the daisy chain. The PPC34C60 and peripherals designed with it, plug into the PC s. The PC s is generally used for printer connection and most PC s only have one. Adding a second kind of defeats the whole purpose of the PPC34C60 to begin with. The beauty of the PPC34C60 is that it enables the design of external attach peripherals. External attach means the end user does not have to open the box. The PPC34C60 supports the IEEE Daisy Chain and Pass Through Modes. Daisy Chaining is exactly what it sounds like. Multiple peripherals may be connected to the same port, in a Daisy Chain fashion. The printer, typically, in the past, a non IEEE 1284 device, is located at the end of the Daisy Chain. Presently, the printer, although, more and more so, an IEEE 1284 device will still not generally be an IEEE device and must still be located at the end of the IEEE Daisy Chain. A block diagram is presented in figure 1. 2

3 FIGURE 1 IEEE DAISY CHAIN BLOCK DIAGRAM H O S T PRINTER #1 #2 #3 #4 The Daisy Chain Protocol allows the use of multiple 1284 devices attached to the PC s while at the same time preserving the Port for it s legacy function. When multiple devices are connected to the, a selection process determines which device is active. Inactive devices Pass Through Status and Control signals not destined for them. The PPC34C60 dedicates nine (9) pins to Pass Through functionality. Please refer to the PPC34C60 data sheet for a complete description of these pins and their utilization. The eight Data lines, do not Pass Through, but rather, multi-drop to each device. Termination There are several termination issues involved with both host and peripheral Designs. Please refer to SMSC Application Note AN 5.10 (Printer Port Issues - Printer Chatter and Back Drive) for a discussion of Host related termination issues. Daisy Chain termination must be handled differently then the Host. Pull - Up resistors change from the Host 1-1.2k ohms to 4.7k ohms for multi-drop Data lines. The Daisy Chain devices must provide termination as any particular Daisy Chain device may be the only device on the. In the case of several attached devices, a high impedance must be presented to minimize loading. This is why multi-drop line termination is increased to 4.7k ohms. Interrupts 3

4 The PPC34C60 includes some non-published features that the designer should be aware of and take into consideration. If the PPC34C60 s interrupts are being utilized in a design, the following should be carefully noted. The PPC34C60, per original design specification, included in band data bus signaling to enable certain advanced features. Due to omissions in design, currently, this feature yields some undesirable results. If interrupts are being used, that is, enabled, a 50H on the peripheral data bus will generate a false interrupt. Of course interrupts can be enabled and a 50H will generate a false interrupt but if the host is not relying on, or using this interrupt, no harm will occur. DMA and Interrupts ( Bus) In the case of interrupt, Terminal Count (TC), driven DMA, if a 50H is transferred, a false interrupt will be generated. When using the PPC34C60, interrupt mode is not recommended. Polling techniques would be the preferred method. However, as some design situations dictate the use of interrupts, the following work arounds are recommended. Of course any fix is possible utilizing external hardware. In the DMA Interrupt driven transfer case, a painless, no hardware solution exists. This is possible due the fact that the DMA Interrupt is generated by a Terminal Count (TC). If an interrupt is generated and there is no TC present or active, then that interrupt was falsely generated. To check this does require a few extra instructions in the Interrupt Service Routine (ISR). By utilizing one of the PPC34C60 s General Purpose Input / Output (GPI/O) pins, the DMA Terminal Count (TC), may be read or checked against an interrupt. If TC is not asserted at the time of the interrupt, it is FALSE. The ISR clears the interrupt and returns, there has been no interruption of the DMA transfer. Registers There are two (2) main registers, detailed below, that are pertinent to the issues presented in this application note. Register bits of interest are: INPUT REGISTER Bits 0-3, for TC Input INPUT REGISTER Bits 5 and 6, for IRQ Control 4

5 OPERATION REGISTER Bits 6 AND 7, for INT Handling INPUT REGISTER (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOBATT IRQ IRQ LATCH QIC-80 IN3 IN2 IN1 IN0 OPERATION REGISTER (Read / Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCLR INTEN AUTO - INC PDMA DIREC DMA EN D16 F16 Physical Pin References Terminal Count (TC) is PPC34C60 Pin # 46 General Purpose Input / Output (GPI/O) are PPC34C60 Pins # 36, 37, 82 and 83. IN(0) - Pin # 82 IN(1) - Pin # 83 IN(2) - Pin # 37 IN(3) - Pin # 36 Please refer to Figure 2 for a for a block diagram detailing the peripheral side. Included in the diagram : PPC34C60 IEEE 1284 DRAM Data Bus DMA DMA Control Lines Bus Device Customer Circuitry 5

6 FIGURE 2 HOST PPC43C60 DMA 'fix' BLOCK DIAGRAM DRAM PPC34C60 TC IN(X) 46 X X = 0, 1, 2 or 3 = 82, 83, 37 or 36 DMA TC Bus Device 6

7 80 Arkay Drive Hauppauge, NY (631) FAX (631) Copyright SMSC All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC s website at SMSC is a registered trademark of Standard Microsystems Corporation ( SMSC ). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 7