USB interface USB 2.0 # of NAND devices supported up to 4 10MBps/8MBps (single NAND) / 10MBps/10MBps (multi NAND) Operating Supply 3.0V to 3.

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1 ST768 USB.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLER PRELIMINARY DATA USB.0 Interface compatible with Mass Storage Device Class Integrated USB.0 PHY Supports USB High Speed and Full Speed Suspend and Resume operations Mass Storage Controller Interface (MSCI) Supports all type of NAND Flash devices Reed-Solomon Encoder/Decoder for MLC NAND Flash support: on-the-fly correction ( bytes of a -byte block) Flash identification support 0MB/s for read and 8MB/s for write operations with one single NAND Flash device 0MB/s for read and 0MB/s for write operations in multi mode NAND Flash device topology Embedded ST7 8-bit MCU Supply Management.V operation Integrated.V-.8V voltage regulator Very low power consumption Less than 00mA during write operation with two NAND Flash devices Less than 00µA in suspend mode Clock Management Integrated PLL for generating core and USB.0 clock sources using an external MHz crystal Up to two configurable LED outputs Blinking on USB specific activity (idle, suspend, data access) TQFP8 Data Protection Write protect switch control Password-based security for data protection Bootability support Flexibility Configurable Vendor ID/Product ID (VID/PID) with production tool Patch code support with external EEPROM device TQFP8 7x7 lead-free package Development Support Complete reference design including schematics, BOM and gerber files Supports Windows ME, Windows K, Windows XP, Linux and MacOS. Drivers available for Windows 98 SE Features ST768 USB interface USB.0 # of NAND devices supported up to R/W speed 0MBps/8MBps (single NAND) / 0MBps/0MBps (multi NAND) Operating Supply.0V to.6v Operating Temperature 0 C to +70 C Packages TQFP8 7x7 / Die form Rev.. May 00 / This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

2 ST768 INTRODUCTION The ST768 is a USB.0 high-speed Flash Drive controller. The USB.0 high-speed interface including PHY and function supports USB.0 Mass Storage Device Class. The Mass Storage Controller Interface combined with the Reed-Solomon Encoder/Decoder on-thefly correction (-byte on -byte data blocks) provides a flexible, high transfer rate solution for interfacing a wide of range NAND Flash memory device types. The internal 60 MHz PLL driven by the MHz oscillator is used to generate the 80MHz frequency for the USB.0 PHY. The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data and patch code are stored in internal RAM. I/O ports provide functions for EEPROM connection, LEDs and write protect switch control. The internal.v to.8v voltage regulator provides the.8v supply voltage to the digital part of the circuit. Figure. Device Block Diagram MHz OSC 8-bit CPU ROM RAM USB.0 USB.0 PHY Function Mass Storage Controller Interface Reed- Solomon Error Correction NAND I/F.V to.8v Voltage Regulator GPIO /

3 ST768 PIN DESCRIPTION Figure. 8-Pin TQFP Package Pinout VSS_ VDD_ * NAND D[0] NAND D[] NAND D[] NAND D[] NAND D[] NAND D[] NAND D[6] NAND D[7] NAND RnB VDDA OSCIN OSCOUT VSSA RREF VSSC VDDC VDD USBDP USBDM VSSBL VDDBL ST NAND WP READ ONLY EEPROM SCL VSS_ VDD_ * * RESET LED LED NAND ALE/EEPROM SDA VSS_ VDDOUSB VSS_ VDD_ NAND CE NAND CE NAND CE NAND CE NAND RE NAND WE NAND CLE * VDD_ * must remain NOT connected in the application /

4 ST768 PIN DESCRIPTION (Cont d) Legend / Abbreviations for tables: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C T = CMOS 0.V DD /0.7V DD with input trigger T T = TTL 0.8V / V with Schmitt trigger Output level: D8 = 8mA drive D = ma drive D = ma drive Port and control configuration: Input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt Output: OD = pseudo open drain, PP = push-pull The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table. Power Supply Pin Pin Name Type 8 VSS_ S Ground Description 7 VDD_ S IOs and Regulator supply voltage VSS_ S Ground VDD_ S IOs and Regulator supply voltage VSS_ S Ground VDD_ S IOs and Regulator supply voltage VSS_ S Ground VDD_ S IOs and Regulator supply voltage VDDOUSB S USB PHY, OSC and PLL power supply output (.8V) Table. Control & System Pin Level TQFP8 Pin Name Type Power Input Output Description 9 RESET I/O. C T Reset input with filter with internal pull-up /

5 ST768 PIN DESCRIPTION (Cont d) Table. USB.0 Interface Pin TQFP8 Pin Name Type Description VDDBL S Supply voltage for buffers and deserialisation flip flops (.8V) VSSBL S Ground for buffers and deserialisation flip flops (.8V) 0 USBDM I/O USB DATA - 9 USBDP I/O USB DATA + 8 VDD S Supply voltage for the FS compliance (.V) 7 VDDC S Supply voltage for DLL & xor tree (.8V) 6 VSSC S Ground for DLL & XOR tree (.8V) RREF I/O Ref. resistor for integrated impedance process adaptation (. kohms % Pull Down) Table. USB.0 and core Clock System Pin TQFP8 Pin Name Type VSSA S Ground for osc & PLL (.8V) OSCOUT O MHz oscillator output OSCIN I MHz oscillator input VDDA S Supply voltage for osc & PLL (.8V) Description /

6 ST768 PIN DESCRIPTION (Cont d) Table. General Purpose IO Ports / Mass Storage IOs Pin TQFP8 Pin Name Type Input Level NAND D[0] I/O T T D NAND DATA [0] NAND D[] I/O T T D NAND DATA [] NAND D[] I/O T T D NAND DATA [] NAND D[] I/O T T D NAND DATA [] NAND D[] I/O T T D NAND DATA [] 0 NAND D[] I/O T T D NAND DATA [] 9 NAND D[6] I/O T T D NAND DATA [6] 8 NAND D[7] I/O T T D NAND DATA [7] 6 NAND ALE / EEPROM SDA Outputs Main function (after reset) Alternate function I/O T T D8 NAND ADDRESS LATCH ENABLE EEPROM SERIAL DATA NAND CLE O T T D8 NAND COMMAND LATCH ENA- BLE NAND WE O T T D8 NAND WRITE ENABLE 0 NAND RE O T T D8 NAND READ ENABLE 9 NAND CE O T T D NAND ENABLE 8 NAND CE O T T D NAND ENABLE 7 NAND CE O T T D NAND ENABLE 6 NAND CE O T T D NAND ENABLE 7 NAND RnB I T T D NAND READY/BUSY 6 NAND WP O T T D NAND WRITE PROTECT READ ONLY I T T D READ ONLY SWITCH EEPROM SCL O T T D EEPROM SERIAL CLOCK 8 LED O T T D8 GREEN LED (USB ACCESS) 7 LED O T T D8 RED LED (NAND ACCESS) 6/

7 ST768 NAND FLASH DEVICE SUPPORT Type Memory size Program Page Size (in Bytes) Samsung K9F808U0C-Y 6M x 8b 8 Samsung K9F608U0C-Y M x 8b 8 Samsung K9F08U0A-Y 6M x 8b 8 Toshiba TC8FT 6M x 8b 8 Toshiba TC8DVM9A 6M x 8b 8 Toshiba TC8DVG0A 8M x 8b 8 Toshiba TC8DVG0BFT00 8M x 8b 8 Toshiba TC8DVGBFT00 6M x 8b 8 ST NAND8WA 6M x 8b 8 ST NAND6WA M x 8b 8 ST NANDWA 6M x 8b 8 ST NAND0GWA 8M x 8b 8 Hynix HY7US088M 6M x 8b 8 Hynix HY7US086M M x 8b 8 Hynix HY7US08M 6M x 8b 8 Samsung K9FG08U0M-Y 8M x 8b Samsung K9FG08U0M-Y 6M x 8b Samsung K9KG08U0M-Y 6M x 8b Samsung K9KG08U0M-Y M x 8b Samsung K9WG08U M x 8b Samsung K9W8G08U G x 8b Toshiba TH8NVG0S 8M x 8b Toshiba TH8NVGS 6M x 8b Toshiba TH8NVGS M x 8b ST NAND0GWB 8M x 8b ST NAND0GWB 6M x 8b Hynix HY7UA08GM 8M x 8b Micron 9FG08AA 6M x 8b 7/

8 ST768 APPLICATION SCHEMATICS Figure. Application Schematic Sheet / D D USB_V U Vin Vout C 0nF C 0nF C 0nF C 0nF GND INHIBIT BYPASS LD98MR_SOT-L C 0nF + C8.7uF C0 0nF D0 D D D D D D6 D7 NAND_VCC NAND NAND Sheet C R.7K D[7..0] C NAND_RnB NAND_WP NAND_CE NAND_CE NAND_CE NAND_CE NAND_RE NAND_WE NAND_CLE NAND_RnB NAND_WP B USB_V C C9 00nF uf J VBUS D- D+ GND USB CON V8_USB C0 8pF XT CRYSTAL MHz_M V8_USB C 8pF R.K % DP DM V8_USB VDDA OSCIN OSCOUT VSSA RREF VSSC VDDC VDD USBDP USBDM VSSBL VDDBL VSS_ VDD_ NAND D[0] NAND D[] NAND D[] NAND D[] NAND D[] NAND D[] NAND D[6] NAND D[7] NAND RnB RO ST768 NAND WP READ ONLY EEPROM SCL VSS_ VDD_ RESET NAND ALE/EEPROM SDA VSS_ UST7 S Read Only R 0K C RESET 00nF PE PE VDDOUSB VSS_ VDD_ NAND CE NAND CE NAND CE NAND CE NAND RE NAND WE NAND CLE VDD_ PE LED 7 LED 6 R 0 PE R 0 NAND_CE NAND_CE NAND_CE NAND_CE NAND_RE NAND_WE NAND_CLE NAND_RnB NAND_WP EEPROM_SCL U E0 VCC E nwc E SCL VSS SDA MCW_TSSOP8 NAND_VCC R6 8K B C6 0nF C7 0nF C8 0nF C 70nF LED RED LED LED GREEN LED NAND_CE NAND_CE NAND_CE NAND_CE NAND_RE NAND_WE NAND_CLE A A Title PFD/Ref B CPU Size Number Revision B Release A Date: 0-May-00 Sheet of Drawn By: File: /

9 C B C B ST768 Figure. Application Schematic Sheet / D A Date: -May-00 Sheet of Drawn By: Size A Number Revision Release PFD/Ref NAND Title NAND_RnB NAND_RnB R_Samsung W_config R_SW NAND_WP NAND_RE NAND_WE NAND_CLE NAND_WP NAND_RE NAND_CE NAND_CE NAND_WE NAND_CE NAND_CE NAND_CLE NAND_CE NAND_CE NAND_CE NAND_CE R_Toshiba_config R_T GND/NAND_RnB NAND_RnB NAND_RE NAND_CE NAND_CE C6 00nF 00nF NAND_CLE NAND_WE NAND_WP On Board Flash On Board Flash NAND_RnB 6 NAND_RnB 7 NAND_RE 8 NAND_CE 9 NAND_CE 0 NAND_CLE 6 7 NAND_WE 8 NAND_WP 9 0 C7 8 /#RES 7 6 I/O 7 GND/RB/ I/O 6 #R/B I/O #RE I/O 0 #CE 9 /#CE 8 /PRE 7 VCC VCC 6 VSS VSS CLE ALE I/O #WE I/O 0 #WP I/O 9 I/O U NAND_FLASH_TSOP8 8 /#RES 7 6 I/O 7 GND/RB/ I/O 6 #R/B I/O #RE I/O 0 #CE 9 /#CE 8 /PRE 7 VCC VCC 6 VSS VSS CLE ALE I/O #WE I/O 0 #WP I/O 9 I/O U NAND_FLASH_TSOP8 D7 D6 D D C 00nF D D D D0 D7 D6 D D C 00nF D D D D0 D[7..0] D[7..0] B D A 9/

10 ST768 PACKAGE MECHANICAL DATA Figure. 8-Pin Thin Quad Flat Package D D A b A A Dim. mm inches Min Typ Max Min Typ Max A A A b C D E E e D E E e L L c θ θ L L Number of Pins N 8 0/

11 ST768 6 REVISION HISTORY Table 6. Revision History Date Revision Description of Changes May-00. Changed status of the document Changed description on st page Removed unconnected pins in Table on page 6 Changed Table, USB.0 and core Clock System, on page Changed pin description in Table, USB.0 Interface, on page Changed section on page 7 Changed Figure and Figure /

12 ST768 Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 00 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia Belgium - Brazil - Canada - China Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America /

13 This datasheet has been downloaded from: Datasheets for electronic components.