Operating Systems. Paging... Memory Management 2 Overview. Lecture 6 Memory management 2. Paging (contd.)

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Raymond Daniels
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1 Operating Systems Lecture 6 Memory management 2 Memory Management 2 Overview Paging (contd.) Structure of page table Shared memory Segmentation Segmentation with paging Virtual memory Just to remind you... logical address page table physical address Paging...

Invalid bit in page table Pages not used by process no corresponding frame invalid bit set trap if addressed Structure of the page table Page table can be large spans the whole

Solutions Page table length register Hierachical page table Hashed page table Inverted page table Hierarchical page table Divide logical address in several parts outer table index

2 Invalid bit in page table Pages not used by process no corresponding frame invalid bit set trap if addressed Structure of the page table Page table can be large spans the whole address space Example: 4kb pages and 32 bit address space 2^(32-2)=2^2 entries in page table if entry is 4 bytes (32 bits), table is 4MB 64 bits architechtures? have to do something! Solutions Page table length register Hierachical page table Hashed page table Inverted page table Hierarchical page table Divide logical address in several parts outer table index inner table index offset (as usual) requires less space invalid page of outer table no table at all for inner table requires more memory lookups hardware support logical address: p p2 d 2

Hierarchical page table Several levels of hierarchy possible SPARC support three levels MC683 support four levels Very large address space are still handled poorly 64-bit

hash function Inverted page table Regular page table for each page in address space store frame number (map from pages to frames) very large table for large address spaces

3 Hierarchical page table Several levels of hierarchy possible SPARC support three levels MC683 support four levels Very large address space are still handled poorly 64-bit addresses would require seven levels Hashed page table table size no direct relation to size of address space used for very large address spaces Issues collision in hash table hash function Inverted page table Regular page table for each page in address space store frame number (map from pages to frames) very large table for large address spaces Logical address space larger than physical memory Inverted page table for each fram in physical memory store page number (map from frames to pages) table size depend on amount of physical memory 3

4 Inverted page table Map frames to pages but... we want to map pages to frames! how to do that? search the table in some way hash table could be used to speed up search Only one table in the system for all processes same page present several times for different processes include process id in table Used by several architechtures UltraSPARC, PowerPC,... Inverted page table TLB searched first then inverted table Searching the inverted table is very slow linear search Shared memory Code can be shared between processes several instances of the same program dynamic link library self-modifying code does not work! should never be used anyway must appear in the same memory location in each process why? program addresses becomes wrong otherwise Data can be shared can appear anywhere in the address space 4

Shared memory on paged system Map pages from different processes to the same (shared) frame big problem with inverted page table only one page entry per frame let the mem ref.

5 Shared memory on paged system Map pages from different processes to the same (shared) frame big problem with inverted page table only one page entry per frame let the mem ref. trap handle the mapping in kernel slower Segmentation User memory divided into segments address specified as <segment number, offset> Motivation segments represent semantically defined portions of user memory: code, data, stack,... segments can be defined read, write, execute, just as pages Segments can be shared between processes Segmentation architecture Address: <segment, offset> the segment is often implicit set in a register in the cpu Each process has a segment table one entry in table is: base: physical address of start of segment limit: size of segment works in the same way as contiguous memory allocation MMU Segment-table base register (STBR) Segment-table length register (STLR) 5

Segmentation example memory holes same problem as

per segment Segmentation hardware similar to contiguous

6 Segmentation example memory holes same problem as contiguous allocation several logical address spaces one per segment Segmentation hardware similar to contiguous allocation use table instead of register memory protection segment size flags read/write/execu te... Shared segments Share segments code several instances of same program shared libraries data 6

Allocation of segments Segments can have different sizes dynamic storage allocation problem search for holes, first fit, bestr fit, etc... external fragmentation Solution to this? compaction?

7 Allocation of segments Segments can have different sizes dynamic storage allocation problem search for holes, first fit, bestr fit, etc... external fragmentation Solution to this? compaction? slow, but works IBM OS/2.3 uses this scheme not that slow though... better solution? Segmentation with paging Combine both segmentation and segmentation Segment table does not contain physical addresses page numbers Paging scheme solves external fragmentation Needs hardware support Best of two worlds? Segmentation with paging the i386 segmentation 2-level paging 7

Virtual memory Overview Virtual memory idea Demand paging page fault page replacement page replacement algorithms Virtual memory considerations memory over-allocation Working set model Efficient

8 Virtual memory Overview Virtual memory idea Demand paging page fault page replacement page replacement algorithms Virtual memory considerations memory over-allocation Working set model Efficient process creation yes it has to do with virtual memory! Memory mapped files Virtual memory Separate logical memory from physical memory earlier, we separated logical addresses from physical, now we separate the actual memory Only part of process need to be in physical memory transparent to the process Emulate more memory than is present use secondary storage performance is decrease if used carelessly performance is increased if used wisley better resource utilization Allows processes to share files efficiently More efficient process creation Implementation demand paging demand segmentation Idea of virtual memory Use disk as memory Transparent for user process load back into memory as needed 8

Demand paging Paging with swapping entire process is swapped in/out of memory process needs to be completely in memory in order to run swapper module swaps processes in/out Demand paging individuasl

9 Demand paging Paging with swapping entire process is swapped in/out of memory process needs to be completely in memory in order to run swapper module swaps processes in/out Demand paging individuasl pages are moved to/from secondary storage as needed only small part (working set) of process needs to be in memory pager module moves pages to/from secondary storage reference to page not in memory traps to pager module Page table includes invalid bit indicates page not present either page not used by process (as previously) or... page not presently in physical memory needs to be loaded if needed Demand paging Page fault Acess to page marked invalid is called a page fault trap to kernel Actions taken by kernel on page fault decide if access is invalid or if page not in memory choose an empty frame (if there are any) load page from disk into the empty frame update page table and TLB and set valid-bit to restart instruction that caused the fault 9

Demand paging Demand paging Hardware must be able to restart instruction not as easy as it might look complex instructions might write to a valid page and then to an invalid page what to do with the

10 Demand paging Demand paging Hardware must be able to restart instruction not as easy as it might look complex instructions might write to a valid page and then to an invalid page what to do with the completed write? Pure demand paging only bring requested pages into memory process started with zero pages in memory and immediately faults Performance of demand paging Costly to service page fault I/O is slow memory access time: to 2 ns disk access time ms Disk is a factor of ^6 slower than memory when it comes to access time Few page faults crucial Efficient swap space handling crucial swap space often handled separate from file systems increase performance a bit

No free frames Page replacement No free frames some frame needs to be replaced page replacement algorithm select page to be replaced Pages needs to be saved (paged out) before replaced by new pages

11 No free frames Page replacement No free frames some frame needs to be replaced page replacement algorithm select page to be replaced Pages needs to be saved (paged out) before replaced by new pages is page not changed since load discard without save page table contains dirty bit maintained by hardware set on page write reduce i/o overhead only dirty pages are paged out Basic page replacement strategy Find location of desired page on disk Find free frame if exists use it in not find a victim frame (page replacement algo) write out the victim fram to disk, if dirty Read desired page into free frame Restart process Page replacement p pages frame valid dirty RAM (frames): swap space: p access

12 Page replacement algorithms What page to replace? Page replacement algo should give lowest page fault rate Algorithm evaluation run on a sequence of memory references compute number of page faults for that sequence Reference sequence generated using some distribution traces of actual memory references FIFO Page replacement algorithms Optimal LRU Counting algorithms Second chance enhanced second chance Page buffering Next lecture... More on virtual memory page replacement algorithms process allocation memory mapped files memory over-allocation 2

Chapter 8 & Chapter 9 Main Memory & Virtual Memory

Chapter 8 & Chapter 9 Main Memory & Virtual Memory 1. Various ways of organizing memory hardware. 2. Memory-management techniques: 1. Paging 2. Segmentation. Introduction Memory consists of a large array