STM32F4 Introduction F1/F2/F4 Comparison Features Highlight

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1 STM32F4 Introduction F1/F2/F4 Comparison Features Highlight February 20 th 2012

2 2 Content Product family overview F1/F2/F4 features comparisons Features highlight Boot & Remap feature RTC calibration & synchronization Reset & Regulator features I2S New Feature F1 to F2 to F4 porting guide

3 3 Content Product family overview F1/F2/F4 features comparisons Features highlight Boot & Remap feature RTC calibration & synchronization Reset & Regulator features I2S New Feature F1 to F2 to F4 porting guide

4 STM32 leading Cortex-M portfolio

5 STM32 product series 4 product series

6 STM32 F4 portfolio 2

7 STM32 F4 block diagram Feature highlight 168 MHz Cortex-M4 CPU Floating point unit (FPU) ART Accelerator TM Multi-level AHB bus matrix 1-Mbyte Flash, 192-Kbyte SRAM 1.7 to 3.6 V supply RTC: <1 µa typ, sub second accuracy 2x full duplex I²S 3x 12-bit ADC 0.41 µs/2.4 MSPS 168 MHz timers 2

8 8 Content Product family overview F1/F2/F4 features comparisons Features highlight Boot & Remap feature RTC calibration & synchronization Reset & Regulator features I2S New Feature F1 to F2 to F4 porting guide

9 SRAM Comparison F4 Series F2 Series F1 Series Embedded SRAM 112K+64K+16K 112K+16K 64K Battery Backed-up SRAM 4K Bytes Not available 9

10 Flash Comparison F4 Series F2 Series F1 Series Embedded Flash (in Bytes) 512K, 1M 128K, 256K, 512K, 768K, 1M 16K, 32K, 64K, 128K, 256K, 384K, 512K, 768K, 1M User Flash sectors/ page sizes (in Bytes) 4*16K + 1*64K + 7*128K (sectors) 1K/page or 2K/page Depending on part number System Flash (Bytes) 30K 2K/6K/18K Option Bytes (Bytes) OTP area (Bytes) 528 Not available Prefetch 2*128bits 2*64bits Read interface Write interface Cache Instructions + data branch caches Not available Nb of Waitstates Depends on HCLK & Voltage range Depends only on HCLK Erase Mass erase or Sector erase Mass erase or Page erase Program 8bits / 16bits / 32bits / 64bits 16bits Vpp Provided externally (8V~9V ) Not available 10

11 Power supply architecture F4 Series F2 Series F1 Series Vdd Voltage Range 1.8V(1.7V) ~ 3.6V 1.8V(1.65V) ~ 3.6V 2.0V ~ 3.6V Vbat Voltage Range 1.65V ~ 3.6V 1.65V ~ 3.6V 1.8V ~ 3.6V Vdda ADC operational 1Msps 1.8V(1.7V)~3.6V 1Msps 1.8V(1.65V)~3.6V 2.4V ~ 3.6V Range ADC not operational 2Msps 2.4V~3.6V 2Msps 2.4V~3.6V 2.0V ~ 3.6V Running mode Available Available Power modes Sleep mode Available Available Standby mode Available Available Bypass mode Available Not Available Low power mode voltage regulator To power the SRAM when in low power mode Not Available Core voltage 1.2V 1.8V Additional power pin V cap1/2 To external provide 1.2V for the core Not Available V pp 7V - 9V Not Available 11

12 Clock schemes comparison F4 Series F2 Series F1 Series HSE Frequency Range 4~26MHz ( Bypass mode :1-26Mhz ) 4~16MHz & 3~25MHz LSE Frequency kHz kHz HSI typical freq. 16MHz 8MHz HSI typical freq. 32kHz 40kHz AHB/APB1/APB2 Maximum frequencies AHB : 168MHz APB1 : 42MHz APB2 : 84Mhz AHB : 120MHz APB1: 30MHz APB2 : 60MHz AHB : 72MHz APB1 : 36MHz APB2 : 72MHz PLL Dual PLL:PLL1 system clock and 48MHz clock PLL2 (for I2S audio) 1 or 3 PLLs MCO output MCO1 (PA.8) or MCO2 (PC.9) MCO (PA.8) Calibration Available via Timer5 Ch4 & Timer 11 ch1 Available via Timer5 Ch4 & Timer 11 ch1 Available via timer5 channel4 13

13 GPIO Features comparison F4 Series F2 Series F1 Series Operating modes Support 8/16/32Bits access BSRR[32] Supports only 32bits Access BSRR/BRR[32] Configuration Locking Available Available Available I/O Bandwidth 2/25/50/100/200MHz 2/25/50/100MHz 2/10/50 MHz Max toggling frequency 84MHz (AHB) 60MHz (AHB) 18MHz (APB2) Remap feature Switch selection Alternate function selectable pin by pin Available, each I/O has a internal switch to select the feature to connect to it. Group remapping Not available group remapping 14

14 ADC Features comparison F4 Series F2 Series F1 Series ADC1 Channels Channels 0~18 Channels 0~17 Conversion time (Sampling + conversion) Sampling time + 12/10/8/6 cycles for conversion time Sampling time cycles Max. ADC clock 36MHz * 30/15MHz * 14MHz ADC Trigger Raising or falling edge Raising edge Precision 12bits / 10 bits / 8bits / 6bits 12bits Precision Vs Speed Precision reduction to speed up conversion Not available Vbatt test Vbat/2 internally connected on Channel 18 Not available ADC Master/ Slave ADC1 Master ADC2 & ADC3 Slaves ADC1 Master /ADC2 Slave ADC3 standalone *Please refer to the datasheet for the ADC voltage range 15

15 F4 and F2 Improved ADC performances Total conversion time = T sample + T conversion Allow compromise between precision & conversion time Example : T sample =3 ADC cycles (smallest) For a ADC clock frequency of 30MHz Precision Conversion time Total conversion time 12 Bits 12 ADC clock cycles 12+3=15 cycles 0.5us 2Mbps 10 Bits 10 ADC clock cycles 10+3=13 cycles 0.433us 2.30Mbps 8 Bits 8 ADC clock cycles 8+3=11 cycles 0.366us 2.72Mbps 6 Bits 6 ADC clock cycles 6+3=9 cycles 0.3us 3.33Mbps These performances can be further improved (3x) by using the interleaved modes of the STM32 s ADC 16

16 RTC Features comparison F4 Series F2 Series F1 Series Calendar type Hardware D/M/Y + sub second register Hardware D/M/Y 32bits counter Alarm wakeup 16bits counter Not Available Calibration 50/60Hz high precision calibration input Not available Interrupts/ Wake up event Periodical wakeup / alarm/ tamper /timestamp Second/alarm/ overflow/ tamper Alarms AlarmA AlarmB AlarmA Backup registers 20 registers = 80Bytes 20 Bytes / 84 Bytes GPIO output Calibration/alarm/wakeup Calibration/alarm/se cond GPIO Input Tamper / timestamp Tamper input Protection after reset Unlock sequence available on all devices (not exactly the same between the devices) 17

17 DMA Features comparison F4 Series F2 Series F1 Series DMA Channels = = 12 DMA Requests DMA Request selected explicitly by a register ORED => Conflicts FIFO Each Channel as 4*32bits FIFO Not available Burst Mode Available Not available Software Trigger Channel priorities Peripheral flow control Available Software + Hardware priorities Available for the SDIO peripheral Available Software + Hardware priorities Not Available Interrupt flags 5 (DMA FIFO error/direct transfer error) 3 18

USART Feature comparison F4 Series F2 Series F1 Series Oversampling Selectable : 8bits /16bits Fixed 16bits Max baudrate 84MHz / 8 = 10.5Mbps 60MHz / 8 = 7.5Mbps 72MHz / 16 = 4.

18 USART Feature comparison F4 Series F2 Series F1 Series Oversampling Selectable : 8bits /16bits Fixed 16bits Max baudrate 84MHz / 8 = 10.5Mbps 60MHz / 8 = 7.5Mbps 72MHz / 16 = 4.5Mbps Sample point Selectable : 1 sample point or 3 sample points Fixed 3 sample points USART6 Available Not Available Note : reducing the number of sampling point (in noisefree environment) allows to increase the clock deviation tolerance Example : oversampling = 16bits,3 sampled points 19

19 SPI Features Max clock frequency F4 Series F2 Series F1 Series 37.5MHz 30MHz 18MHz TI Mode support Available Available Not available 8/16 位 20

20 Timer Features F4 Series F2 Series F1 Series Advanced timers TIM1/8 16bits up/down counter; 4 Channels IC/OC/PWM ; Complementary output & dead-time insertion (motor control) Standard timers TIM2~5 TIM3/4 : 16bits up/down counter TIM2/5 : 32bits up/down counter 4 Channels IC/OC/PWM 16bits up/down counter 4Channels IC/OC/PWM Basic timers TIM6/7 Standard timers TIM9/12 Standard timers 10/11/13/14 16Bits up/down counter;can be used as DAC trigger timers 16Bits up/down counter;2 Channels IC/OC/PWM 16Bits up/down counter;1 Channel IC/OC/PWM 21

21 Other features NVIC and EXTI F4 Series F2 Series F1 Series Maskable interrupts External interrupt/ wake up event 87 23,(including new event 3) High-speed OTG Mode wake up / RTC Wake up/rtc 60/68 20 F2 & F4 compared to F1 (other differences) : SDIO 48MHz clocked from PLL2 (F1 from AHB Clock) DAC operational on full voltage range (F1 2.4V) IWDG source clock 32kHz (F1Series =40kHz) reduced frequency = longer maximum watchdog timing 22

22 23 Content Product family overview F1/F2/F4 features comparisons Features highlight Boot & Remap feature RTC calibration & synchronization Reset & Regulator features I2S New Feature F1 to F2 to F4 porting guide

23 24 The STM32 Buses I-Bus : Instruction fetch in the address range 0x to 0x1FFFFFFF D-Bus : Data access in the address range 0x to 0x1FFFFFFF Best execution in Harvard architecture (when code is fetched from the I-Bus) S-Bus : Instruction fetch, Data access, peripheral access in the other address range

25 What is the FSMC remap feature FSMC is connected on the I-bus for faster code execution FSMC is also connected on the D-bus for faster data access FSMC is connected on the S bus This is the only

24 25 What is the FSMC remap feature FSMC is connected on the I-bus for faster code execution FSMC is also connected on the D-bus for faster data access FSMC is connected on the S bus This is the only configuration on STM32F1 This is the default configuration on STM32F2/F4 On STM32F2 this S-bus link is disconnected when I-Bus/D-Bus access is enabled On STM32F4 this S-bus link is always available even when I-Bus/D-Bus access is enable

25 26 The remap feature BOOT and SW Remap SW Remap only

26 27 The STM32F2xx Boot feature The boot part is similar to the STM32F1xx It is not possible to boot from the FSMC A software remap feature has been added IMPORTANT : The BOOT0/1 Marking on the MB786 Rev.A is inverted (the switch written as boot0 is indeed the boot1)

27 28 The remap register : SYSCFG_MEMRMP After reset the register takes the value of the boot pins (except if Boot0=0 and Boot1=1) Boot from the FSMC is not possible, so after reset If Boot0=0 and Boot1=1 the device starts from the main flash and the reset value of this register is 0b00 The FSMC remap (0b10) can only be enabled by software

29 Example 1 : boot0=0, Boot1=0 The main flash is remapped at address 0x00000000 The MCU boots from the main flash The

configuration the main flash is accessible from both address ranges : 0x00000000 and 0x08000000 It is recommended to keep the

28 29 Example 1 : boot0=0, Boot1=0 The main flash is remapped at address 0x The MCU boots from the main flash The SYSCFG_MEMRMP register reset value is 0x The vector table is at its default address 0x Notes : in this configuration the main flash is accessible from both address ranges : 0x and 0x It is recommended to keep the code in the non-remapped main flash address range (0x ). This will avoid the code to be remapped unexpectedly to other areas by software

system memory The SYSCFG_MEMRMP register reset value is

29 30 Example 2 : boot0=1, Boot1=0 The system memory is remapped at address 0x The MCU boots from the system memory The SYSCFG_MEMRMP register reset value is 0x The vector table is at its default address 0x

31 Example 3 : boot0=0, Boot1=1 The main flash is remapped at address 0x00000000 The MCU boots from the main flash The SYSCFG_MEMRMP

configuration, the boot from main flash is enforced by the hardware (SYSCFG_MEMRMP is initialized to 0x00000000) For the remap the FSMC

30 31 Example 3 : boot0=0, Boot1=1 The main flash is remapped at address 0x The MCU boots from the main flash The SYSCFG_MEMRMP register reset value is 0x The vector table is at its default address 0x NO BOOT Important Notes : In this configuration, the boot from main flash is enforced by the hardware (SYSCFG_MEMRMP is initialized to 0x ) For the remap the FSMC to be effective (right column), the firmware will have to configure the FSMC and then write 0x2 in the SYSCFG_MEMRMP (see next slide for complete sequence)

31 32 FSMC Remap Sequence 1. Configure Boot0/1 to boot from the main flash 2. Run the application code from the address 0x ( nonremapped main flash) 3. Remap the Vector Table to the non-remapped main flash area 0x Enable the SYSCFG Clock 5. Remap the FSMC by writing 0x2 into the SYSCFG_MEMRMP register Notes : This sequence does not maximize the security, to further secure it additional configuration is required (use of priviledges, MPU ) After Remap, the original FSMC address range (0x x9FFFFFFFF) is still accessible (STM32F4xx). After Remap, the first 2 blocks of the Bank1 are also accessible in the remapped area (bank1 block1 : 0x x03FFFFFF and bank1 block2 : 0x x07FFFFFF

32 33 Content Product family overview F1/F2/F4 features comparisons Features highlight Boot & Remap feature RTC calibration & synchronization Reset & Regulator features I2S New Feature F1 to F2 to F4 porting guide

33 34 STM32F2 Vs F4 : RTC differences Calendar STM32 F2 12/24 format Hour / Min / seconds STM32 F4 12/24 format Hour / Min / seconds / Subsecond Max resolution : 30.52µs (clk = 32768Hz) Shadow register bypass No Yes synchronization No Yes - On the fly synchronization Calibration type Coarse calibration Coarse & Smooth calibration Calibration windows 64 minutes 8s / 16s / 32s (On the fly) Calendar Calibration steps Alarm on calendar Time stamp Tamper detection Negative:-2ppm Positive: +4ppm 2 x alarms Sec, Min, Hour, Date/day Sec, Min, Hour, Date/day YES (2 pins /1 event) Edge Detection only Smooth calib. Negative or Positive: 3.81ppm / 1.91ppm / 0.95 ppm 2 x alarms : Sec, Min, Hour, Date/day, Sub seconds Sec, Min, Hour, Date/day, Sub seconds YES (2 pins / 2 events) Edge detection or Level Detection (with filtering)

35 Subsecond counter The Date/Time is updated with the 1Hz clock coming out of the synchronous prescaler The sub-second field is the value of the

34 35 Subsecond counter The Date/Time is updated with the 1Hz clock coming out of the synchronous prescaler The sub-second field is the value of the synchronous prescaler s counter. This field is not writable. Therefore the precision of the sub second counter depends on the PREDIV_S value (see next slide)

35 36 Subsecond counter Prediv_A SS Clock Prediv_S Sub second counter PREDIV_S high PREDIV_A low to get 1Hz Higher current consumption Higher input frequency (SS Clock) higher sub second precision (best precision is µs if SS Clock=32768 Hz) PREDIV_S low PREDIV_A high to get 1Hz Lower current consumption Lower input frequency (SS Clock) Lower sub second precision

37 F2 & F4 RTC Clock calibration F2 calibration coarse calibration after the prescaler Resolution : 4ppm Range 63 ppm to 126 ppm: F4 calibration Coarse calibration after the asynchronous prescaler

36 37 F2 & F4 RTC Clock calibration F2 calibration coarse calibration after the prescaler Resolution : 4ppm Range 63 ppm to 126 ppm: F4 calibration Coarse calibration after the asynchronous prescaler Resolution : 4ppm Range 63 ppm to 126 ppm: smooth calibration on the fly before the asynchronous prescaler Resolution : ppm to ppm Range : -511 to +512 RTCCLK Note : On the STM32F4, the two calibration methods are not intended to be used together, the application must select one of the two methods. Coarse calibration is provided for compatibly reasons.

37 39 The coarse calibration (F2 & F4) The 512Hz clock output is before the calibration Cannot check its effect The 1Hz clock output is after the synchronous prescaler allows to check it Available on the STM32F4 only The calibration setting can only be changed during initialization Cannot be updated on the fly Suitable for static compensation Not suitable for temperature compensation The coarse calibration cannot be used together with the smooth calibration STM32F2 STM32F4

38 40 The smooth calibration (F4 Only) The smooth calibration is available : On the STM32F1 devices On the STM32F4 devices Both the 512Hz clock and 1Hz clock outputs are after the calibration Both allows to check it The calibration setting Can be updated on the fly Suitable for static compensation Also suitable for temperature or other compensation The smooth calibration is more precise Precision (ppm) Smooth calibration Coarse calibration -2 and +4 The smooth coarse calibration cannot be used together with the coarse calibration Range (ppm) -244 ~ ~ ~ ~ +126

39 41 The synchronization This allows to synchronize the clock to a master clock without modifying the calibration. This is available : On the STM32F1 devices On the STM32F4 devices This mechanism allow to adjust the calendar by adding or removing a few fractions from its counter. The shift function has no impact on the RTC clock. Therefore its effect cannot be seen on the AFO_Calib output the shift operation is initiated by a write into the RTC_SHIFTR register (on the fly) This feature is not compatible with the reference clock detection

40 42 The reference clock calibration The RTC provides a reference clock input (RTC_50Hz pin) that can be used to compensate the imprecision of the calendar frequency (1 Hz). Features : The reference clock calibration and the coarse calibration can not be used together. The reference clock calibration and the synchronization can not be used together. The reference clock calibration is the best (ensures a high calibrated time) if the 50 Hz is always available. If the 50 Hz input is lost, the LSE can be used. The reference clock detection can not be used in Vbat mode. The reference clock calibration can only be used if you provide a precise 50 or 60 Hz input.

41 43 Content Product family overview F1/F2/F4 features comparisons Features highlight Boot & Remap feature RTC calibration & synchronization Reset & Regulator features I2S New Feature F1 to F2 to F4 porting guide

42 F4/F2 Reset & Power regulator features Power supply range 1.8(1.7)~3.6V Lowering the power supply may impact the performances of some peripherals. Refer to the datasheet. Option to disable the internal reset circuit (if disabled, and external reset circuit is required ) 44

43 45 Regulator-Reset : what is available on F2/F4? Regulator ON Internal Regulator Bypass Brown out reset off Voltage Scaling Reset ON Regulator OFF STM32F2 STM32F4 STM32F2 STM32F4 LQFP64 Always enabled LQFP64 Not available LQFP100 Always ON Available LQFP100 Not available LQFP144 Always ON Available LQFP144 Not available WLCS66 Available Available WLCS66 Available Available UFBGA176 Available Available UFBGA176 Available Available LQFP64 Not available LQFP64 Not available Reset OFF LQFP100 N/A Available LQFP100 Not available LQFP144 N/A Available LQFP144 Not available WLCS66 N/A Available WLCS66 Available Available UFBGA176 N/A Available UFBGA176 N/A Available

44 46 F2/F4 : Regulator-Reset : when to use what Reset ON Reset OFF Regulator ON Only one Vdd power supply No need for external reset device This is the default configuration Available on all F2/F4 packages Only one Vdd power supply Need external reset circuit To use when the MCU need to run with a Vdd lower than 1.8V Check datasheet for minimum Vdd Available on F4 only LQFP100/144 UFBGA176 packages Regulator OFF Need Vdd & 1.2V power supplies No need for external reset circuit To use an external regulator Available on F2/F4 on WLCS66 and UFBGA176 packages Need Vdd & 1.2V power supplies Need external reset circuit To use when the MCU need to run with a Vdd lower than 1.8V Check datasheet for minimum Vdd While allowing the customer to use their own external regulator Available on WLCS66 (F2/F4) and UFBGA176 (F4 only) packages

45 47 F4 : Regulator ON - Reset ON/OFF details Internal Regulator Bypass Brown out reset off Voltage Scaling Reset ON Regulator ON : low power modes and conditions to respect There are three low-power modes: MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes Power-down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). Reset OFF There are three low-power modes: MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes Power-down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). The following conditions must be respected: NRST pin should be controlled by an external reset controller to keep the device under reset when VDD is below 1.7 V

46 48 F4 : Regulator OFF - Reset ON/OFF details Internal Regulator Bypass Brown out reset off Voltage Scaling Reset ON Regulator OFF : conditions to respect This mode allows to power the device as soon as VDD reaches 1.7 V. An 1.2 V source is supplied through VCAP_1 and VCAP_2 pins, in addition to VDD The following conditions must be respected: VDD should always be higher than VCAP_1 and VCAP_2. If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to reach 1.7 V, then PA0 should be connected to the NRST pin. Otherwise, PA0 should be asserted low externally during POR until VDD reaches 1.7 V. PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the internal regulator is off. This mode allows to power the device as soon as VDD reaches 1.7 V. An 1.2 V source is supplied through VCAP_1 and VCAP_2 pins, in addition to VDD Reset OFF The following conditions must be respected: VDD should always be higher than VCAP_1 and VCAP_2. PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V and until VDD reaches 1.7 V. NRST should be controlled by an external reset controller to keep the device under reset when VDD is below 1.7 V

47 51 Content Product family overview F1/F2/F4 features comparisons Features highlight Boot & Remap feature RTC calibration & synchronization Reset & Regulator features I2S New Feature F1 to F2 to F4 porting guide

48 I2S Half duplex Vs Full duplex STM32F2 I 2 S I 2 S SCK WS SD Out Half duplex (config. OUT) SCK WS SD In Half duplex (config. IN) STM32F4 I 2 S SCK WS SD out SD in Full duplex (IN & OUT) STM32F2 : 2xI 2 S Half duplex STM32F4 : 2xI 2 S Full duplex

49 53 Content Product family overview F1/F2/F4 features comparisons Features highlight Boot & Remap feature RTC calibration & synchronization Reset & Regulator features I2S New Feature F1 to F2 to F4 porting guide

50 54 IDE support for STM32F4 IDE versions natively supporting the STM32F4 - IAR 6.30 (see the release note) - Keil Version 4.22a - Atollic version 2.2 (2.3 preferred) -

51 About the pin to pin compatibility The devices are functional pin-to-pin compatible There are minor differences on the power supply pins QFP64 QFP100 QFP144 F1 QFP64 QFP100 QFP144 F2 & F PD0 - OSC_IN PH0 - OSC_IN PD1 - OSC_OUT VSSA VDD PH1 - OSC_OUT VREF VSSA VSS_ VCAP NC VCAP VSS_ VSS VSS_3 63 VSS_ VDD_SA 55

52 About the pin to pin compatibility STM32F4 and STM32F2 are hardware pin to pin compatible. Just pay attention to the F2 RFU pin software compatible STM32F4 and STM32F2 work with the same IDE STM32F1 and STM32F4 are Functional pin to pin compatible But not fully pin to pin compatible for the power supply part Compatible designs are detailed in the next slides. 56

53 LQFP144 STM32F1 compatible design Connected to Vss for the F1 series Connected to Vdd for F2 and F4 series Solder a 0ohm resistor for F1 series Keep it open for F2 and F4 series 57

54 LQFP100 STM32F1 compatible design Connected to Vss for the F1 series Connected to Vdd for F2 and F4 series Solder a 0ohm resistor for F1 series Keep it open for F2 and F4 series 58

55 LQFP64 STM32F1 compatible design Solder a 0ohm resistor for F1 series Keep it open for F2 and F4 series 59

56 Thanks - 谢谢!

Hello, and welcome to this presentation of the STM32L4 power controller. The STM32L4 s power management functions and all power modes will also be

Hello, and welcome to this presentation of the STM32L4 power controller. The STM32L4 s power management functions and all power modes will also be covered in this presentation. 1 Please note that this