Jin-Fu Li Dept. of Electrical Engineering National Central University
|
|
- Priscilla Gregory
- 5 years ago
- Views:
Transcription
1 Memory Built-In Self-Repair Dept. of Electrical Engineering National Central University Jungli, Taiwan
2 Introduction Outline Redundancy Organizations Built-In Redundancy Analysis Built-In Self-Repair Infrastructure IP for Memory Yield Improvement References 2
3 Introduction Difficulties in System-On-Chip Designs Timing closure Verification & testing Yield improvement Memories usually dominate the chip area Memories will cover 90% of an SOC die area by 2011 Thus the memory yield heavily impacts the SOC yield Increasing memory yield can significantly increase the SOC yield 3
4 Example Notebook Graphic Controller um CMOS 2. 24M-bit edram k logic gates, 83M Hz Source: Courtesy NeroMagic 4
5 Yield of an SOC SOC Yield Y S = Y M Y L Improve the yields of memories can drastically increase the yields of SOCs For example, UltraSparc chip yield Source: R. Rajsuman IEEE D&T,
6 Conventional Memory Repair Flow Test Laser Repair Error Logging Test Bitmaps Redundancy Analysis Requirements: 1. Memory tester 2. Laser repair equipment Disadvantages: 1. Time consuming 2. Expensive 6
7 The Conventional Approach for SOCs Memory repair in SOCs Memory Tester Laser Repair Large capture memory, redundancy analysis Swap the defective cells Memory Tester Test the repaired memories Logic Tester Test the remaining non-memory components Problems Cost: time cost & equipment cost Accessibility Laser repair become more difficult 7
8 Memory BISR is Indispensable BISR for SOCs Built-In Self-Test (BIST) Test Built-In Self-Diagnosis (BISD) Diagnostics Built-In Redundancy Analyzer (BIRA) Redundancy allocation Redundancy Reconfiguration Swap the defective cells Within 5 years (~2006), 100% high capacity memories are equipped with BISR (ITRS 2001) 8
9 Typical Memory BIST Architecture Normal I/Os Test Controller Test Pattern Generator Test Collar RAM Comparator 9
10 NTHU-FTC BISD Architecture ADD RD ID WEB O CS OE BEF BSO BSI BMS BSC BRS BGO FSI CTR ERR EOP CONT CM D TGO DONE ENA TPG ADDR_T DI_T DO_T WEB_T CS_T OE_T ADDR_S DI_S DO_S WEB_S CS_S OE_S SRAM CLK Test_se 10
11 BISD in Diagnosis Mode In diagnosis i mode, the BISD can run userspecified march algorithm for test/diagnosis EOP format: Addr Session Syndrome A sample of timing diagram is as follows CLK ERR EOP BEF BSO CONT 11
12 Typical Memory BISR Architecture Normal I/Os BIRA BIST Reco onfigura ation m echanism Test Collar & RAM Redundancy 12
13 Redundancy Organizations A memory array with local redundancies Bank 1 Bank k2 Local lspare Columns Local Spare Rows 13
14 Redundancy Organizations A memory array with hybrid redundancies Bank 1 Bank k2 Local Spare Rows Global (Linked) Spare Columns 14
15 Redundancy Organizations A memory array with hybrid redundancies Bank 1 Bank 2 Bank 2 Bank k2 Global (Linked) Spare Rows Local Spare Columns 15
16 Reconfiguration Techniques Three kinds of reconfiguration techniques Soft (programmed) By programming FFs to store reconfiguration information which can connect spare rows or columns Disadvantage: repair process must be performed when the power is turned on; some potential faults cannot be repaired Soft/Firm (programmed) By programming non-volatile memories to blow soft fuses internally and connect spare rows or columns Disadvantage: high-voltage h programming circuitry is usually needed 16
17 Reconfiguration Techniques Hard (permanent) Laser-blown or electrically-blown polysilicon or diffusion fuses Disadvantages: 1) there techniques are not part of standard CMOS technology, and incorporating them into the process technology and then adding repairing steps after the chip is made cause the cost to increase; 2) allow one-time programming, and any field-related error correction and fault tolerance is difficult to achieve These techniques can coexist in memory BISRs 17
18 Repair with Flash EEPROM Switches D0 D1 D2 D14 D Multiplexers Size: 768 kb/12 Rows: 512 Column: 128 Controller with 20 flash cells Q0 Q1 Q2 Q14 Q15 [R. J. McPartland, et al., IEEE CICC, 2000] 18
19 Redundancy Analysis The redundancy analysis problem is to choose the minimum number of spare rows and columns that cover all the faulty cells The complexity of 2-D redundancy analysis 2-D redundancy analysis problem is NP- complete The time required to determine repair solution is crucial factor 19
20 Example 1: Redundancy Analysis
21 Example 2: Redundancy Analysis
22 2D Redundancy Analysis Algorithm Typical redundancy analysis algorithms for RAMs with 2D redundancy (spare rows/columns) Two-phase redundancy allocation procedure: must- repair phase and final-repair phase Must-repair phase Row-must repair (column-must repair): a repair solution forced by a failure pattern with >S C (>S R ) defective cells in a single row (column), where S C and S R denote the number of available spare columns and spare rows Final-repair phase Heuristic algorithms are usually used, e.g., repair- most rule 22
23 Redundancy Analysis Using ATE Create a fault map which size is the same as the memory under test Column Counters Row Execute software-based redundancy analysis using computer in ATE Counters 23
24 Redundancy Analysis Using ATE Hardware necessary to execute the redundancy analysis A device image memory (or fault memory) The size is the same as the memory under test Counters that indicate the number of faults that occur in a row, or a column Apparently, the conventional software-based redundancy analysis algorithms are not adapted to be realized with hardware and be embedded into the SOCs Hardware overhead is too large Efficient built-in redundancy-analysis (BIRA) algorithms are required to be developed d 24
25 Types of BISR Off-line BISR On-line BISR BISR Strategies Off-line BISR without BIRA ability BIST + reconfiguration mechanism Off-line BISR with BIRA ability BIST + BIRA + reconfiguration mechanism On-line BISR 25
26 Examples of BISR Design NEC BISR design without BIRA (JSSC92) Mb I/O Buffer I/O Memory Array Spare 21 16wx32b 21 Memory ROM TPG Comparator Fail CAM BIST Block 16wx21b BISR Block 26
27 Examples of BISR Design A BISR design (ITC98) Data Input Bus Main Memory Spare Memory Redundancy Analysis Algorithm Information Reconfiguration Control Unit Column Decoder 27
28 Main idea BIRA Algorithms CRESTA Exhaustive search with parallel multiple hardware implementations For example, assume that a memory with 2 spare rows (Rs) & 2 spare columns (Cs), then all possible repair solutions R-R-C-C (Solution 1) R-C-R-C R C (Solution 2) R-C-C-R (Solution 3) C-R-R-C R C (Solution 4) C-R-C-R (Solution 5) C-C-R-R (Solution 6) 28
29 BIRA Algorithms CRESTA Comprehensive Real-time Exhaustive Search Test and Analysis Parallel algorithms For example, Solution 1 (R-R-C-C) R C) 29
30 BIRA Algorithms CRESTA Analysis flow chart Start Test Fail? Yes No S1 S2 S3 S6 Finish? Yes Result Output No End 30
31 Review Basic Idea of CRESTA Assume that there are m spare rows and n spare columns in a memory. Then a CRESTA repair analyzer contains C(m+n, m) subanalyzers E.g., if 2 spare rows and 2 spare columns are available, CRESTA will need C(4, 2)=6 sub-analyzers Each sub-analyzer analyzes in-coming row/column addresses of faulty memory cells in parallel l in a different repair strategy t using spare rows/columns Because CRESTA tries all the possible repair strategies of spare resources, it guarantees finding a solution for a repairable memory 31
32 Limitation of CRESTA However, since CRESTA needs row address and column address of a faulty memory cell in order to check if the current faulty memory cell can be repaired by previously allocated spare resources It is unable to handle at-speed multiple-bit failure occurring in a word-oriented memory due to the fact that determining the number of spare columns needed for all failure bits in a word cannot be achieved in one cycle To solve this at-speed problem, a column repair vector (CRV) is used to store column failure information By analyzing CRV at the end of memory BIST will allow post BIST analysis to determine whether a given repair strategy can repair or not 32
33 At-Speed BISR Example of redundancy allocation CCRR (Unrepairable) CRRC
34 At-Speed BISR Implementation Restart BIST Controller Fail/Success Memory Under Test BISRA Controller Repair Data Repairable In the BISRA, all C(m+n, m) analysis engines or just one engine can be implemented In one engine scheme, update the repair strategy if the current repair strategy fails and then re-run BIST and try the next repair strategy 34
35 At-Speed BISR Implementation Fail Map Address SRA CAR BISRA Engine SRA CAR A B I T E R Fail Map Address Restart SRA CAR BISRA Engine RSR BISRA Engine BISRA controller with C(m+n, m) engines BISRA controller with one engine 35
36 Basic Components of BISRA Spare Resource Allocation (SRA): allocates either a spare row or a spare column according to its repair strategy Control and Report (CAR): checks if this repair strategy fails If not, it will report the repair data, such as faulty row addresses and CRV, to BISRA controller if Arbiter grants the right to it Repair Strategy Reconfiguration (RSR) block: it updates the repair strategy and sends a restart signal to BIST controller 36
37 Early Abort Method E.g., let a memory have 2 spare rows and 2 spare columns, and the current repair strategy is CCRR If after reserving a spare column we find that the number of ones in CRV exceeds 2, we can conclude that the memory cannot be repaired by any repairing strategy beginning with a spare column R C R C C R C R C R R C C C R R C R 37
38 RAM BISR Using Redundant Words The BISR methodology contains memory BIST logic, wrapper logic to replace defect words, and fuse boxes to store the failing addresses Only spare words are used for replacing defective cells Avoid redundancy calculation The BISR will be no additional delay in the data path of the memory Without penalty on total test time Redundancies can be activated immediately within 1 cycle 38
39 The RAM BISR Architecture Address, Data Input, Control BIST Mux Fuse Box Redundancy Logic RAM Mux Source: V. Schober, et. al, ITC01. 39
40 Redundancy Wrapper Logic The redundancy logic consists of two basic components Spare memory words Logic to program the address decoding The address comparison is done in the redundancy logic The address is compared to the addresses that are stored in the redundancy word lines An overflow bit identifies that there are more failing addresses than possible repair cells The programming of the faulty addresses is done during the memory BIST or from the fuse box during memory setup 40
41 An Array of Redundant Word Lines MBIST Address Write Data Address, Data Input, Control F Address Expected Data Fail fail Fail Address RAM Data TDI FA Address Data RAM Word Redundancy FA Address Data FA Address Data FO Control Overflow TDO Data out Source: V. Schober, et. al, ITC01. 41
42 Applications of Redundancy Logic Faulty addresses can be streamed out after test completion. Then the fuse box is blown accordingly in the last step of the test This is called here hard repair This is normally done at wafer level test Furthermore, the application can be started immediately after the memory BIST passes This is called here soft repair 42
43 Redundancy Word Line Fail Fail_address A R W DI Expected_data TDI FA Address Data TDO Comparator & & Read Fail Fail_address Expected_data, DO Source: V. Schober, et. al, ITC01. 43
44 Issues about Fuse Boxes From a testing point of view, three problems arise: The logic of fuse box has to be tested An easy way to set fuse values from external source without blowing the fuse is helpful This allows a pre-fuse test and a proof of the determined faulty memory locations for reliability tests, yield improvements and diagnosis capabilities A possibility to read the fuse values directly after the fuse blowing process To enhance observability of the fuse process 44
45 One-Bit Fuse Box One-bit fuse box contains a fuse bit and a scan flip flop for controlling and observing the fuse data Test_Update=0: the chain of inverters is closed (The value is latched) Test_Update=1: It is possible to set the internal node from TDO The ports TDI and TDO are activated at scan mode Test_Update TDI FRest FRead 1 0 Scan FF TDO F out FRest FRead FGND Fuse Fuse Bit (FB) FGND Reset cycle to read out the fuse information t Source: V. Schober, et. al, ITC01. 45
46 Fuse Boxes The fuse box can be connected to a scan register to stream in and out data during test and redundancy configuration Update Reset Fuse Box FB FB FB TDI Scan FF Scan FF Scan FF TDO Fail A[0] A[N-1] Source: V. Schober, et. al, ITC01. 46
47 Parallel Access of the Fuse Information Fuse Box Fuse activation BIST FA Fuse Address Address to be fuse FA Fuse Address FA Address Register FA Fuse Address FA Address Register FA Address Register Redundancy Logic Source: V. Schober, et. al, ITC01. 47
48 Serial Access of the Fuse Information Fuse Box Fuse activation BIST TDI FA Fuse Address Address to be fuse FA Fuse Address FA Address Register FA Fuse Address FA Address Register FA Address Register TDO Redundancy Logic Source: V. Schober, et. al, ITC01. 48
49 Test Flow to Activate the Redundancy Initialization of the BIST Load faulty addresses Increment address Access memory No Yes Test finished? No Fail? Yes No Fuse to be blown? No Free register? Yes Yes Stream out faulty addresses Write expected data Write address Write Fail flag Soft repair Hard repair Unrepairable Source: V. Schober, et. al, ITC01. 49
50 NTHU/ADMtek BISR Scheme Redundancy organization SEG0 SEG1 SR0 SR1 SCG0 SCG1 SR: Spare Row; SCG: Spare Column Group; SEG: Segment 50
51 NTHU/ADMtek BISR Scheme Redundancy organization Q D A MAO BIRA Wrap pper Main Memory POR BIST Spare Memory MAO: mask address output; POR: power-on reset 51
52 NTHU/ADMtek BISR Scheme Power-on BISR procedure Power On BIST Test Spare Row & Column Error information BIRA BIST Test Main Memory Continue Error information BIRA Masked address BIRA Reduced address space Address Remapping Address 52
53 NTHU/ADMtek BISR Scheme Down-graded operation mode If the spare rows are exhausted, the memory is operated at down-graded mode The size of the memory is reduced For example, assume that a memory with multiple blocks is used for buffering and the blocks are chained by pointers If some block is faulty and should be masked, then the pointers are updated to invalidate the block The system still works if a smaller buffer is allowed 53
54 Definition NTHU/ADMtek BISR Scheme Subword A subword is consecutive bits of a word Its length is the same as the group size Example: a 32x16 RAM with 3-bit row address and 2- bit column address A word with 4 subwords A subword with 4 bits 54
55 NTHU/ADMtek BISR Scheme Row-repair rules To reduce the complexity, we use two row-repair repair rules A row has multiple faulty subwords Multiple faulty subwords with the same column address and different row addresses Examples: subword subword 55
56 NTHU/ADMtek BISR Scheme BIRA procedure Run BIST Detects a fault Check Row-Repair Rules Not met Done Met Stop Repair-Most Rules Check Available Spare Rows No available spare row Export Faulty Row Address 56
57 NTHU/ADMtek BISR Scheme Repair rate analysis Repair rate The ratio of the number of repaired memories to the number of defective memories A simulator has been implemented to estimate the repair rate of the proposed BISR scheme [Huang, et al., l MTDT, 2002] Industrial case: SRAM size: 8Kx64 # of injected random faults: 1~10 # of memory samples: 534 RA algorithms: proposed and exhaustive search algorithms 57
58 NTHU/ADMtek BISR Scheme Simulation results N SR N SC N SCG RR 1MA 2MA 3MA 4MA 5MA >5MA RR (Best) % % % 94.43% 99.26% % 99.81% 100% % 86.09% 99.26% 100% 72.17% 96.10% 99.81% 100% 72.36% 98.52% 100% 100% 85.90% 99.81% 100% 100% % 94.01% 100% 100% 55.06% 97.38% 100% 100% 71.91% 98.69% 100% 100% 85.77% 99.81% 100% 100% 58
59 NTHU/ADMtek BISR Scheme Layout view of the repairable SRAM Technology: 0.25um SRAM area: 6.5 mm 2 BISR area : 0.3 mm 2 Spare area : 0.3 mm 2 HO spare : 4.6% HO bisr : 4.6% Repair rate: 100% (if # random faults is no more than 10) Redundancy: 4 spare rows and 2 spare column groups Group size: 4 59
60 Infrastructure IP What is Infrastructure IP Advanced yield optimization solutions necessitate embedding a special type of IP blocks in a chip. Such IP blocks are called Infrastructure IP Unlike the functional IP cores used in SOCs, the infrastructure IP cores do not add to the main functionality of the chip Rather, they are intended to ensure the manufacturability of the SOC and to achieve lifetime reliability Examples of such infrastructure IPs Process monitoring IP, test & repair IP, diagnosis IP, timing measurement IP, and fault tolerance IP 60
61 Composite IP Infrastructure IP STAR Mem. Mem. Mem. Mem. IW IW IW IW STAR Processor 1 STAR Processor 2 Fuse Box P1500 Mem. IW 61
62 Infrastructure IP STAR The infrastructure IP is comprised of a number of hardware components, including A STAR Processor A Fuse Box Intelligent Wrappers (IW) The STAR Processor Performs all appropriate test & repair coordination i of a STAR memory It is programmed by a set of instructions to control the operation of the internal modules The Fuse Box May be made of laser fuses to allow single-time repair or may be built of non-volatile memory to perform multi-time time repair 62
63 Infrastructure IP STAR The Intelligent Wrapper (IW) Associated with each memory is used in conjunction with the STAR Processor to perform test and repair of the memory as well as allow normal memory functioning in the system The IW contains Address counters, registers, data comparators and multiplexers The architectural partitioning between the functions contained in IW and the STAR Processor Depend on the infrastructure IP bandwidth requirements 63
64 References [1] Y. Zorian, Embedded memory test & repair: infrastructure IP for SOC yield, Proc. Int. Test Conf. (ITC), Oct., 2002, pp [2] D.-K. Bhavsar, An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21246, Proc. Int. Test Conf. (ITC), Oct., 1999, pp [3] R.-Rajsuman, Design and test of large embedded memories: an overview, IEEE Design & Test, May/June, 2001, pp [4]T. Kawagoe, et al., A built-in self-repair analyzer (CRESTA) for embedded DRAMs, Proc. Int. Test Conf. (ITC), Oct., [5] I.-Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, Built in self repair for embedded high density SRAM, in Proc. Int. Conf. (ITC), Oct. 1998, pp [6] J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, A built-in self-repair scheme for semiconductor memories with 2-D redundancy, Proc. Int. Test Conf. (ITC), Sep., [7] Volker Schober, Steffen Paul, and Olivier Picot, Memory built-in selfrepair using redundant words, Infineon Technologies AG Balanstr.73,81541 Munich, Germany, / , IEEE 64
A Review paper on the Memory Built-In Self-Repair with Redundancy Logic
International Journal of Engineering and Applied Sciences (IJEAS) A Review paper on the Memory Built-In Self-Repair with Redundancy Logic Er. Ashwin Tilak, Prof. Dr.Y.P.Singh Abstract The Present review
More informationJin-Fu Li. Department of Electrical Engineering National Central University Jhongli, Taiwan
Yield eda and Reliability- Enhancement Techniques for Random Access Memories Jin-Fu Li Advanced d Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli,
More informationAN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS
International Journal of Engineering Inventions ISSN: 2278-7461, www.ijeijournal.com Volume 1, Issue 8 (October2012) PP: 76-80 AN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS B.Prathap Reddy
More informationA Built-In Redundancy-Analysis Scheme for RAMs with 2D Redundancy Using 1D Local Bitmap
A Built-In Redundancy-Analysis Scheme for RAMs with D Redundancy Using D Local Bitmap Tsu-Wei Tseng, Jin-Fu Li, and Da-Ming Chang Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering
More informationRE-CONFIGURABLE BUILT IN SELF REPAIR AND REDUNDANCY MECHANISM FOR RAM S IN SOCS Ravichander Bogam 1, M.Srinivasa Reddy 2 1
RE-CONFIGURABLE BUILT IN SELF REPAIR AND REDUNDANCY MECHANISM FOR RAM S IN SOCS Ravichander Bogam 1, M.Srinivasa Reddy 2 1 Department of Electronics and Communication Engineering St. Martins Engineering
More informationBuilt-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs Shyue-Kung Lu and Shih-Chang Huang Department of Electronic Engineering Fu Jen Catholic University Hsinchuang, Taipei, Taiwan 242, R.O.C.
More informationNear Optimal Repair Rate Built-in Redundancy Analysis with Very Small Hardware Overhead
Near Optimal Repair Rate Built-in Redundancy Analysis with Very Small Hardware Overhead Woosung Lee, Keewon Cho, Jooyoung Kim, and Sungho Kang Department of Electrical & Electronic Engineering, Yonsei
More informationA Proposed RAISIN for BISR for RAM s with 2D Redundancy
A Proposed RAISIN for BISR for RAM s with 2D Redundancy Vadlamani Sai Shivoni MTech Student Department of ECE Malla Reddy College of Engineering and Technology Anitha Patibandla, MTech (PhD) Associate
More informationDesign and Implementation of Microcode based Built-in Self-Test for Fault Detection in Memory and its Repair
Design and Implementation of Microcode based Built-in Self-Test for Fault Detection in Memory and its Repair C. Padmini Assistant Professor(Sr.Grade), ECE Vardhaman college of Engineering, Hyderabad, INDIA
More informationAn Area-Efficient BIRA With 1-D Spare Segments
206 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 1, JANUARY 2018 An Area-Efficient BIRA With 1-D Spare Segments Donghyun Kim, Hayoung Lee, and Sungho Kang Abstract The
More information3D Memory Formed of Unrepairable Memory Dice and Spare Layer
3D Memory Formed of Unrepairable Memory Dice and Spare Layer Donghyun Han, Hayoug Lee, Seungtaek Lee, Minho Moon and Sungho Kang, Senior Member, IEEE Dept. Electrical and Electronics Engineering Yonsei
More informationAn Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy Philipp Öhler and Sybille Hellebrand University of Paderborn Germany {oehler,hellebrand}@uni-paderborn.de Hans-Joachim Wunderlich
More informationAn Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement Chin-LungSu,Yi-TingYeh,andCheng-WenWu Laboratory for Reliable Computing (LaRC) Department of Electrical Engineering National
More informationOptimized Built-In Self-Repair for Multiple Memories
Optimized Built-In Self-Repair for Multiple Memories Abstract: A new built-in self-repair (BISR) scheme is proposed for multiple embedded memories to find optimum point of the performance of BISR for multiple
More informationDesign and Implementation of Improved BISR Strategy for Systems-on-a-Chip (SoC)
RESEARCH ARTICLE OPEN ACCESS Design and Implementation of Improved BISR Strategy for Systems-on-a-Chip (SoC) Mr. D. Sri Harsha 1, Mr. D. Surendra Rao 2 1 Assistant Professor, Dept. of ECE, GNITC, Hyderabad
More informationTest/Repair Area Overhead Reduction for Small Embedded SRAMs
Test/Repair Area Overhead Reduction for Small Embedded SRAMs Baosheng Wang and Qiang Xu ATI Technologies Inc., 1 Commerce Valley Drive East, Markham, ON, Canada L3T 7X6, bawang@ati.com Dept. of Computer
More informationA Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan 320 Jen-Chieh Yeh, Rei-Fu Huang, and
More informationSram Cell Static Faults Detection and Repair Using Memory Bist
Sram Cell Static Faults Detection and Repair Using Memory Bist Shaik Moulali *, Dr. Fazal Noor Bhasha, B.Srinivas, S.Dayasagar chowdary, P.Srinivas, K. Hari Kishore Abstract Memories are one of the most
More informationModeling and Simulation of Multi-Operation Microcode-based Built-in Self Test for Memory Fault Detection and Repair
Modeling and Simulation of Multi-Operation Microcode-based Built-in Self Test for Memory Fault Detection and Repair Dr. R.K. Sharma and Aditi Sood Abstract As embedded memory area on-chip is increasing
More informationImproving Memory Repair by Selective Row Partitioning
200 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Improving Memory Repair by Selective Row Partitioning Muhammad Tauseef Rab, Asad Amin Bawa, and Nur A. Touba Computer
More informationBuilt-in self-repair (BISR) technique widely Used to repair embedded random access memories (RAMs)
Built-in self-repair (BISR) technique widely Used to repair embedded random access memories (RAMs) V.SRIDHAR 1 M.RAJENDRA PRASAD 2 1 Assistant Professor, ECE, Vidya Jyothi Institute of Technology, Hyderabad
More informationDesign and Implementation of Built-in-Self Test and Repair
P.Ravinder, N.Uma Rani / International Journal of Engineering Research and Applications (IJERA) Design and Implementation of Built-in-Self Test and Repair P.Ravinder*, N.Uma Rani** * (Guru Nanak Institute
More informationEfficient Built In Self Repair Strategy for Embedded SRAM with selectable redundancy
Efficient Built In Self Repair Strategy for Embedded SRAM with selectable redundancy *GUDURU MALLIKARJUNA **Dr. P. V.N.REDDY * (ECE, GPCET, Kurnool. E-Mailid:mallikarjuna3806@gmail.com) ** (Professor,
More informationScalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN)
Scalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN) Abstract With increasing design complexity in modern SOC design, many memory
More informationSelf-Repair for Robust System Design. Yanjing Li Intel Labs Stanford University
Self-Repair for Robust System Design Yanjing Li Intel Labs Stanford University 1 Hardware Failures: Major Concern Permanent: our focus Temporary 2 Tolerating Permanent Hardware Failures Detection Diagnosis
More informationA Universal Test Pattern Generator for DDR SDRAM *
A Universal Test Pattern Generator for DDR SDRAM * Wei-Lun Wang ( ) Department of Electronic Engineering Cheng Shiu Institute of Technology Kaohsiung, Taiwan, R.O.C. wlwang@cc.csit.edu.tw used to detect
More informationAS THE capacity and density of memory gradually
844 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 25, NO. 3, MARCH 2017 Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares Jooyoung Kim, Woosung Lee,
More informationBuilt-in i Repair Analysis 2010. 10. 20 Woosik.jeong@hynix.com Contents 1. RA 2. BIRA 3. Previous Works 4. Summary 1/ 38 1. RA 2. BIRA 3. Previous Works 4. Summary 2/ 38 Repair What is Repair? Replacing
More informationEmbedded Quality for Test. Yervant Zorian LogicVision, Inc.
Embedded Quality for Test Yervant Zorian LogicVision, Inc. Electronics Industry Achieved Successful Penetration in Diverse Domains Electronics Industry (cont( cont) Met User Quality Requirements satisfying
More informationCOEN-4730 Computer Architecture Lecture 12. Testing and Design for Testability (focus: processors)
1 COEN-4730 Computer Architecture Lecture 12 Testing and Design for Testability (focus: processors) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University 1 Outline Testing
More informationOptimal Built-In Self Repair Analyzer for Word-Oriented Memories
Optimal Built-In Self Repair Analyzer for Word-Oriented Memories B.Prabhakaran 1, J.Asokan 2, Dr.G.K.D.PrasannaVenkatesan 3 Post Graduate student- ME in Communication Systems 1, Assistant Professor 2,Vice
More informationTHREE algorithms suitable for built-in redundancy analysis
386 IEEE TRANSACTIONS ON RELIABILITY, VOL. 52, NO. 4, DECEMBER 2003 Built-In Redundancy Analysis for Memory Yield Improvement Chih-Tsun Huang, Member, IEEE, Chi-Feng Wu, Member, IEEE, Jin-Fu Li, Member,
More informationRepair Analysis for Embedded Memories Using Block-Based Redundancy Architecture
, July 4-6, 2012, London, U.K. Repair Analysis for Embedded Memories Using Block-Based Redundancy Architecture Štefan Krištofík, Elena Gramatová, Member, IAENG Abstract Capacity and density of embedded
More informationDigital Integrated Circuits
Digital Integrated Circuits Lecture Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University Design/manufacture Process Chung EPC655 2 Design/manufacture Process Chung EPC655 3 Layout
More informationChapter 1. Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Dept. of Electrical Engineering. Jhongli, Taiwan
Chapter 1 Introduction to Memorie Advanced Reliable Sytem (ARES) Lab. Dept. of Electrical Engineering it Jhongli, Taiwan Outline Importance of Embedded Memorie Overview of Memory Structure 2 Embedded Memory
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 10 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Content Manufacturing Defects Wafer defects Chip defects Board defects system defects
More informationEmbedded Static RAM Redundancy Approach using Memory Built-In-Self-Repair by MBIST Algorithms
Embedded Static RAM Redundancy Approach using Memory Built-In-Self-Repair by MBIST Algorithms Mr. Rakesh Manukonda M.Tech. in VLSI &ES, MLEC, Singarayakonda, Mr. Suresh Nakkala Asst. Prof. in E.C.E MLEC,
More information(Advanced) Computer Organization & Architechture. Prof. Dr. Hasan Hüseyin BALIK (5 th Week)
+ (Advanced) Computer Organization & Architechture Prof. Dr. Hasan Hüseyin BALIK (5 th Week) + Outline 2. The computer system 2.1 A Top-Level View of Computer Function and Interconnection 2.2 Cache Memory
More informationBlock Sparse and Addressing for Memory BIST Application
Block Sparse and Addressing for Memory BIST Application Mohammed Altaf Ahmed 1, D Elizabath Rani 2 and Syed Abdul Sattar 3 1 Dept. of Electronics & Communication Engineering, GITAM Institute of Technology,
More informationLecture 13: SRAM. Slides courtesy of Deming Chen. Slides based on the initial set from David Harris. 4th Ed.
Lecture 13: SRAM Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports
More informationMULTIPLE FAULT DIAGNOSIS FOR HIGH SPEED HYBRID MEMORY ARCHITECTURE
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 2, Issue. 5, May 2013, pg.33
More informationDiagnostic Testing of Embedded Memories Using BIST
Diagnostic Testing of Embedded Memories Using BIST Timothy J. Bergfeld Dirk Niggemeyer Elizabeth M. Rudnick Center for Reliable and High-Performance Computing, University of Illinois 1308 West Main Street,
More informationBIST-Based Test and Diagnosis of FPGA Logic Blocks 1
BIST-Based Test and Diagnosis of FPGA Logic Blocks 1 Miron Abramovici Bell Labs - Lucent Technologies Murray Hill, NJ Charles Stroud 2 Dept. of Electrical and Computer Engineering University of North Carolina
More informationAn Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy
An Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy A. Sharone Michael.1 #1, K.Sivanna.2 #2 #1. M.tech student Dept of Electronics and Communication,
More informationMemory. Outline. ECEN454 Digital Integrated Circuit Design. Memory Arrays. SRAM Architecture DRAM. Serial Access Memories ROM
ECEN454 Digital Integrated Circuit Design Memory ECEN 454 Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports DRAM Outline Serial Access Memories ROM ECEN 454 12.2 1 Memory
More informationGLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES A NOVAL BISR APPROACH FOR EMBEDDED MEMORY SELF REPAIR G. Sathesh Kumar *1 & V.
GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES A NOVAL BISR APPROACH FOR EMBEDDED MEMORY SELF REPAIR G. Sathesh Kumar *1 & V. Saminadan 2 *1 Research Scholar, Department of ECE, Pondcherry Engineering
More informationBUILT IN REDUNDANCY ALGORITHMS FOR MEMORY YIELD ENHANCEMENT
International Journal of Electronics and Communication Engineering and Technology (IJECET) Volume 9, Issue 3, May-June 2018, pp. 13 22, Article ID: IJECET_09_03_002 Available online at http://www.iaeme.com/ijecet/issues.asp?jtype=ijecet&vtype=9&itype=3
More informationAdvanced Reliable Systems (ARES) Laboratory. National Central University Jhongli, Taiwan
Chapter 7 Memory Testing Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Importance of Embedded Memories RAM
More informationMemory System Design. Outline
Memory System Design Chapter 16 S. Dandamudi Outline Introduction A simple memory block Memory design with D flip flops Problems with the design Techniques to connect to a bus Using multiplexers Using
More informationCHAPTER TWELVE - Memory Devices
CHAPTER TWELVE - Memory Devices 12.1 6x1,024 = 16,384 words; 32 bits/word; 16,384x32 = 524,288 cells 12.2 16,384 addresses; one per word. 12.3 2 16 = 65,536 words = 64K. Thus, memory capacity is 64Kx4.
More informationEmbedded Systems Design: A Unified Hardware/Software Introduction. Outline. Chapter 5 Memory. Introduction. Memory: basic concepts
Hardware/Software Introduction Chapter 5 Memory Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 1 2 Introduction Memory:
More informationEmbedded Systems Design: A Unified Hardware/Software Introduction. Chapter 5 Memory. Outline. Introduction
Hardware/Software Introduction Chapter 5 Memory 1 Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 2 Introduction Embedded
More informationMemory and Programmable Logic
Digital Circuit Design and Language Memory and Programmable Logic Chang, Ik Joon Kyunghee University Memory Classification based on functionality ROM : Read-Only Memory RWM : Read-Write Memory RWM NVRWM
More informationAtmel AT94K FPSLIC Architecture Field Programmable Gate Array
Embedded Processor Based Built-In Self-Test and Diagnosis of FPGA Core in FPSLIC John Sunwoo (Logic BIST) Srinivas Garimella (RAM BIST) Sudheer Vemula (I/O Cell BIST) Chuck Stroud (Routing BIST) Jonathan
More informationBIST is the technique of designing additional hardware and software. features into integrated circuits to allow them to perform self testing, i.e.
CHAPTER 6 FINITE STATE MACHINE BASED BUILT IN SELF TEST AND DIAGNOSIS 5.1 Introduction BIST is the technique of designing additional hardware and software features into integrated circuits to allow them
More information8051 INTERFACING TO EXTERNAL MEMORY
8051 INTERFACING TO EXTERNAL MEMORY Memory Capacity The number of bits that a semiconductor memory chip can store Called chip capacity It can be in units of Kbits (kilobits), Mbits (megabits), and so on
More informationCHAPTER 12 ARRAY SUBSYSTEMS [ ] MANJARI S. KULKARNI
CHAPTER 2 ARRAY SUBSYSTEMS [2.4-2.9] MANJARI S. KULKARNI OVERVIEW Array classification Non volatile memory Design and Layout Read-Only Memory (ROM) Pseudo nmos and NAND ROMs Programmable ROMS PROMS, EPROMs,
More informationA Case Study. Jonathan Harris, and Jared Phillips Dept. of Electrical and Computer Engineering Auburn University
Built-In Self-Test for System-on on-chip: A Case Study Charles Stroud, Srinivas Garimella,, John Sunwoo, Jonathan Harris, and Jared Phillips Dept. of Electrical and Computer Engineering Auburn University
More informationMemory Controller. Speaker: Tzu-Wei Tseng. Adopted from National Taiwan University SoC Design Laboratory. SOC Consortium Course Material
Memory Controller Speaker: Tzu-Wei Tseng Adopted from National Taiwan University SoC Design Laboratory SOC Consortium Course Material Goal of This Lab Familiarize with ARM memory interface Know ARM Integrator
More informationEvaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks Charles Stroud, Ping Chen, Srinivasa Konala, Dept. of Electrical Engineering University of Kentucky and Miron Abramovici
More informationLecture 11 SRAM Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 11 SRAM Zhuo Feng 11.1 Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitryit Multiple Ports Outline Serial Access Memories 11.2 Memory Arrays
More informationCOMP3221: Microprocessors and. and Embedded Systems. Overview. Lecture 23: Memory Systems (I)
COMP3221: Microprocessors and Embedded Systems Lecture 23: Memory Systems (I) Overview Memory System Hierarchy RAM, ROM, EPROM, EEPROM and FLASH http://www.cse.unsw.edu.au/~cs3221 Lecturer: Hui Wu Session
More informationAn Integrated ECC and BISR Scheme for Error Correction in Memory
An Integrated ECC and BISR Scheme for Error Correction in Memory Shabana P B 1, Anu C Kunjachan 2, Swetha Krishnan 3 1 PG Student [VLSI], Dept. of ECE, Viswajyothy College Of Engineering & Technology,
More informationPOWERFUL BISR DESIGN FOR EMBEDDED SRAM WITH SELECTABLE REDUNDANCY
POWERFUL BISR DESIGN FOR EMBEDDED SRAM WITH SELECTABLE REDUNDANCY 1 K Naveen, 2 AMaruthi Phanindra, 3 M Bhanu Venkatesh, 4 M Anil Kumar Dept. of Electronics and Communication Engineering, MLR Institute
More informationDesign for Test of Digital Systems TDDC33
Course Outline Design for Test of Digital Systems TDDC33 Erik Larsson Department of Computer Science Introduction; Manufacturing, Wafer sort, Final test, Board and System Test, Defects, and Faults Test
More informationBIST for Deep Submicron ASIC Memories with High Performance Application
BIST for Deep Submicron ASIC Memories with High Performance Application Theo J. Powell, Wu-Tung Cheng *, Joseph Rayhawk *, Omer Samman *, Paul Policke, Sherry Lai Texas Instruments Inc. PO Box 660199,
More informationEfficient BISR strategy for Embedded SRAM with Selectable Redundancy using MARCH SS algorithm. P. Priyanka 1 and J. Lingaiah 2
Proceedings of International Conference on Emerging Trends in Engineering & Technology (ICETET) 29th - 30 th September, 2014 Warangal, Telangana, India (SF0EC009) ISSN (online): 2349-0020 Efficient BISR
More informationExploiting Unused Spare Columns to Improve Memory ECC
2009 27th IEEE VLSI Test Symposium Exploiting Unused Spare Columns to Improve Memory ECC Rudrajit Datta and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering
More informationInternational Journal of Digital Application & Contemporary research Website: (Volume 1, Issue 7, February 2013)
Programmable FSM based MBIST Architecture Sonal Sharma sonal.sharma30@gmail.com Vishal Moyal vishalmoyal@gmail.com Abstract - SOCs comprise of wide range of memory modules so it is not possible to test
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 26: November 9, 2018 Memory Overview Dynamic OR4! Precharge time?! Driving input " With R 0 /2 inverter! Driving inverter
More informationMarch 20, 2002, San Jose Dominance of embedded Memories. Ulf Schlichtmann Slide 2. esram contents [Mbit] 100%
Goal and Outline IC designers: awareness of memory challenges isqed 2002 Memory designers: no surprises, hopefully! March 20, 2002, San Jose Dominance of embedded Memories Tomorrows High-quality SoCs Require
More informationMemory and Programmable Logic
Memory and Programmable Logic Memory units allow us to store and/or retrieve information Essentially look-up tables Good for storing data, not for function implementation Programmable logic device (PLD),
More informationOrganization. 5.1 Semiconductor Main Memory. William Stallings Computer Organization and Architecture 6th Edition
William Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory 5.1 Semiconductor Main Memory 5.2 Error Correction 5.3 Advanced DRAM Organization 5.1 Semiconductor Main Memory
More informationAt-Speed On-Chip Diagnosis of Board-Level Interconnect Faults
At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults Artur Jutman Tallinn University of Technology artur@pld.ttu.ee Abstract This article describes a novel approach to fault diagnosis suitable
More informationWilliam Stallings Computer Organization and Architecture 6th Edition. Chapter 5 Internal Memory
William Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory Semiconductor Memory Types Semiconductor Memory RAM Misnamed as all semiconductor memory is random access
More informationAddress connections Data connections Selection connections
Interface (cont..) We have four common types of memory: Read only memory ( ROM ) Flash memory ( EEPROM ) Static Random access memory ( SARAM ) Dynamic Random access memory ( DRAM ). Pin connections common
More informationSELF CORRECTING MEMORY DESIGN FOR FAULT FREE CODING IN PROGRESSIVE DATA STREAMING APPLICATION
SELF CORRECTING MEMORY DESIGN FOR FAULT FREE CODING IN PROGRESSIVE DATA STREAMING APPLICATION ABSTRACT Harikishore.Kakarla 1, Madhavi Latha.M 2 and Habibulla Khan 3 1, 3 Department of ECE, KL University,
More informationECE 485/585 Microprocessor System Design
Microprocessor System Design Lecture 4: Memory Hierarchy Memory Taxonomy SRAM Basics Memory Organization DRAM Basics Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering
More informationComputer Organization. 8th Edition. Chapter 5 Internal Memory
William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory Semiconductor Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM)
More informationSRAM. Introduction. Digital IC
SRAM Introduction Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories Memory Arrays Memory Arrays Random Access Memory Serial Access Memory
More informationBIST-Based Test and Diagnosis of FPGA Logic Blocks
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRUARY 2001 159 BIST-Based Test and Diagnosis of FPGA Logic Blocks Miron Abramovici, Fellow, IEEE, and Charles E. Stroud,
More information+1 (479)
Memory Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Memory Arrays Memory Arrays Random Access Memory Serial
More informationSemiconductor Memories: RAMs and ROMs
Semiconductor Memories: RAMs and ROMs Lesson Objectives: In this lesson you will be introduced to: Different memory devices like, RAM, ROM, PROM, EPROM, EEPROM, etc. Different terms like: read, write,
More informationWilliam Stallings Computer Organization and Architecture 8th Edition. Chapter 5 Internal Memory
William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory Semiconductor Memory The basic element of a semiconductor memory is the memory cell. Although a variety of
More informationFPGA Programming Technology
FPGA Programming Technology Static RAM: This Xilinx SRAM configuration cell is constructed from two cross-coupled inverters and uses a standard CMOS process. The configuration cell drives the gates of
More informationINTERCONNECT TESTING WITH BOUNDARY SCAN
INTERCONNECT TESTING WITH BOUNDARY SCAN Paul Wagner Honeywell, Inc. Solid State Electronics Division 12001 State Highway 55 Plymouth, Minnesota 55441 Abstract Boundary scan is a structured design technique
More informationBuilt-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs
Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs Sudheer Vemula, Student Member, IEEE, and Charles Stroud, Fellow, IEEE Abstract The first Built-In Self-Test (BIST) approach for the programmable
More informationDesign and Synthesis for Test
TDTS 80 Lecture 6 Design and Synthesis for Test Zebo Peng Embedded Systems Laboratory IDA, Linköping University Testing and its Current Practice To meet user s quality requirements. Testing aims at the
More informationIntroduction to CMOS VLSI Design Lecture 13: SRAM
Introduction to CMOS VLSI Design Lecture 13: SRAM David Harris Harvey Mudd College Spring 2004 1 Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access
More informationChapter 5. Internal Memory. Yonsei University
Chapter 5 Internal Memory Contents Main Memory Error Correction Advanced DRAM Organization 5-2 Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory(ram) Read-write
More informationBuilt-In Self-Test for Regular Structure Embedded Cores in System-on-Chip
Built-In Self-Test for Regular Structure Embedded Cores in System-on-Chip Srinivas Murthy Garimella Master s Thesis Defense Thesis Advisor: Dr. Charles E. Stroud Committee Members: Dr. Victor P. Nelson
More informationY. Tsiatouhas. VLSI Systems and Computer Architecture Lab. Embedded Core Testing (ΙΕΕΕ SECT std) 2
CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES University of Ioannina Embedded Testing (ΙΕΕΕ 1500 Std. SECT) Dept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit Design Techniques
More informationECE 341. Lecture # 16
ECE 341 Lecture # 16 Instructor: Zeshan Chishti zeshan@ece.pdx.edu November 24, 2014 Portland State University Lecture Topics The Memory System Basic Concepts Semiconductor RAM Memories Organization of
More informationJin-Fu Li. Department of Electrical Engineering. Jhongli, Taiwan
Chapter 9 Basics of SOC Testing Jin-Fu Li Advanced Reliable Systems (ARES) Lab Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Introduction SOC Test Challenge SOC
More informationMagnetic core memory (1951) cm 2 ( bit)
Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM
More informationInfineon HYB39S128160CT M SDRAM Circuit Analysis
September 8, 2004 Infineon HYB39S128160CT-7.5 128M SDRAM Circuit Analysis Table of Contents Introduction... Page 1 List of Figures... Page 2 Device Summary Sheet... Page 13 Chip Description... Page 16
More informationDigital Integrated Circuits Lecture 13: SRAM
Digital Integrated Circuits Lecture 13: SRAM Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec13 cwliu@twins.ee.nctu.edu.tw 1 Outline Memory Arrays
More informationAn Efficient Parallel Transparent Diagnostic BIST
An Efficient Parallel Transparent Diagnostic BIST D. C. Huang and W. B. Jone Department of CS & IE, National Chung-Cheng University, Taiwan, R.O.C. Abstract- In this paper, we propose a new transparent
More informationModeling And Simulation Of Microcode Based Asynchronous Memory Built In Self Test For Fault Detection Using Verilog
Modeling And Simulation Of Microcode Based Asynchronous Memory Built In Self Test For Fault Detection Using Verilog Amruta P. Auradkar # and Dr. R. B. Shettar * # M.Tech.,2 nd year, Digital Electronics,
More informationOutline of Presentation
Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs Sudheer Vemula and Charles Stroud Electrical and Computer Engineering Auburn University presented at 2006 IEEE Southeastern Symp. On System
More information