UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO.

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1 Filed on behalf of SanDisk Corporation By: Lori A. Gordon Robert E. Sokohl Sterne, Kessler, Goldstein & Fox PLLC 1100 New York Avenue, NW Washington, D.C. Tel: (202) Fax: (202) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 8,081,536

2 Table of Contents I. Mandatory Notice (37 C.F.R. 42.8(a)(1))... 1 II. Grounds for Standing (37 C.F.R (a))... 2 III. Identification of Challenge (37 C.F.R (b))... 2 A. Statutory Grounds for the Challenge... 2 B. Citation of Prior Art... 2 IV. The '536 Patent... 4 A. Overview... 4 B. Level of Ordinary Skill in the Art... 8 C. Challenged Claims The challenged claims include substantially overlapping claim limitations Claim Construction V. Grounds of Rejection A. Ground 1: Claims 1 and 24 of the 536 Patent are Obvious over Takeda and Karabatsos Overview of Takeda and Karabatsos Prosecution History Related to Takeda The combination of Takeda and Karabatsos renders independent claims 1 and 24 Obvious B. Ground 2: The Combination of Takeda, Karabatsos, and JEDEC Renders Claims 16, 17, 30, and 31 Obvious The combination of Takeda, Karabatsos, and JEDEC renders dependent claims 16 and 30 obvious Takeda, Karabatsos, and JEDEC render Dependent Claims 17 and 31 obvious C. Ground 3: The Combination of Takeda, JEDEC and Connolly Renders Claims 1, 16, 17, 24, 30, and 31 Obvious Overview of Takeda, JEDEC, and Connolly The combination of Takeda, JEDEC, and Connolly renders independent claims 1 and 24 obvious i -

3 3. The combination of Takeda, JEDEC, and Connolly renders claims 16 and 30 obvious The combination of Takeda, JEDEC, and Connolly renders claims 17 and 31 obvious D. Ground 4: The Combination of Amidi and Connolly Renders Claims 1, 16, 17, 24, 30, and 31 Obvious Overview of Amidi and Connolly The combination of Amidi and Connolly renders independent claims 1 and 24 obvious The combination of Amidi and Connolly renders dependent claims 16 and 30 obvious The combination of Amidi and Connolly renders dependent claims 17 and 31 obvious VI. Conclusion ii -

4 EXHIBIT LIST SanDisk Exh. No. Description 1001 U.S. Patent No. 8,081,536 to Solomon, et al., issued December 20, 2011 ( 536 Patent ) 1002 Declaration of Dr. Srinivasan Jagannathan ( Jagannathan Dec. ) 1003 Japanese Patent Application Publication No. H to Takeda, published December 4, 1998 ( Takeda ) 1004 Certified English-language translation of Japanese Patent Application Publication No. H to Takeda, published December 4, 1998 ( Takeda Trans. ) 1005 U.S. Patent No. 6,446,158 to Karabatsos, issued September 3, 2002 ( Karabatsos ) 1006 JEDEC Standard 21-C: PC2100 and PC1600 DDR SDRAM Registered DIMM Design Specification, Revision 1.3, January 2002 ( JEDEC21C ) 1007 U.S. Patent No. 6,070,217 to Connolly, et al., issued May 30, 2000 ( Connolly ) 1008 U.S. Patent Application Publication No. 2006/ to Amidi, et al., published June 1, 2006 ( Amidi ) 1009 Excerpts of prosecution history of Application Serial No. 13/032,470, which issued as U.S. Patent No. 8,081,536 ( 536 File History ) 1010 Detailed Request for Inter Partes Reexamination of Patent No. 8,250,295 B2, Netlist, Inc. v. Smart Modular Technologies, Control No. 95/002,399, filed September 15, 2012 ( Request ) 1011 Patent Owner s Preliminary Response (Paper No. 9), Diablo Technologies, Inc. v. NetList, Inc., IPR , filed October 7, 2014 ( IPR POPR ) - iii -

5 1012 Action Closing Prosecution, mailed March 21, 2014, Inter Partes Reexamination Control No. 95/000,578 ( the 912 ACP ) 1013 Action Closing Prosecution, mailed March 12, 2012, Inter Partes Reexamination Control No. 95/001,337, ( the 274 ACP ) 1014 ALTERA ACEX 1K Programmable Logic Device Family Datasheet, ver. 3.4, May 2003, accessed at [ archives/acex.pdf] ( ALTERA ) 1015 JESD79C: Double Data Rate (DDR) SDRAM Specification, March 2003 [accessed at ( JEDEC79C ) 1016 JESD21-C: JEDEC Configurations for Solid State Memories section 4.5.7, 168 Pin Registered SDRAM DIMM Family, October 2001 [accessed at ( JEDEC21C ) 1017 JESD21-C: JEDEC Configurations for Solid State Memories section 4.6.1, 278 Pin Buffered SDRAM DIMM Family, June 1997 [accessed at ( JEDEC21C ) 1018 JESD21-C: JEDEC Configurations for Solid State Memories section , Appendix E: Specific PD s for Synchronous DRAM (SDRAM), May 2003 [accessed at docs/4_01_02_05r12.pdf] ( JEDEC21C ) 1019 MT16VDDT3264A, MT16VDDT6464A DDR SDRAM DIMM Module Data Sheet [accessed at cd012/ pdf] ( Micron ) 1020 Synchronous DRAM Architectures, Organizations, and Alternative Technologies, Prof. Bruce L. Jacob, December 10, 2002 [accessed at Systems.pdf] ( Jacob ) - iv -

6 1021 Logic Design Principles with Emphasis on Testable Semicustom Circuits, Edward J. McCluskey, 1986, Prentice Hall, Englewood Cliffs, NJ ( McCluskey ) 1022 Decision on Institution of Inter Partes Review of U.S. Patent 7,881,150 B2 (Paper No. 11), Diablo Technologies, Inc. v. Netlist, Inc., IPR , mailed December 16, 2014 ( the 150 Diablo IPR11 ) 1023 Decision on Institution of Inter Partes Review of U.S. Patent 7,881,150 B2 (Paper No. 12), Diablo Technologies, Inc. v. Netlist, Inc., IPR , mailed December 16, 2014 ( the 150 Diablo IPR12 ) 1024 Decision on Institution of Inter Partes Review of U.S. Patent 8,081,536 B1 (Paper No. 11), Diablo Technologies, Inc. v. Netlist, Inc., IPR , mailed December 16, 2014 ( the 536 Diablo IPR ) 1025 Opening Claim Construction Brief, Netlist Inc., vs. Google, Inc., Case No. 4:08-CV (N.D. Cal., July 28, 2009) ( 2009 NetList Claim Construction Brief ) 1026 Curriculum Vitae of Dr. Srinivasan Jagannathan ( Jagannathan CV ) 1027 Excerpts from file history of Inter Partes Reexamination Control No. 95/001,337 (Action Closing Prosecution mailed March 12, 2012 [ the 337 ACP ]; Decision On Appeal mailed January 16, 2014 [ the 337 DOA ]) - v -

7 SanDisk Corporation requests that the United States Patent Office institute an inter partes review of claims 1, 16, 17, 24, 30, and 31 (collectively, the challenged claims ) of United States Patent No. 8,081,536 to Solomon et al. ( the 536 patent ). According to Office records, the ʼ536 patent is assigned to Netlist, Inc. A copy of the 536 patent is provided as SanDisk I. Mandatory Notice (37 C.F.R. 42.8(a)(1)) REAL PARTY IN INTEREST: The real party-in-interest of Petitioner is SanDisk Corporation. RELATED MATTERS: U.S. Patent No. 8,081,536 is involved in the following current proceedings that may affect or be affected by a decision in this proceeding: NetList, Inc. v. Smart Storage Systems, Inc., Diablo Technologies, Inc., and SanDisk Corporation, 4:13-cv YGR, NDCA. Diablo Technologies, Inc. v. Netlist, Inc., IPR LEAD AND BACKUP COUNSEL: Pursuant to 37 C.F.R. 42.8(b)(3) and 42.10(a), Petitioner appoints Lori A. Gordon (Reg. No. 50,633) as its lead counsel, Robert E. Sokohl (Reg. No. 36,013) as its back-up counsel, both at the address: STERNE, KESSLER, GOLDSTEIN & FOX, 1100 New York Avenue, N.W., Washington, D.C., 20005, phone number (202) and facsimile (202)

8 SERVICE INFORMATION: Petitioner consents to electronic service by at the addresses: and II. Grounds for Standing (37 C.F.R (a)) The undersigned and SanDisk certify that the ʼ536 patent is available for inter partes review. SanDisk certifies that it is not barred or estopped from requesting this inter partes review on the grounds identified herein III. Identification of Challenge (37 C.F.R (b)) A. Statutory Grounds for the Challenge Petitioner requests review of claims 1, 16, 17, 24, 30 and 31on four grounds: GROUND 1: Takeda in view of Karabatsos renders claims 1 and 24 unpatentable under 35 U.S.C. 103(a). GROUND 2: Takeda in view of Karabatsos and further in view of JEDEC renders claims 16, 17, 30 and 31 unpatentable under 35 U.S.C. 103(a). GROUND 3: Takeda in view of JEDEC and further in view of Connolly renders claims 1, 16, 17, 24, 30 and 31 unpatentable under 35 U.S.C. 103(a). GROUND 4: Amidi in view of Connolly renders claims 1, 16, 17, 24, 30, and 31 unpatentable under 35 U.S.C. 103(a). B. Citation of Prior Art In support of the grounds of unpatentability cited above, Petitioner cites the following prior art references: Japanese Patent Publication No. H to Takeda, provided as SanDisk 1003, qualifies as prior art under at least 35 U.S.C. 102(b) because it - 2 -

9 published on December 4, 1998, more than one year prior to the earliest possible priority date of the '536 patent. 1 A certified English translation Takeda Trans is provided as SanDisk Citations in this Petition are made to the certified translation. U.S. Patent No. 6,446,158 to Karabatsos, provided as SanDisk 1005, qualifies as prior art under at least 35 U.S.C. 102(b) because it issued on September 3, 2002, more than one year prior to the earliest possible priority date of the '536 patent. JEDEC Standard 21-C: DDR SDRAM Registered DIMM Design Specification, provided as SanDisk 1006, qualifies as prior art under at least 35 U.S.C. 102(b) because it published in January of 2002, more than one year prior to the earliest possible priority date of the '536 patent. U.S. Patent No. 6,070,217 to Connolly et al., provided as SanDisk 1007, qualifies as prior art under at least 35 U.S.C. 102(b) because it issued on May 30, 1 The '536 patent is the member of a large family and claims as its earliest benefit, U.S. Provisional Application No. 60/550,668, filed on March 5, 2004 ("the '668 Provisional Application). Petitioner does not believe that the claims of the '536 patent are entitled to benefit of the '668 Provisional Application. However, each of the applied references was published or filed prior to the March 5, 2004 date. Therefore, Petitioner does not address the priority claim in the Petition

10 2000, more than one year prior to the earliest possible priority date of the '536 patent. U.S. Patent Publication No. 2006/ to Amidi, provided as SanDisk 1008, qualifies as prior art under at least 35 U.S.C. 102(e) because it was filed on January 5, 2004, prior to the earliest possible priority date of the '536 patent. IV. The '536 Patent A. Overview The 536 patent "relates generally to memory modules of a computer system, and more specifically to devices and method for improving the performance, the memory capacity, or both, of memory modules." ( 536 patent, 1:35 38.) FIG. 1 of the '536 patent (reproduced below) illustrates an exemplary memory module 10 having a plurality of memory devices 30 (arranged in ranks 32) and a circuit 40. (Id., 5:25-34.) Circuit 40 is coupled to the memory devices 30 and also to a memory controller 20 of a computer system. (Id. at 5:25-34) - 4 -

11 FIG. 1 from 536 patent In embodiments, two memory devices having a memory density are used to simulate a single memory device having twice the memory density. ( 536 patent, 21:63-65.) For example, "computer systems which are normally limited to using memory modules which have a single rank of 128Mx4-bit memory devices" can use "memory modules which have double the memory (e.g., two ranks of 128Mx4bit memory devices). ( 536 patent, 22:17-18.) In a further example, two 512-M memory devices, each with a 128Mx4-bit configuration can be used to simulate a 1-Gb memory device having a 128Mx8-bit configuration. ('536 patent, 20:45-47.) The memory module of the '536 patent typically includes a serial-presence detect (SPD) device comprising data that characterizes various attributes of the - 5 -

12 memory module. ( 536 patent, 18:55-60.) The SPD communicates this data to the BIOS of the computer system so that the computer system is informed of the memory capacity and the memory configuration available for use and can configure the memory controller properly. ( 536 patent, 18:55-19:2.) In the simulation embodiments of the '536 patent, the data stored in the SPD device does not describe the actual-lower-density memory devices but instead describes the virtual or pseudo-higher density memory devices. ( 536 patent, 20:58-60.) FIG. 9A (reproduced below) illustrates memory module 210 in more detail. As shown in FIG. 9A, circuit 40 receives a set of input command signals and address signals (An+1) including bank address signals (BA0-BAm), gated column address strobe signals, and chip-select signals (CS0, CS1) from memory controller 20 of the computer system. (Id., 16:36 44; 17:19 26.) Based on the received input signals from memory controller 20, circuit 40 generates output signals corresponding to the larger number of memory devices on the memory module. (Id., 16:36-52) For example, the output signals include a different number of chip select signals than received from the memory controller, reflecting the larger number of memory devices 30 in ranks 32. (Id., 17:4-12; 17:34-51.) As shown in Figure 9A, circuit 40 is included on a memory module 10 along with a register 230 and a phase-lock loop device (PLL) 220. (Id. at 15:52 58; Fig. 9A.) - 6 -

13 FIG. 9A from 536 patent With the output address and command signals, circuit 40 isolates the electrical loads of some of memory devices 30 from the computer system. (Id., 7:17-31.) According to the 536 patent, load isolation may result in specific benefits including reduced capacitive load related to data signal lines. (Id., 7:27-31.) As shown in Fig. 3A (reproduced below), circuit 40 isolates the load of a memory device by isolating one or both of DQ data signal lines 102a, 102b of two memory devices 30a and 30b from common DQ data signal line 112 that is coupled to the computer system using simple switches. (Id., 7:32-38, Fig. 3A.) - 7 -

14 B. Level of Ordinary Skill in the Art One of ordinary skill in the art related to the 536 patent would understand basic memory and data communication concepts, with a bachelor s degree in any of electrical engineering, computer engineering, computer science, or related field. Course work for one of ordinary skilll in the artt would have included a course on computer organization, principles of digital design, or computer architecture. One of ordinary skill in the art would also have around one yearr of experience related to computer memory systems. For example, such experiencee may include experience in DRAM memory technology and related industry standards such as JEDEC standards for DRAM memories and memory modules. C. Challenged Claims 1. The challenged claims limitations. include substantially overlapping claim Independent claim 1 directed to a "circuit to be mounted on a memory module" and independent claim 24 directed to a "method of operating a memory module" contain substantiall ly identical claim limitations. The following claim - 8 -

15 chart highlights the similarities with bold indicating the differences between the claims. Because the claims are substantially identical, Petitioner addresses them together. [A] Claim 1 Claim 24 A circuit configured to be A method of operating a [B] mounted on a memory module configured to be operationally coupled to a computer system, the memory module having a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another for receiving and transmitting data having a bit width of the rank in response at least in part to a first number of DDR chip-select signals, the circuit including at least one memory module configured to be operationally coupled to a computer system, the memory module having a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another for receiving and transmitting data having a bit width of the rank in response at least in part to a first number of DDR chip-select signals, the method comprising: - 9 -

16 [C] [D] [E] configuration in which the circuit is configured to: receive a set of signals comprising address signals and a second number of DDR chip-select signals smaller than the first number of DDR chip-select signals; generate phase-locked clock signals and transmit the phaselocked clock signals to the DDR memory circuits of the first number of ranks; selectively isolate a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals; and receiving a set of signals comprising address signals and a second number of DDR chip-select signals smaller than the first number of DDR chip-select signals; using the memory module to generate phase-locked clock signals and transmitting the phase-locked clock signals to the DDR memory circuits of the first number of ranks; selectively isolating a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals; and [F] generate the first number of generating the first number of

17 DDR chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of DDR chip-select signals. DDR chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of DDR chip-select signals. Challenged dependent claims 16 and 17 are substantially identical to challenged dependent claims 30 and 31. Therefore, Petitioner also address these claims together. 2. Claim Construction Except for the term set forth below, construed under the broadest reasonable interpretation standard, the terms are to be given their plain and ordinary meaning as understood by one of ordinary skill in the art and consistent with the disclosure. Petitioner reserves the right to present different constructions in the District Court where a different claim construction standard applies. Rank A rank is a broad term of the art related to a group of memory devices on a memory module. (Jagannathan Dec. 2, 44.) Specifically in the context of the 536 patent, a rank is a block or area that is created using some or all of the memory chips on a memory module. (Jagannathan Dec., 18) This construction is also 2 Jagannathan Declaration is provided as SanDisk

18 consistent with the specification of the 536 patent which states: [t]he DRAM devices of a memory module are generally arranged as ranks or rows of memory... ( 536 patent, 2:29-30.) The figures of the 536 patent also consistently illustrate a rank of devices as comprising memory chips on a memory module ( 536 patent, FIGs. 4A, 4B, 5C, 5D, 8A, 8B, 8C, 8D, 9A, 9B, 10A, 11A). V. Grounds of Rejection A. Ground 1: Claims 1 and 24 of the 536 Patent are Obvious over Takeda and Karabatsos. 1. Overview of Takeda and Karabatsos Takeda discloses a memory module having more ranks than are expected by the computer system to which it is connected. (Takeda Trans., [0004]) (Jagannathan Dec., 54.) The computer system indicates the number of ranks that it expects to find on a memory module by providing a fixed number of fully decoded chip select signals to the memory module. (Jagannathan Dec., ) Thus, the memory module of Takeda simulates to the computer system a memory module having the expected configuration. Since Takeda s memory module has more ranks than the computer expects, the circuitry on the memory module generates the required extra chip selects to operate the additional ranks. (Takeda Trans., [0012]-[0013]) (Jagannathan Dec., ) Takeda's rank simulation is identical to the simulation described in the 536 patent. ( 536 patent, 16:57-66.) (Jagannathan Dec., 60.)

19 FIG. 1 of Takeda (reproduced below with annotations) identifies the ranks of SDRAM chips along with their associated chip select signals. Annotated FIG. 1 from Takeda (Jagannathan Dec., p. 37.) In Takeda, a memory module has a bank control unit for converting drive signals from outside the module, which are sent in order to control the plurality of banks, to signals for controlling the plurality of banks. (Takeda Trans., [0005].) Each of the banks is composed of a plurality of multibit DRAMs. (Takeda Trans.,

20 [0011].) An illustration of the bank control unit is shown in FIG. 2 of Takeda (reproduced below with annotations). Annotated FIG. 2 of Takeda (Jagannathan Dec., p. 39.) A person having ordinary skill in the art (PHOSITA) would understand that the context in which the term bank is used makes it clear when the term refers to ranks of memory devices and when the term refers to banks of memory arrays inside a single memory device. (Jagannathan Dec., 55.) For example, a bank of memory devices refers to rank in a memory module, whereas a bank of memory arrays inside an SDRAM refers to an arrangement inside the memory device. (Jagannathan Dec., 55.) Takeda refers throughout to a bank of memory devices and therefore the banks of Takeda are ranks. (Jagannathan Dec., ) As shown in FIG. 2 above, the signals on the left side of the bank control unit (shown in FIG. 2 of Takeda) are received from outside the module while the signals on the right are generated to control the plurality of banks on the memory

21 module. (Takeda Trans., [0005]) (Jagannathan Dec., 59.)) A PHOSITA would appreciate that the bank control circuitry would be includedd on the memory module. (Jagannathan Dec., 59, 61.) The signalss received from outside the memory module include 2 chip select signals (/S0 and /S2) along with address signals (A12 and A13.) (Takeda Trans., [0012]) (Jagannathan Dec., 59.) The logic circuitry then uses at least these signals to select a bank via chip select signals /CS0 - /CS7. (Takeda Trans., [0012].) (Jagannathan Dec., ) FIG. 3 of Takeda (reproduced below) provides a timing diagram of the various signals received and generated by the logic circuit of FIG. 2. FIG. 3 from Takeda Each signal transition shown in Fig. 3 is aligned with a corresponding transition of a clock (CLK) signal that controls the timing of the circuit. (Jagannathan Dec., 62.) This clock signal is also received by each SDRAM chip

22 to control the timing of the read/write operations of the SDRAM chips (as shown in FIG. 1). (Jagannathan Dec., 62, 66.) Although Takeda discloses the use of a clock signal in the memory circuit, Takeda does not explicitly disclose that the clock signal is a phase-locked clock signal[] as recited in independent claims 1 and 24. But phase-locked clock signals were commonly implemented on memory modules before the critical date of the 536 patent, as evidenced by Karabatsos. Karabatsos also discloses a memory module architecture using a plurality of SDRAM chips. (Karabatsos, 5:39-47) (Jagannathan Dec., 91, 93.) To provide the synchronous control of the memory chips, Karabatsos discloses a phase-locked loop: [f]or high-speed operation, one method of generating the delayed clock signal is the use of a clock driver or Phase Locked Loop (PLL) with multiple outputs of the same phase in order to drive several SDRAM chips with small capacitive loading. (Karabatsos, 9:10-14.) The PLL receives the clock signal from the memory bus and generates a phase-locked clock signal for use with the SDRAM memory. (Jagannathan Dec., 94.) It would have been obvious to a PHOSITA at the time of the alleged invention in the 536 patent to use the phase-locked clock signals of Karabatsos to control the timing of the elements of the memory module in Takeda. (Jagannathan Dec., 105, 107.) Karabatsos teaches using a Phase Locked Loop (PLL) with multiple outputs of the same phase in order to drive several SDRAM chips with

23 small capacitive loading. (Karabatsos, 9:11-14 (emphasis added).) A PHOSITA would recognize that a benefit of reduced capacitive loading is a reduced power consumption. (Jagannathan Dec., 107.) As such, a PHOSITA would have been motivated to apply the known technique of phase-lock clock signals of Karabatsos to the known memory circuit of Takeda to yield the predictable result of driving the SDRAM chips with small capacitive loading. (Jagannathan Dec., 107.) Takeda also discloses that the unselected memory banks reduce the overall power consumption: the banks are active one at a time, so in other words the active SDRAMs constitute 1/4 of the total number of SDRAMs in the memory module. Power consumption for the inactive SDRAMs is close to the power consumed during standby and is very low compared with the power consumed during operation. (Takeda Trans., [0015].) However, Takeda does not explicitly disclose selectively isolat[ing] a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system. But performing selective isolation of the memory circuits was well known as also evidenced by Karabatsos. (Jagannathan Dec., 95.) Karabatsos discloses the use of FET switches to selectively isolate the data outputs of various memory chips: [t]he output 106 of memory chip A is connected to the input of FET switch A The output of memory chip B is similarly switched by FET switch B 113. (Karabatsos, 5:56-60; FIG. 3(a).) As such, the

24 deselected memory chip is electrically isolated from the computer system: [w]hen a FET switch is enabled, the data path through the switch presents vey negligible delay to the signal. When the switch is disabled, the data path is high impedance and no signal can travel through it. (Karabatsos, 5:64-67; emphasis added.) (Jagannathan Dec., 95, 106.) This high impedance state isolates the capacitive load of unselected memory chips from the memory bus. (Jagannathan Dec., 95.) It would have been obvious to a PHOSITA at the time of the alleged invention to use the memory chip isolation technique of Karabatsos with the SDRAM memory chips of Takeda. A PHOSITA would recognize that isolating the loads of the unselected memory ranks would result in a reduced power consumption. (Jagannathan Dec., 42, 106.) As such, a PHOSITA would have been motivated to apply Karabatos' known technique of isolating unselected data outputs of different memory circuits to the known memory circuits of Takeda to yield the predictable result of switching to isolate unselected memory chip outputs. (Jagannathan Dec., 106.) 2. Prosecution History Related to Takeda During prosecution of U.S. Appl. No. 13/032,470, which issued as the 536 patent, the Examiner found the Takeda reference and scheduled an interview to discuss the reference. Takeda was never applied in a rejection by the Examiner. The Examiner made the Takeda reference of record by entering into the record the

25 original Japanese patent (JP ), the English abstract for JP , and an English machine translation of JP provided by the Japanese Patent Office. ( 536 file history excerpts, p. 18.) Based on these documents, and representations made during the interview, the Examiner concluded that Takeda does not teach receive a second number of DDR chip-select signals smaller than the first number of DDR chip-select signals... (Interview Summary, 3 p. 11 of SanDisk 1009) As discussed herein, the Examiner s conclusion regarding Takeda is technically incorrect. And, Patent Owner also now acknowledges that Takeda discloses this limitation. Less than one year later after the Interview, the Patent Owner relied upon Takeda in an inter partes reexamination 4. As part of the Request, the Patent Owner provided their own translation of Takeda. (Request, p. 16) Armed with this new translation, Patent Owner described Takeda as teaching that a set of first chip 3 The other features listed by the Examiner in the interview summary as not being taught be Takeda are addressed herein by Takeda s combination with Karabatsos, and combination with JEDEC and Connolly. 4 Inter partes reexamination of U.S. Patent No. 8,250,295 (Control number 95/002,399; request filed by Netlist on September 15, 2012, Request, and provided as SanDisk 1010.)

26 select signals S0 and S1, which correspond to a smaller number of ranks (e.g., two ranks), are combined with a portion of the address signal, A12 and A13, to generate a set of second chip select signals CS0 CS7 (at the right of the figure) to selectively activate a larger number of ranks (e.g., eight ranks). (Request, pp. 5-6.) Patent Owner went on to state that Takeda's express disclosure of SDRAM devices points to DDR SDRAM devices and conventional memory modules using DDR SDRAM devices. (Request, p. 6.) Thus, after considering a more thorough translation of Takeda as compared to a machine translation, Patent Owner agrees that Takeda discloses many of the features found in claims 1 and 24, such as those relating to the first number of DDR chip-select signals address signals and second number of DDR chip-select signals smaller than the first number of DDR chip-select signals. 3. The combination of Takeda and Karabatsos renders independent claims 1 and 24 Obvious a) Takeda discloses the preambles of independent claims 1 and 24 [1A, 24A]. Takeda discloses "a memory module configured to be operationally coupled to a computer system" and a "method of operating" such a memory module: In Takeda, the circuit convert[s] drive signals from outside the module, which are sent in order to control the plurality of banks, to signals for controlling the plurality of banks. (Takeda Trans., [0005].) Although Takeda does not specify the

27 originator of the outside drive signals, it would be obvious to a PHOSITA that a computer system generates these drive signals. (Jagannathan Dec., 59, 61.) Memory modules are designed to receive input signals from a memory controller (i.e., a computer component). (Jagannathan Dec., 61.) Further, a PHOSITA would appreciate that it would be obvious that such a circuit is mounted on the memory module given that it receives signals from outside the module and converts them to signals that control the memory banks (which are also coupled to the memory module) (Jagannathan Dec., 61.) b) Takeda discloses the memory module configuration limitations ([1B], [24B]). Takeda discloses a "memory module having a first number of ranks, each rank of the first number of ranks comprising memory circuits": As illustrated in FIG. 1 (reproduced below with annotations), Takeda's memory module includes a plurality of banks comprising a plurality of current-generation SDRAMs... (Takeda Trans., [0005].) As discussed above, the banks disclosed in Takeda are the same as the claimed ranks. (Jagannathan Dec., )

28 Annotated FIG. 1 from Takeda (Jagannathan Dec., p. 37.) Although Takeda describes the use of SDRAM circuits, a PHOSITA would readily understand that the teachings of Takeda could be applied to any synchronous memory architecture, which includes a "DDR memory circuit." (Jagannathan Dec., ) In fact, Takeda explicitly discloses that JEDEC documents are used to describe memory module configurations. (Takeda Trans., [0002]). Thus, a PHOSITA would understand that Takeda s teachings may be

29 applied to JEDEC compliant devices, such as a DDR SDRAM. (Jagannathan Dec., 65.) The memory circuits of Takeda "are configured to be activated concurrently with one another for receiving and transmitting data having a bit width of the rank in response at least in part to a first number of [] chip select signals." Takeda discloses the use of 4 banks (ranks): D0 D15; D16 D31; D32 D47; and D48 D63 with each bank (rank) selected using pairs of chip select signals selected from CS0 CS7 (a first number of chip select signals). (Takeda Trans., [0011] [0013].) (Jagannathan Dec., ) Each SDRAM of a selected bank would operate concurrently to output data on the data buses DQ0 DQ63 (defining the bit width of the selected bank.) (Jagannathan Dec., ) As noted above, it would be obvious to a PHOSITA that the teachings in Takeda regarding the activation of different ranks of memory could be applied to either SDRAM or DDR SDRAM. (Jagannathan Dec., 65.) Thus, it would be obvious to a PHOSITA that the DDR memory circuits "are configured to be activated concurrently with one another in response at least in part to a first number of DDR chip select signals." c) Takeda discloses the receive limitation (1[C],24[C]). The circuit of Takeda "receiv[es] a set of signals comprising address signals" and a "second number of [] chip select signals": As shown in annotated FIG

30 below, the memory module circuit of Takeda receives address signals and a second number of chip-select signals. And, as discussed above, it would be obvious to a PHOSITA to use a DDR memory circuit in Takeda. Therefore, the received "chipselect signals" are "DDR chip-select signals." Annotated FIG. 2 from Takeda (Jagannathan Dec., p. 39.). In Takeda, the memory module circuit receives fewer chip-select signals than it generates. This is highlighted in annotated FIG. 2 showing two received chip-select signals whereas 8 chip-select signals are generated for transmission to the memory devices. Thus, Takeda discloses that "the second number of DDR chip-select signals [is] smaller than the first number of DDR chip-select signals." d) The combination of Takeda and Karabatsos discloses the phase-locked clock signal generation and transmission limitation. (1[D], 24[D]). Takeda discloses that the generation and transmission of a clock signal to the memory circuits of the first number of ranks: As shown in FIG. 1 of Takeda, a

31 clock (CLK) signal being received by each SDRAM memory chip receives a clock signal. (Jagannathan Dec., 66.) However, Takeda does not explicitly disclose that this clock signal is a phase-locked clock signal. However, Karabatsos discloses using a phase-locked clock signal to drive the timing on SDRAM chips: [f]or high-speed operation, one method of generating the delayed clock signal is the use of a clock driver or Phase Locked Loop (PLL) with multiple outputs of the same phase in order to drive several SDRAM chips with small capacitive loading. (Karabatsos, 9:10-14.) Thus, in Karabatsos, the PLL receives the clock from the memory controller and generates a phase-locked clock signal for use with the SDRAM memory. (Jagannathan Dec., 94.) It would have been obvious to incorporate the phase-locked clock signal of Karabatsos with the SDRAM memory module of Takeda, as already discussed above. (Jagannathan Dec., 107.) e) The combination of Takeda and Karabatsos discloses the selectively isolating limitation (1[E], 24[E]). Takeda does not explicitly disclose "selectively isolating a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals." However, Karabatsos discloses this limitation. In Karabatsos, FET switches are used to control which memory chips use a shared data bus: [t]he output 106 of memory chip A is connected to the input of FET switch A The output of memory chip B is

32 similarly switched by FET switch B 113. (Karabatsos, 5:56-60; FIG. 3(a).) As such, the deselected memory chip is electrically isolated from the computer system: [w]hen a FET switch is enabled, the data path through the switch presents vey negligible delay to the signal. When the switch is disabled, the data path is high impedance and no signal can travel through it. (Karabatsos, 5:64-67; emphasis added.) (Jagannathan Dec., 95.) In Takeda, the shared data bus line (DQ0-3) connects to memory chips D0, D16, D32, and D48, with each memory chip in a different bank. Since each chip shares the same data bus, each chip may be isolated from one another using the FET switches taught by Karabatsos. (Jagannathan Dec., 95,106.) When this is performed for each row of chips in Takeda, an entire bank of chips is isolated. (Jagannathan Dec., 95,106.) The isolation operation of Karabatsos is performed in response at least in part to the set of signals. Karabatsos discloses that the FET switches are controlled via separate enable signals. (Karabatsos, 5:58-60.) As discussed above in the received signal limitation section, Takeda uses the received set of signals (e.g., address signals and chip-select signals) to generate the internal chip select signals (first number of chip-select signals). It would be obvious to a PHOSITA that the FET enable signals are activated relative to which chip select signals CS

33 CS7 are activated so that the selected memory bank is not inadvertently isolated from the computer. (Jagannathan Dec., 106.) f) The combination of Takeda and Karabatsos discloses the first number of chip-select signal generation limitation (1[F],24[F]). The memory module circuit of Takeda "generat[es] the first number of [DDR] chip-select signals in response to at least in part the address signals, and the second number of DDR chip-select signals." As shown in FIG. 2 from Takeda, the logic circuitry generates the first number of chip-select signals at least in part based on the address signals (A12 and A13) and the second number of chip-select signals (S0 and S2). (Jagannathan Dec., ) As discussed above, when DDR memory circuits are substituted for the SDRAM memory circuits of Takeda, the chip-select signals are "DDR chip-select signals." Takeda does not explicitly disclose that the generation of the first number of chip-select signals is in response in part to "the phase-locked clock signals." However, the timing diagram of Takeda shown in FIG. 3 illustrates how each of the signal transitions is influenced by the clock signal (CLK). (Jagannathan Dec., 62.) It would be obvious to a PHOSITA that the clock signal could be improved to be a phase-locked clock signal as shown in Karabatsos, as discussed above. Therefore, the combination of Takeda and Karabatsos discloses that the generation of the first number of chip-select signals can additionally be in response to the phase-locked clock signals of Karabatsos. (Jagannathan Dec., 107.)

34 B. Ground 2: The Combination of Takeda, Karabatsos, and JEDEC Renders Claims 16, 17, 30, and 31 Obvious. The combination of Takeda and Karabatsos discloses each and every limitation of independent claims 1 and 24. However, the combination of Takeda and Karabatsos does not disclose that the "memory module has attributes" or that "data characterize[ing] the memory as having attributes that are different from the attributes of the memory module" are stored. However, these limitations would be obvious in view of JEDEC, as described below. 1. The combination of Takeda, Karabatsos, and JEDEC renders dependent claims 16 and 30 obvious. JEDEC specifies "attributes" for a "memory module." In the similar field of SDRAM module design, JEDEC is a product datasheet designed to inform a user about all the various input signals, output signals, and operating conditions of a DDR SDRAM module as it existed in (JEDEC, p. 5) A PHOSITA would have understood that the configuration of a DDR SDRAM architecture as described in JEDEC is compatible with the SDRAM configuration disclosed in Takeda. (Jagannathan Dec., 64-65, 109.) Both architectures use similarly connected ranks of synchronous DRAM chips. (JEDEC, p. 13; Takeda, FIG. 1) (Jagannathan Dec., 64.) Furthermore, Takeda explicitly discloses that JEDEC documents are used to describe memory module configurations. (Takeda Trans., [0002])

35 JEDEC teaches a serial presence detect (SPD) element on the memory module configured to "store data accessible to the computer system." (JEDEC, p. 13). JEDEC's SPD element is the same as the SPD device that the 536 patent describes as a typical component of a memory module. ( 536 patent, 18:56-60.) ( Memory modules typically include a serial-presence detect (SPD) device comprising data which characterize various attributes of the memory module. (See also, Jagannathan Dec., ) The data stored in the SPD of the memory module of Takeda, Karabatsos, and JEDEC combined "characterizes the memory module as having attributes that are different from the attributes of the memory module." As described above, Takeda discloses a bank control unit that emulates a two rank memory module to the computer system whereas the actual memory module has four ranks. (Takeda Trans., [0005], [0008], [0016]) (Jagannathan Dec., 54, 110.) It would have been obvious to a PHOSITA that information at least related to the emulated number of ranks must be stored in the SPD so that the memory controller interfaces with the emulated memory organization of the memory module. (Jagannathan Dec., 110.) Therefore, the information stored in the SPD would characterize the memory module with having different attributes (e.g., two ranks) than the actual attributes of the memory module (e.g., four ranks). (Jagannathan Dec., 54, 110.)

36 A PHOSITA would have been motivated to combine the disclosure of the SPD device in JEDEC with the memory module architecture of Takeda. Takeda explicitly discloses that the standards for memory module design are found in JEDEC documents. (Takeda Trans., [0002].) JEDEC provides further implementation details about an SDRAM module on which Takeda s bank control unit would be utilized. (Jagannathan Dec., 109.) Furthermore, the SPD element is commonly used on memory modules so that the memory controller is correctly configured to interface with the memory, as noted by the 536 patent. ( 536 patent, 18:56 19:2) (Jagannathan Dec., 110.) Thus, JEDEC discloses that the memory module has attributes and the circuit in the at least one configuration is further configured to store data accessible to the computer system, wherein the data characterizes the memory module as having attributes that are different from the attributes of the memory module. 2. Takeda, Karabatsos, and JEDEC render Dependent Claims 17 and 31 obvious An SPD as specified in JEDEC stores attributes including data related to row addresses, column addresses, and number of physical banks on the module as identified in the table below taken from page 68 of JEDEC

37 Table (excerpt) from p. 68 of JEDEC Thus, JEDEC discloses that the attributes are selected from a group consisting of: a number of row addresses, a number of column addresses, a number of DDR memory circuits, a data width of the DDR memory circuits, a memory density per DDR memory circuit, a number of ranks, and a memory density per rank. C. Ground 3: The Combination of Takeda, JEDEC and Connolly Renders Claims 1, 16, 17, 24, 30, and 31 Obvious. 1. Overview of Takeda, JEDEC, and Connolly As discussed above in Ground 1, Takeda discloses a memory module circuit that emulates a memory module having a certain number of ranks to a computer system whereas the actual memory module has a different number of ranks. Although Takeda discloses the use of a clock signal in the memory circuit, Takeda does not explicitly disclose that the clock signal is a phase-locked clock signal[]. However, the use of phase-lock clock signals was commonly implemented on memory modules before the critical date of the 536 patent as evidenced by JEDEC

38 JEDEC illustrates that the memory module includes a phase-locked loop device (JEDEC, pp. 17, 29.) The PLL of JEDEC directly provides the clock signal to the SDRAM memory devices. (JEDEC, p. 17.) It would be obvious to a PHOSITA to use the phase-lock clock signals as disclosed by JEDEC to control the timing of the elements of the memory module in Takeda. (Jagannathan Dec., 112.) JEDEC provides the specification for DDR SDRAM and describes using a PLL on the memory module to generate a clock signal provided to the memory devices. (Jagannathan Dec., 45-46, 99.) Furthermore, Takeda explicitly discloses that JEDEC documents are used to describe memory module configurations. (Takeda Trans., [0002]). As such, a PHOSITA would have been motivated to apply the known technique of phase locking clock signals as taught in JEDEC to the known memory circuit of Takeda to yield predictable result of providing timing signals to the elements of the memory module. (Jagannathan Dec., ) Takeda also does not explicitly disclose selectively isolate a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system. But performing selective isolation of the memory circuits was also well known as is evidenced by Connolly. Connolly is in the same field of SDRAM module design. (Connolly, 1:19-22; 3:22-24.) More specifically, Connolly aims to reduce the capacitance load of the memory chips on the bus: [w]hat is needed in order to better utilize less expensive RAM chips in systems

39 with otherwise limited memory expansion is a way to minimize data line capacitance loading so that oversize memory modules with banks of RAM chips can be added to the system. (Connolly, 1:48-53.) In order to reduce this capacitive loading, Connolly provides switches between the memory chips on a module: DRAMs to , preferably SDRAMs, are coupled through bit switches to as controlled by ASIC 910 (corresponding to ASICs 310 and 410 of FIG. 1). (Connolly, 5:7-13; FIG. 6A.) (See also Connolly 1:67 2:4.) The memory chips in Connolly are arranged within ranks of memory. (Jagannathan Dec., ) It would have been obvious to a PHOSITA to use the memory chip isolation technique of Connolly with the SDRAM memory chips of Takeda. (Jagannathan Dec., 111, ) Connolly explicitly discloses that performing the load isolation of the memory chips reduces capacitive loading on the data lines: [t]he present invention is a two part solution to reducing data line capacitance to an acceptable system limit. The first part is a memory module, e.g., single in-line memory module (SIMM) or a dual in-line memory module (DIMM), with in-line bus switches. (Connolly, 1:63-67.) The 536 patent uses switches to isolate memory ranks for the same reasons: the circuit 40 selectively isolates the loads of some (e.g., one or more) of the ranks of the memory module 10 from the computer system.... For example, when a memory module 10 is not being

40 accessed by the computer system, the capacitive load on the memory controller 20 of the computer system by the memory module 10 can be substantially reduced to the capacitive load of the circuit 40 of the memory module 10. ( 536 patent, 7:22-31.) A PHOSITA would recognize that the reduced capacitive load described by Connolly leads to a reduced power consumption. (Jagannathan Dec., 42, 113.) As such, a PHOSITA would have been motivated to apply the known technique of switching data outputs of different memory chips to the known memory circuits of Takeda to yield the predictable results reducing capacitive loading, and thus reducing power consumption. (Jagannathan Dec., ) 2. The combination of Takeda, JEDEC, and Connolly renders independent claims 1 and 24 obvious. a) Takeda discloses the preambles of independent claims 1 and 24 [1A, 24A]. Takeda discloses "a memory module configured to be operationally coupled to a computer system" and a "method of operating" such a memory module: In Takeda, the circuit convert[s] drive signals from outside the module, which are sent in order to control the plurality of banks, to signals for controlling the plurality of banks. (Takeda Trans., [0005].) Although Takeda does not specify the originator of the outside drive signals, it would be obvious to a PHOSITA that a computer system generates these drive signals. (Jagannathan Dec., )

41 Further, a PHOSITA would appreciate that it would be obvious that such a circuit is mounted on the memory module given that it receives signals from outside the module and converts them to signals that control the memory banks (which are also coupled to the memory module) (Jagannathan Dec., 61.) b) Takeda discloses the memory module configuration limitations ([1B], [24B]). Takeda discloses a "memory module having a first number of ranks, each rank of the first number of ranks comprising memory circuits": As illustrated in FIG. 1 (reproduced below with annotations), Takeda's memory module includes a plurality of banks comprising a plurality of current-generation SDRAMs... (Takeda Trans., [0005].) As discussed above, the banks disclosed in Takeda are the same as the claimed ranks. (Jagannathan Dec., 56.)

42 Annotated FIG. 1 from Takeda (Jagannathan Dec., p. 37.) Although Takeda describes the use of SDRAM circuits, a PHOSITA would readily understand that the teachings of Takeda could be applied to any synchronous memory architecture, which includes a "DDR memory circuit." (Jagannathan Dec., ) In fact, Takeda explicitly discloses that JEDEC documents are used to describe memory module configurations. (Takeda Trans., [0002]). Thus, a PHOSITA would understand that Takeda s teachings may be

43 applied to JEDEC compliant devices, such as a DDR SDRAM. (Jagannathan Dec., 65.) The memory circuits of Takeda "are configured to be activated concurrently with one another for receiving and transmitting data having a bit width of the rank in response at least in part to a first number of [] chip select signals." Takeda discloses the use of 4 banks (ranks): D0 D15; D16 D31; D32 D47; and D48 D63 with each bank (rank) selected using pairs of chip select signals selected from CS0 CS7 (a first number of chip select signals). (Takeda Trans., [0011] [0013].) (Jagannathan Dec., ) Each SDRAM of a selected bank would operate concurrently to output data on the data buses DQ0 DQ63 (defining the bit width of the selected bank.) (Jagannathan Dec., ) As noted above, it would be obvious to a PHOSITA that the teachings in Takeda regarding the activation of different ranks of memory could be applied to either SDRAM or DDR SDRAM. (Jagannathan Dec., 65.) Thus, it would be obvious to a PHOSITA that the DDR memory circuits are configured to be activated concurrently with one another in response at least in part to a first number of DDR chip select signals. c) Takeda discloses the receive limitation (1[C],24[C]). The circuit of Takeda "receiv[es] a set of signals comprising address signals" and a "second number of [] chip select signals": As shown in annotated FIG

44 below, the memory module circuit of Takeda receives address signals and a second number of chip-select signals. And, as discussed above, it would be obvious to a PHOSITA to use a DDR memory circuit in Takeda. Therefore, the received "chipselect signals" are "DDR chip-select signals." Annotated FIG. 2 from Takeda (Jagannathan Dec., p. 39.) In Takeda, the memory module circuit receives fewer chip-select signals than it generates. This is highlighted in annotated FIG. 2 showing two received chip-select signals whereas 8 chip-select signals are generated for transmission to the memory devices. Thus, Takeda discloses that the second number of DDR chip-select signals [is] smaller than the first number of DDR chip-select signals. d) The combination of Takeda and JEDEC discloses the phase-locked clock signal generation and transmission limitation. (1[D], 24[D]). Takeda discloses that the generation and transmission of a clock signal to the memory circuits of the first number of ranks: As shown in FIG. 1 of Takeda, a

45 clock (CLK) signal being received by each SDRAM memory chip receives a clock signal. (Jagannath han Dec., 66.) However, Takeda does not explicitly disclose that this clock signal is a phase-locked clock signal. JEDEC discloses memory modules having phase-lock ked loop devices for generating g phase-locked signals. (JEDEC, pp ) (Jagannathan Dec., ) The generated phase-locked clock signals are provided directly to the memory devices as shown in the annotated illustration below. Annotated Figure from p. 17 of JEDEC (Jagannathan Dec., p. 29) It would have been obvious to a PHOSITA to incorporate the phase-locked clock signal of JEDEC with the SDRAM memory module of Takeda, as already discussed above. (Jagannath han Dec., ) )

46 e) The combination of Takeda and Connolly discloses the selectively isolating limitation (1[E], 24[E]). Takeda does not explicitly disclose "selectively isolating a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals." However, Connolly discloses this limitation. Connolly provides switches between the memory chips on a module to reduce (i.e., isolate) the capacitive load on the bus. As illustrated in FIG. 6A (reproduced below), the "DRAMs to , preferably SDRAMs, are coupled through bit switches to as controlled by ASIC 910 (corresponding to ASICs 310 and 410 of FIG. 1). (Connolly, 5:7-13.) (See also Connolly 1:67 2:4.) Connolly uses switches to selectively electrically couple a memory device (memory circuits of at least one rank) and its associated load to the computer system and decouple other memory devices (memory circuits of at least one rank) and their associated loads from the computer system thereby isolating the unselected memory devices to reduce the capacitive load of the memory chips on the data bus: [w]hat is needed in order to better utilize less expensive RAM chips in systems with otherwise limited memory expansion is a way to minimize data line capacitance loading so that oversize memory modules with banks of RAM chips can be added to the system. (Connolly, 1:48-53.)

47 Connolly discloses that the operation of its switches (FETs) is responsive at least in part to the set of signals: As shown in the block diagram of FIG. 3, the ASIC 60 (corresponding to ASICs 310 and 410 of FIG. 1) receives the system s RAS and CAS signals, determines the READ/WRITE state of the memory from the RAS and CAS signals and generates therefrom, an RC_SELECT signal to the enable inputs of bus switches 61 and 62. (Connolly, 4:12-17.) Thus, Connolly's FETs are controlled by signals from the ASIC which in turn are generated based on a received set of input signals. In Takeda, the shared data bus line (DQ0-3) connects to memory chips D0, D16, D32, and D48, with each memory chip in a different bank. Since each chip shares the same data bus, each chip may be isolated from one another using the FET switches taught be Connolly. When this is performed for each row of chips in Takeda, an entire bank of chips is isolated. (Jagannathan Dec., 97, 113.) Because Connolly already determines the switch on/off state based on signals related to the operation of the memory chips, it would have been obvious to a PHOSITA that the switches of Connolly would operate based at least on the generated chip select signals to isolate certain memory devices (memory circuits). (Jagannathan Dec., 113.) The FET enable signals of Connolly are activated relative to which chip select signals are activated (e.g., the CS0-CS7 generated from the logic element of Takeda.) (Jagannathan Dec., 113.)

48 f) The combination of Takeda and JEDEC discloses the first number of chip-select signal generation limitation (1[F],24[F]). The memory module circuit of Takeda generat[es] the first number of [DDR] chip-select signals in response to at least in part the address signals, and the second number of DDR chip-select signals. As shown in FIG. 2 from Takeda, the logic circuitry generates the first number of chip-select signals at least in part based on the address signals (A12 and A13) and the second number of chip-select signals (S0 and S2). (Jagannathan Dec., ) As discussed above, when DDR memory circuits are substituted for the SDRAM memory circuits of Takeda, the chip-select signals are DDR chip-select signals. Takeda does not explicitly disclose that the generation of the first number of chip-select signals is in response in part to "the phase-locked clock signals." However, the timing diagram of Takeda shown in FIG. 3 illustrates how each of the signal transitions is influenced by the clock signal (CLK). (Jagannathan Dec., 62.) It would be obvious to a PHOSITA that the clock signal could be improved to be a phase-locked clock signal as shown in JEDEC and discussed above. Therefore, the combination of Takeda and JEDEC discloses that the generation of the first number of chip-select signals can additionally be in response to the phaselocked clock signals of JEDEC. (Jagannathan Dec., 112.)

49 3. The combination of Takeda, JEDEC, and Connolly renders claims 16 and 30 obvious. As discussed in detail above for Ground 2, the combination of Takeda and JEDEC discloses the subject matter of claims 16 and 30. Therefore, for the same reasons, the combination of Takeda, JEDEC and Connolly renders dependent claims 16 and 30 obvious. 4. The combination of Takeda, JEDEC, and Connolly renders claims 17 and 31 obvious. As discussed in detail above for Ground 2, the combination of Takeda and JEDEC discloses the subject matter of claims 17 and 31. Therefore, for the same reasons, the combination of Takeda, JEDEC and Connolly renders dependent claims 17 and 31 obvious. D. Ground 4: The Combination of Amidi and Connolly Renders Claims 1, 16, 17, 24, 30, and 31 Obvious. 1. Overview of Amidi and Connolly Amidi discloses a four rank memory module that emulates a two rank memory module: [a] need therefore exists for a transparent four rank memory module fitting into a memory socket having two chip select signals routed. A primary purpose of the present invention is to solve these needs and provide further, related advantages. (Amidi, [0011].) Using more ranks of memory on the memory module allows for more lower density memory chips to be used to achieve the same memory capacity as a memory module with fewer higher density chips

50 (Jagannathan Dec., 69.) Amidi recognizes the economic benefit of using more lower-density memory chips: [b]ecause memory devices with lower densities are cheaper and more readily available, it may be advantageous to build the above same density memory module using lower densities devices. (Amidi, [0008].) The 536 patent provides the same motivation for using more lower-density memory chips on the memory module. ( 536 patent, 15:20-33.) FIG. 4A of Amidi (reproduced below) illustrates an exemplary DDR memory module 400 having a set of memory devices 404, a complex programmable logic device (CPLD) 410, a phase-lock loop (PLL) device 412, a register 408, and a serial-presence detect (SPD) device 414. (Amidi, [0037]; Fig. 4A.) The DDR memory devices of Amidi are organized into four ranks on the memory module. (Amidi, [0004], [0034]-[0035].) The memory devices 306 of each rank receive and transmit data using a data bus [7:0]. (Id., [0034], Fig. 3.)

51 The CPLD of Amidi receives input signalss including address signals and two input chip-select signals (CS0, CS1) from the computer system. In response to the input signals, the CPLD generates four output chip-select signals (rcs0, rcs1, rcs2, rcs3): CPLD 604 generates rcs2 and rcs3, besides rcs0 and rcs1 off of CS0, CS1, and Add(n) from the memory controller side. (Id., [0052].) The output chip select signals are then used to determine an active rank from the four ranks. (Amidi, [0043], [0052]) CPLD. FIG. 6A (reproduce ed below) depicts the signals to and from the

52 FIG. 6A from Amidi Amidi discloses that only one memory rank is active at one time. (Amidi, [0043] [0044].) However, Amidi does not explicitly disclose selectively isolate[ing] a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system. But performing selective isolation of the memory circuits was also well known as is evidenced by Connolly. Connolly is in the same field of SDRAM module design. (Connolly, 1:19-22; 3:22-24.) More specifically, Connolly aims to reduce the capacitance load of the memory chips on the bus: [w]hat is needed in order to better utilize less expensive RAM chips in systemss with otherwise limited memory expansion is a way to minimize dataa line capacitance loading so that oversize memory modules with banks of RAM chips can be added to the system. (Connolly, 1:48-53.) In orderr to reduce this capacitive

53 loading, Connolly provides switches between the memory chips on a module: DRAMs to , preferably SDRAMs, are coupled through bit switches to as controlled by ASIC 910 (corresponding to ASICs 310 and 410 of FIG. 1). ASIC 910 determines whether the SDRAM to on the DIMM 90 is in a READ/WRITE state or the bit switches to should remain inactive. (Connolly, 5:7-13; FIG. 6A.) (See also Connolly 1:67 2:4.) The memory chips in Connolly are arranged within ranks of memory. (Jagannathan Dec., ) It would have been obvious to a PHOSITA to use the memory chip isolation technique of Connolly with the DDR memory chips of Amidi. (Jagannathan Dec., ) Connolly explicitly discloses that performing the load isolation of the memory chips reduces capacitive loading on the data lines: [t]he present invention is a two part solution to reducing data line capacitance to an acceptable system limit. The first part is a memory module, e.g., single in-line memory module (SIMM) or a dual in-line memory module (DIMM), with in-line bus switches. (Connolly, 1:63-67.) The 536 patent uses switches to isolate memory ranks for the same reasons: the circuit 40 selectively isolates the loads of some (e.g., one or more) of the ranks of the memory module 10 from the computer system.... For example, when a memory module 10 is not being accessed by the computer system, the capacitive load on the memory

54 controller 20 of the computer system by the memory module 10 can be substantially reduced to the capacitive load of the circuit 40 of the memory module 10. ( 536 patent, 7:22-31.) A PHOSITA would recognize that the reduced capacitive load described by Connolly leads to a reduced power consumption. (Jagannathan Dec., 42, 117.) As such, a PHOSITA would have been motivated to apply the known technique of switching data outputs of different memory chips to the known memory circuits of Amidi to yield the predictable results reducing capacitive loading, thus reducing power consumption. (Jagannathan Dec., ) 2. The combination of Amidi and Connolly renders independent claims 1 and 24 obvious a) Amidi discloses the preambles of independent claims 1 and 24 [1A, 24A]. Amidi discloses "a memory module configured to be operationally coupled to a computer system" and a "method of operating" such a memory module: memory module 400 as illustrated in FIG. 4A includes a register 408, a CPLD 410, a PLL 412, and a SPD 414. (Amidi, [0037]; FIG. 4A.) The memory module of Amidi is coupled to a computer system as the module includes memory accessed by the computer system: [c]omputers use memory devices for the storage and retrieval of information. These memory devices are often mounted on a memory module to expand the memory capacity of the computer. (Amidi, [0002].) Thus, Amidi discloses the features of claim elements 1[A] and 24 [A]

55 b) Amidi discloses the memory module configuration limitations ([1B], [24B]). Amidi discloses a "memory module having a first number of ranks, each rank of the first number of ranks comprising memory circuits": Amidi illustrates a four-rank DDR memory module in FIG. 3 (Amidi, [0017]) Each rank includes memory devices having a total bit width of 72 bits designed to be concurrently accessed via a data bus. (Amidi, [0034].) (Jagannathan Dec., 77.) Each rank is selected in response to its own chip select signal: [a] chip select signal is coupled to each rank of memory devices... chip select signal cs0 is connected to the first rank chip select signal cs2 is connected to the third rank chip select signal cs1 is connected to the second rank chip select signal cs3 is connected to the fourth rank 314. (Amidi, [0034] [0035].) Chip select signals cs1, cs2, cs3, and cs4 make up the claimed first number of DDR chip-select signals. (Jagannathan Dec., 77, 85, 87.) c) Amidi discloses the receive limitation (1[C],24[C]). The circuit of Amidi "receiv[es] a set of signals comprising address signals" and a "second number of [] chip select signals": Amidi discloses a circuit (CPLD) that emulates a two rank memory module on the four rank memory module The CPLD 410 determines which rank from the four ranks to activate based on the address and command signals from a memory controller coupled to the memory module 410. (Amidi, [0041].) The CPLD of Amidi receives a first

56 number of chip select signals (cs0 and cs1) from the computer (i.e., first number of chip-select signalss compatible with the system memory domain) and generates a second number of chip-select signals (rcs0, rcs1,, rcs2, rcs3) to activate the different banks of memory (i.e., second number of chip select signals compatible with the physical memory domain.) (Amidi, [0041], [0052], [0062].) FIG. 6A (reproduced below with annotations) illustrates the addresss signals, first number of DDR chip-select signals and second number of DDR chip-select signals. Annotated FIG. 6A from Amidi (Jagannathann Dec., p. 51) Thus, Amidi disclosess that the second number of DDR chip-select signals [is] smaller than the first number of DDR chip-select signals