RF ESD Protection Strategies The Design and Performance Trade-off Challenges

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1 RF ESD Protection Strategies The Design and Performance Trade-off Challenges Ph.Jansen, S.Thijs, D.Linten, M.I.Natarajan V.Vassilev, M.Liu, D.Trémouilles, S.Decoutere, G.Groeseneken T.Nakaie, M.Sawada, T.Hasebe A.Concannon, V.Vashchenko, M.ter Beek

2 Outline of Presentation Introduction Key performance parameters Diode protection with Power Clamp Inductor protection with Power Clamp Full circuit ESD co-design Partial circuit ESD co-design Conclusions CICC05 - IMEC 2

3 Introduction: RF circuit design Integrated RF 5.5 GHz 90nm CMOS technology BiCMOS technology Typical design for performance: Large gain Low noise Linearity But ESD protection is often overlooked CICC05 - IMEC 3

4 Introduction: RF circuit design Common issues of ESD protection: Extra input capacitance Gain reduction Noise increase Comparison of advantages and disadvantages of several ESD protection strategies CICC05 - IMEC 4

5 Introduction: ESD protection V DD, p1 V DD V DD, p2 Diode protection with power clamp Zap RF IN ESD1 ESD2 B A L G L LOAD C 1 C L 2 S ESD5 ESD3 ESD4 RF OUT Inductor protection with power clamp Distributed protection Resonant and cancellation V SS, p1 V SS, p2 Co-design V SS CICC05 - IMEC 5

6 Key performance parameters Performance figure Target Value f C ) f C S11 S22 S21 S12 NF IIP3 Ptot Area ESD protection level 5.5 GHz < -10 db < -10 db > 15 db < -30 db < 3 db As high as possible As low as possible As small as possible > 2 kv HBM CICC05 - IMEC 6

7 Key performance parameters Low-power RF Figure-Of-Merit FOM 1 [ mw 1 ] = Gain[ abs] ( NF[ abs] 1). P [ mw ] Brederlow s RF Figure-Of-Merit DC FOM 2 [ GHz] = Gain[ abs]. IIP3[ mw ]. fc[ GHz] ( NF[ abs] 1). P [ mw ] DC CICC05 - IMEC 7

8 Diode protection with Power Clamp BiCMOS LNA F c = 5.5 GHz Pn and Np diodes of 71μm 2 (~100fF) S21 reduction NF: +0.4 db FOM 2 increase 50V -> 3kV HBM Gain (S21), Input reflection (S11) [db] S21 S Frequency [GHz] CICC05 - IMEC 8

9 Diode protection with Power Clamp 90nm CMOS LNA F c = 5 GHz Pn and Np diodes of 65μm 2 (~100fF) S21 reduction NF: +0.6 db FOM 2 increase <50V -> 500V HBM Insufficient: Why? Frequency [GHz] CICC05 - IMEC Frequency [GHz] 9 Gain (S21), Input reflection (S11) [db] Noise figure 50 Ω [db] ESD protected LNA Reference LNA ESD protected LNA Reference LNA

10 Diode protection with Power Clamp V DD, p1 V DD V DD, p2 Insufficient protection ESD current path B Zap RF IN ESD1 ESD2 B A L G L LOAD C 1 C L 2 S ESD5 ESD3 ESD4 RF OUT Parasitic current path A V SS, p1 V SS V SS, p2 CICC05 - IMEC 10

11 Diode protection with Power Clamp Insufficient protection: BiCMOS LNA: parasitic ESD current flows through L G, emitter diode and L S to ground 90nm CMOS LNA: parasitic ESD current loads gate capacitor and builds up overvoltage Solutions: On-chip capacitor Series resistor CICC05 - IMEC 11

12 Inductor protection with Power Clamp V DD CA I BIAS C DEC M 1' L load M ESD R B M 2 C 1 RF IN A D 5 D 4 RF OUT C pad L ESD C c L g M 1 D 1 D 3 D 2 L s C 2 C pad CICC05 - IMEC 12

13 Inductor protection with Power Clamp Addition of inductor as plug-n-play Diverts ESD current to ground Is transparent for the RF signal Inductor selection: S11 input matching Over-voltage at the gate during ESD Parasitic resistance of the inductor during ESD and in RF operation CICC05 - IMEC 13

14 Inductor protection with Power Clamp 0-5 S11 (db) no inductor 1nH inductor 2nH inductor 3nH inductor 5nH inductor Frequency (GHz) CICC05 - IMEC 14

15 Inductor protection with Power Clamp Vgate (V) nH inductor 3nH inductor 2nH inductor 1nH inductor Time (s) CICC05 - IMEC 15

16 Inductor protection with Power Clamp M ESD L ESD CICC05 - IMEC 16

17 Inductor protection with Power Clamp Measurement results Gain (S21), Input reflection (S11) [db] ESD protected LNA Reference LNA Frequency [GHz] Noise figure 50 Ω [db] ESD protected LNA Reference LNA Frequency [GHz] CICC05 - IMEC 17

18 Inductor protection with Power Clamp Gate over-voltage protection Add a minimum size reverse diode at the gate to block negative over-voltage Add two minimum size forward diodes at the gate, biased at 0.6V to block positive over-voltage These diodes are placed right in front of the gate CICC05 - IMEC 18

19 Inductor protection with Power Clamp V in C c V gate M 2 L g M 1 L ESD L s Schematic with additional diodes to clamp the voltage at M1 CICC05 - IMEC 19

20 Inductor protection with Power Clamp Circuit LNA ESD-LNA ESD-LNA no ESD w/o diodes with diodes Vdd [Volt] Current [ma] Gain [db] S11 [db] S22 [db] S12 [db] NF [db] dB CP [dbm] IIP3 [dbm] TLP [A] HBM [kv] MM [V] CICC05 - IMEC 20

21 Inductor protection with Power Clamp Measurement results Gain (S21), Input reflection (S11) [db] ESD protected LNA Reference LNA Frequency [GHz] Noise figure 50 Ω [db] ESD protected LNA Reference LNA Frequency [GHz] CICC05 - IMEC 21

22 Full circuit ESD co-design ESD protection is integrated into the matching circuit Typical matching circuit is extended to include ESD protection CICC05 - IMEC 22

23 Full circuit ESD co-design Schematic including the ESD protection into the matching circuit CICC05 - IMEC 23

24 Full circuit ESD co-design Circuit LNA no ESD ESD-LNA Co-design Vdd [Volt] Current [ma] Gain [db] S11 [db] S22 [db] S12 [db] NF [db] dB CP [dbm] IIP3 [dbm] -1-5 HBM [kv] CICC05 - IMEC 24

25 Full circuit ESD co-design Measurement results Gain (S21), Input reflection (S11) [db] ESD protected LNA Reference LNA Frequency [GHz] Noise figure 50 Ω [db] ESD protected LNA Reference LNA Frequency [GHz] CICC05 - IMEC 25

26 Partial circuit ESD co-design Determine parasitic loading due to the ESD protection and other parasitics Take this value into account for input/output matching Opposite to previous methods Determine ESD robustness Optimize LNA for this robustness CICC05 - IMEC 26

27 Partial circuit ESD co-design V CC V CC L bw L bw bonding wire bondpad D ESD1 L o R o D ESD1 In C d L bwin V Bias2 V Bias1 Q 2 C o R L L bwout C d Out Q 1 Q buf D ESD2 L e1 L e2 V Bias3 L buf on-chip D ESD2 L bw L bw CICC05 - IMEC 27

28 Partial circuit ESD co-design Measurement results for an ultra wideband LNA in 0.35μm BiCMOS technology Gain (db) NF (db) Frequency (GHz) CICC05 - IMEC 28

29 Conclusions Comparison of 4 RF ESD protection strategies with respect to their respective performance trade-offs Discussion of the limiting factors and proposal of solutions for further improvement Review of the performance parameters for 90nm CMOS LNA s at 5 GHz CICC05 - IMEC 29

30 Conclusions Circuit LNA LNA ESD-LNA ESD-LNA ESD-LNA diodes inductor inductor co-design w/o diodes with diodes Vdd [V] Current [ma] Gain [db] S11 [db] S22 [db] S12 [db] NF [db] dB CP [dbm] IIP3 [dbm] TLP [A] HBM [kv] MM [V] CICC05 - IMEC 30