MC68HC908JB8 MC68HC08JB8 MC68HC08JT8

Transcription

1 MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Technical Data M68HC08 Microcontrollers MC68HC908JB8/D Rev /2005 freescale.com

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3 MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale and the Freescale logo are registered trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash technology licensed from SST. Freescale Semiconductor, Inc., All rights reserved. MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor 3

4 Revision History Revision History Date Revision Level Description Page Number(s) September 2005 August Added Pb-free parts. 267, Updated to meet Freescale identity guidelines. Throughout.9 ROM-Resident Routines Removed block erase references for ROM-resident routines. 61 December USB Control Register 3 Clarified bit descriptions for OSTALL0 and ISTALL USB Status Register 1 Clarified bit descriptions for TXACK, TXNAK, and TXSTL. 19, Section 19. Mechanical Specifications Replaced incorrect -pin QFP drawing, case 82E to case 82A. 263 February Corrected PTD6 and PTD7: not direct LED drive pins. 28, 210, 217 Removed incorrect RX1E text from USB control register Corrected Figure 9-30 for USB module. 159 Corrected timer discrepancies throughout Section 11. Timer Interface Module (TIM). Added Table Port Control Register Bits Summary. 201 Changed pullup resistor limits for D and I/O ports in 18.6 DC Electrical Characteristics. Added mechanical drawing for 20-pin SOIC package. 266 Added Appendix A. MC68HC08JB8 ROM part. 269 Added Appendix B. MC68HC08JT8 low-voltage ROM part Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Freescale Semiconductor

5 Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 List of Sections Section 1. General Description Section 2. Memory Map Section 3. Random-Access Memory (RAM) Section. FLASH Memory Section 5. Configuration Register (CONFIG) Section 6. Central Processor Unit (CPU) Section 7. Oscillator (OSC) Section 8. System Integration Module (SIM) Section 9. Universal Serial Bus Module (USB) Section 10. Monitor ROM (MON) Section 11. Timer Interface Module (TIM) Section 12. Input/Output Ports (I/O) Section 13. External Interrupt (IRQ) Section 1. Keyboard Interrupt Module (KBI) Section 15. Computer Operating Properly (COP) Section 16. Low Voltage Inhibit (LVI) Section 17. Break Module (BREAK) Section 18. Electrical Specifications Section 19. Mechanical Specifications Section 20. Ordering Information Appendix A. MC68HC08JB Appendix B. MC68HC08JT MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor List of Sections 5

6 List of Sections Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev List of Sections Freescale Semiconductor

7 Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Table of Contents Section 1. General Description 1.1 Contents Introduction Features MCU Block Diagram Pin Assignments Power Supply Pins (V DD, V SS ) Voltage Regulator Out (V REG ) Oscillator Pins (OSC1 and OSC2) External Reset Pin (RST) External Interrupt Pins (IRQ, PTE/D ) Port A Input/Output (I/O) Pins (PTA7/KBA7 PTA0/KBA0) Port B (I/O) Pins (PTB7 PTB0) Port C I/O Pins (PTC7 PTC0) Port D I/O Pins (PTD7 PTD0) Port E I/O Pins (PTE/D, PTE3/D+, PTE2/TCH1, PTE1/TCH0, PTE0/TCLK) Section 2. Memory Map 2.1 Contents Introduction I/O Section Monitor ROM MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor Table of Contents 7

8 Table of Contents Section 3. Random-Access Memory (RAM) 3.1 Contents Introduction Functional Description Section. FLASH Memory.1 Contents Introduction Functional Description FLASH Control Register FLASH Block Erase Operation FLASH Mass Erase Operation FLASH Program Operation FLASH Protection FLASH Block Protect Register ROM-Resident Routines Variables ERASE Routine PROGRAM Routine VERIFY Routine Section 5. Configuration Register (CONFIG) 5.1 Contents Introduction Functional Description Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev Table of Contents Freescale Semiconductor

9 Table of Contents Section 6. Central Processor Unit (CPU) 6.1 Contents Introduction Features CPU Registers Accumulator Index Register Stack Pointer Program Counter Condition Code Register Arithmetic/Logic Unit (ALU) Low-Power Modes Wait Mode Stop Mode CPU During Break Interrupts Instruction Set Summary Opcode Map Section 7. Oscillator (OSC) 7.1 Contents Introduction Oscillator External Connections I/O Signals Crystal Amplifier Input Pin (OSC1) Crystal Amplifier Output Pin (OSC2) Oscillator Enable Signal (SIMOSCEN) External Clock Source (OSCXCLK) Oscillator Out (OSCOUT) Low-Power Modes Wait Mode Stop Mode Oscillator During Break Mode MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor Table of Contents 9

10 Table of Contents Section 8. System Integration Module (SIM) 8.1 Contents Introduction SIM Bus Clock Control and Generation Bus Timing Clock Startup from POR or LVI Reset Clocks in Stop Mode and Wait Mode Reset and System Initialization External Pin Reset Active Resets from Internal Sources Power-On Reset Computer Operating Properly (COP) Reset Illegal Opcode Reset Illegal Address Reset Low-Voltage Inhibit (LVI) Reset Universal Serial Bus Reset Registers Values After Different Resets SIM Counter SIM Counter During Power-On Reset SIM Counter During Stop Mode Recovery SIM Counter and Reset States Exception Control Interrupts Hardware Interrupts SWI Instruction Interrupt Status Registers Interrupt Status Register Reset Break Interrupts Status Flag Protection in Break Mode Low-Power Modes Wait Mode Stop Mode SIM Registers Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev Table of Contents Freescale Semiconductor

11 Table of Contents Break Status Register Reset Status Register Break Flag Control Register Section 9. Universal Serial Bus Module (USB) 9.1 Contents Introduction Features Pin Name Conventions Functional Description USB Protocol Sync Pattern Packet Identifier Field Address Field (ADDR) Endpoint Field (ENDP) Cyclic Redundancy Check (CRC) End-of-Packet (EOP) Reset Signaling Suspend Resume After Suspend Host Initiated Resume USB Reset Signalling Remote Wakeup Low-Speed Device Clock Requirements Hardware Description Voltage Regulator USB Transceiver Output Driver Characteristics Low Speed (1.5 Mbps) Driver Characteristics Receiver Data Jitter Data Source Jitter Data Signal Rise and Fall Time USB Control Logic MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor Table of Contents 11

12 Table of Contents 9.8 I/O Registers USB Address Register USB Interrupt Register USB Interrupt Register USB Interrupt Register USB Control Register USB Control Register USB Control Register USB Control Register USB Control Register USB Status Register USB Status Register USB Endpoint 0 Data Registers USB Endpoint 1 Data Registers USB Endpoint 2 Data Registers USB Interrupts USB End-of-Transaction Interrupt Receive Control Endpoint Transmit Control Endpoint Transmit Endpoint Transmit Endpoint Receive Endpoint Resume Interrupt End-of-Packet Interrupt Section 10. Monitor ROM (MON) 10.1 Contents Introduction Features Functional Description Entering Monitor Mode Baud Rate Data Format Echoing Break Signal Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev Table of Contents Freescale Semiconductor

13 Table of Contents Commands Security Section 11. Timer Interface Module (TIM) 11.1 Contents Introduction Features Pin Name Conventions Functional Description TIM Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Buffered Output Compare Pulse Width Modulation (PWM) Unbuffered PWM Signal Generation Buffered PWM Signal Generation PWM Initialization Interrupts Low-Power Modes Wait Mode Stop Mode TIM During Break Interrupts I/O Signals TIM Clock Pin (PTE0/TCLK) TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1) I/O Registers TIM Status and Control Register TIM Counter Registers TIM Counter Modulo Registers TIM Channel Status and Control Registers TIM Channel Registers MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor Table of Contents 13

14 Table of Contents Section 12. Input/Output Ports (I/O) 12.1 Contents Introduction Port A Port A Data Register Data Direction Register A Port B Port B Data Register Data Direction Register B Port C Port C Data Register Data Direction Register C Port D Port D Data Register Data Direction Register D Port E Port E Data Register Data Direction Register E Port Options Port Option Control Register Section 13. External Interrupt (IRQ) 13.1 Contents Introduction Features Functional Description IRQ Pin PTE/D Pin IRQ Module During Break Interrupts IRQ Status and Control Register IRQ Option Control Register Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev Table of Contents Freescale Semiconductor

15 Table of Contents Section 1. Keyboard Interrupt Module (KBI) 1.1 Contents Introduction Features Pin Name Conventions Functional Description Keyboard Initialization Low-Power Modes Wait Mode Stop Mode Keyboard Module During Break Interrupts I/O Registers Keyboard Status and Control Register Keyboard Interrupt Enable Register Section 15. Computer Operating Properly (COP) 15.1 Contents Introduction Functional Description I/O Signals OSCXCLK STOP Instruction COPCTL Write Power-On Reset Internal Reset Reset Vector Fetch COPD (COP Disable) COPRS (COP Rate Select) COP Control Register Interrupts MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor Table of Contents 15

16 Table of Contents 15.7 Monitor Mode Low-Power Modes Wait Mode Stop Mode COP Module During Break Mode Section 16. Low Voltage Inhibit (LVI) 16.1 Contents Introduction Functional Description LVI Control Register (CONFIG) Low-Power Modes Wait Mode Stop Mode Section 17. Break Module (BREAK) 17.1 Contents Introduction Features Functional Description Flag Protection During Break Interrupts CPU During Break Interrupts TIM During Break Interrupts COP During Break Interrupts Low-Power Modes Wait Mode Stop Mode Break Module Registers Break Status and Control Register Break Address Registers Break Status Register Break Flag Control Register (BFCR) Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev Table of Contents Freescale Semiconductor

17 Table of Contents Section 18. Electrical Specifications 18.1 Contents Introduction Absolute Maximum Ratings Functional Operating Range Thermal Characteristics DC Electrical Characteristics Control Timing Oscillator Characteristics USB DC Electrical Characteristics USB Low-Speed Source Electrical Characteristics USB Signaling Levels TImer Interface Module Characteristics Memory Characteristics Section 19. Mechanical Specifications 19.1 Contents Introduction Pin Plastic Quad Flat Pack (QFP) Pin Small Outline Integrated Circuit (SOIC) Pin Dual In-Line Package (PDIP) Pin Small Outline Integrated Circuit (SOIC) Section 20. Ordering Information 20.1 Contents Introduction MC Order Numbers MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor Table of Contents 17

18 Table of Contents Appendix A. MC68HC08JB8 A.1 Contents A.2 Introduction A.3 MCU Block Diagram A. Memory Map A.5 Reserved Registers A.6 Monitor ROM A.7 Electrical Specifications A.7.1 DC Electrical Characteristics A.7.2 Memory Characteristics A.8 MC68HC08JB8 Order Numbers Appendix B. MC68HC08JT8 B.1 Contents B.2 Introduction B.3 MCU Block Diagram B. Memory Map B.5 Power Supply Pins B.6 Reserved Register Bit B.7 Reserved Registers B.8 Monitor ROM B.9 Universal Serial Bus Module B.10 Low-Voltage Inhibit Module B.11 Electrical Specifications B.11.1 Absolute Maximum Ratings B.11.2 Functional Operating Range B.11.3 DC Electrical Characteristics B.11. Control Timing B.11.5 Memory Characteristics B.12 MC68HC08JT8 Order Numbers Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev Table of Contents Freescale Semiconductor

19 Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 List of Figures Figure Title Page 1-1 MCU Block Diagram Pin QFP Pin Assignments pin SOIC Pin Assignments pin PDIP and SOIC Pin Assignments Power Supply Bypassing Regulator Supply Capacitor Configuration Memory Map Control, Status, and Data Registers FLASH Memory Register Summary FLASH Control Register (FLCR) FLASH Programming Flowchart FLASH Block Protect Register (FLBPR) FLASH Block Protect Start Address Configuration Register (CONFIG) CPU Registers Accumulator (A) Index Register (H:X) Stack Pointer (SP) Program Counter (PC) Condition Code Register (CCR) Oscillator External Connections SIM Block Diagram SIM I/O Register Summary SIM Clock Signals MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor List of Figures 19

20 List of Figures Figure Title Page 8- External Reset Timing Internal Reset Timing Sources of Internal Reset POR Recovery Interrupt Processing Interrupt Entry Interrupt Recovery Interrupt Recognition Example Interrupt Status Register 1 (INT1) Wait Mode Entry Timing Wait Recovery from Interrupt or Break Wait Recovery from Internal Reset Stop Mode Entry Timing Stop Mode Recovery from Interrupt or Break Break Status Register (BSR) Reset Status Register (RSR) Break Flag Control Register (BFCR) USB I/O Register Summary USB Block Diagram Supported Transaction Types Per Endpoint Supported USB Packet Types Sync Pattern SOP, Sync Signaling, and Voltage Levels EOP Transaction Voltage Levels EOP Width Timing External Low-Speed Device Configuration Regulator Electrical Connections Receiver Characteristics Differential Input Sensitivity Range Data Jitter Data Signal Rise and Fall Time USB Address Register (UADDR) USB Interrupt Register 0 (UIR0) USB Interrupt Register 1 (UIR1) USB Interrupt Register 2 (UIR2) Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev List of Figures Freescale Semiconductor

21 List of Figures Figure Title Page 9-19 USB Control Register 0 (UCR0) USB Control Register 1 (UCR1) USB Control Register 2 (UCR2) USB Control Register 3 (UCR3) USB Control Register (UCR) USB Status Register 0 (USR0) USB Status Register 1 (USR1) USB Endpoint 0 Data Registers (UE0D0 UE0D7) USB Endpoint 1 Data Registers (UE1D0 UE1D7) USB Endpoint 2 Data Registers (UE2D0 UE2D7) OUT Token Data Flow for Receive Endpoint SETUP Token Data Flow for Receive Endpoint IN Token Data Flow for Transmit Endpoint IN Token Data Flow for Transmit Endpoint Monitor Mode Circuit Low-Voltage Monitor Mode Entry Flowchart Monitor Data Format Sample Monitor Waveforms Read Transaction Break Transaction Monitor Mode Entry Timing TIM Block Diagram TIM I/O Register Summary PWM Period and Pulse Width TIM Status and Control Register (TSC) TIM Counter Registers (TCNTH:TCNTL) TIM Counter Modulo Registers (TMODH:TMODL) TIM Channel Status and Control Registers (TSC0:TSC1) CHxMAX Latency TIM Channel Registers (TCH0H/L:TCH1H/L) I/O Port Register Summary Port A Data Register (PTA) Data Direction Register A (DDRA) MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor List of Figures 21

22 List of Figures 12- Port A I/O Circuit Port B Data Register (PTB) Data Direction Register B (DDRB) Port B I/O Circuit Port C Data Register (PTC) Data Direction Register C (DDRC) Port C I/O Circuit Port D Data Register (PTD) Data Direction Register D (DDRD) Port D I/O Circuit Port E Data Register (PTE) Data Direction Register E (DDRE) Port E I/O Circuit Port Option Control Register (POCR) IRQ Module Block Diagram IRQ I/O Register Summary IRQ Status and Control Register (ISCR) IRQ Option Control Register (IOCR) Keyboard Module Block Diagram Keyboard Status and Control Register (KBSCR) Keyboard Interrupt Enable Register (KBIER) COP Block Diagram Configuration Register (CONFIG) COP Control Register (COPCTL) LVI Module Block Diagram Configuration Register (CONFIG) Break Module Block Diagram Break I/O Register Summary Break Status and Control Register (BRKSCR) Break Address Register High (BRKH) Break Address Register Low (BRKL) Break Status Register (BSR) Break Flag Control Register High (BFCR) Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev List of Figures Freescale Semiconductor

23 List of Figures Figure Title Page Pin QFP (Case #82E) Pin SOIC (Case #751F) Pin PDIP (Case #738) Pin SOIC (Case #751D) A-1 MC68HC08JB8 Block Diagram A-2 MC68HC08JB8 Memory Map B-1 MC68HC08JT8 Block Diagram B-2 MC68HC08JT8 Memory Map B-3 Power Supply Bypassing MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor List of Figures 23

24 List of Figures Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev List of Figures Freescale Semiconductor

25 Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 List of Tables Table Title Page 1-1 Summary of Pin Functions Vector Addresses ROM-Resident Routines ROM-Resident Routine Variables ERASE Routine PROGRAM Routine VERIFY Routine Instruction Set Summary Opcode Map SIM Module Signal Name Conventions PIN Bit Set Timing Registers not Affected by Normal Reset Interrupt Sources USB Module Pin Name Conventions Supported Packet Identifiers Mode Entry Requirements and Options Monitor Mode Vector Differences Monitor Baud Rate Selection READ (Read Memory) Command WRITE (Write Memory) Command IREAD (Indexed Read) Command IWRITE (Indexed Write) Command READSP (Read Stack Pointer) Command RUN (Run User Program) Command MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor List of Tables 25

26 List of Tables 11-1 TIM Pin Name Conventions Prescaler Selection Mode, Edge, and Level Selection Port Control Register Bits Summary Port A Pin Functions Port B Pin Functions Port C Pin Functions Port D Pin Functions Port E Pin Functions KBI Pin Name Conventions I/O Register Summary MC Order Numbers A-1 Summary of MC68HC08JB8 and MC68HC908JB8 Differences A-2 MC68HC08JB8 Order Numbers B-1 Summary of MC68HC08JT8 and MC68HC908JB8 Differences B-2 MC68HC08JT8 Order Numbers Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev List of Tables Freescale Semiconductor

27 Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Section 1. General Description 1.1 Contents 1.2 Introduction Features MCU Block Diagram Pin Assignments Power Supply Pins (V DD, V SS ) Voltage Regulator Out (V REG ) Oscillator Pins (OSC1 and OSC2) External Reset Pin (RST) External Interrupt Pins (IRQ, PTE/D ) Port A Input/Output (I/O) Pins (PTA7/KBA7 PTA0/KBA0) Port B (I/O) Pins (PTB7 PTB0) Port C I/O Pins (PTC7 PTC0) Port D I/O Pins (PTD7 PTD0) Port E I/O Pins (PTE/D, PTE3/D+, PTE2/TCH1, PTE1/TCH0, PTE0/TCLK) Introduction The MC68HC908JB8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor General Description 27

28 General Description 1.3 Features Features of the MC68HC908JB8 include: High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M16805, and M68HC05 Families 3-MHz internal bus frequency 8,192 bytes of on-chip FLASH memory 256 bytes of on-chip random-access memory (RAM) FLASH program memory security 1 On-chip programming firmware for use with host PC computer Up to 37 general-purpose 3.3V input/output (I/O) pins, including: 13 or 10 shared-function I/O pins, depending on package 2, 8, or 2 dedicated I/O pins, depending on package 8 keyboard interrupts on port A, on all packages 10mA sink capability for normal LED on pins 25mA sink capability for infrared LED on 2 pins 10mA sink capability for PS/2 connection on 2 pins (with USB module disabled) 16-bit, 2-channel timer interface module (TIM) with selectable input capture, output compare, PWM capability on each channel, and external clock input option (TCLK) Full Universal Serial Bus Specification 1.1 low-speed functions: 1.5 Mbps data rate On-chip 3.3V regulator Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer Endpoint 1 with 8-byte transmit buffer Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer 1. No security feature is absolutely secure. However, Freescale s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev General Description Freescale Semiconductor

29 General Description Features System protection features: Optional computer operating properly (COP) reset Optional low-voltage detection with reset Illegal opcode detection with reset Illegal address detection with reset Low-power design (fully static with stop and wait modes) Master reset pin with internal pullup and power-on reset External interrupt pin with programmable internal pullup (IRQ) -pin quad flat pack (QFP), 28-pin small outline integrated circuit package (SOIC), 20-pin small outline integrated circuit package (SOIC), and 20-pin plastic dual in-line package (DIP) Specific features of MC68HC908JB8 in -pin are: Port B is 8 bits: PTB0 PTB7 Port C is 8 bits: PTC0 PTC7 Port D is 8 bits: PTD0 PTD7 Port E is 5 bits: PTE0 PTE; 2-channel TIM module with TCLK input option Specific features of MC68HC908JB8 in 28-pin are: Port B is not available Port C is only one bit: PTC0 Port D is only 7 bits: PTD0 PTD6 Port E is 5 bits: PTE0 PTE; 2-channel TIM module with TCLK input option Specific features of MC68HC908JB8 in 20-pin are: Port B is not available Port C is only one bit: PTC0 Port D is only one bit: PTD0/1; internal PTD0 and PTD1 pads are bonded together to a single pin, PTD0/1 Port E is only 3 bits: PTE1, PTE3, and PTE; 1-channel TIM module without TCLK input option MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor General Description 29

30 General Description Features of the CPU08 include the following: Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Efficient C language support 1. MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908JB8. Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev General Description Freescale Semiconductor

31 Freescale Semiconductor General Description 31 MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data OSC1 OSC2 (1), (2) RST (1), (3) IRQ CPU REGISTERS M68HC08 CPU ARITHMETIC/LOGIC UNIT (ALU) CONTROL AND STATUS REGISTERS 6 BYTES V DD V SS V REG (3.3 V) USER FLASH MEMORY 8,192 BYTES USER RAM 256 BYTES MONITOR ROM 976 BYTES USER FLASH VECTORS 16 BYTES OSCILLATOR SYSTEM INTEGRATION MODULE IRQ MODULE POWER INTERNAL VOLTAGE REGULATOR INTERNAL BUS KEYBOARD INTERRUPT MODULE TIMER INTERFACE MODULE BREAK MODULE LOW VOLTAGE INHIBIT MODULE POWER-ON RESET MODULE COMPUTER OPERATING PROPERLY MODULE USB MODULE USB ENDPOINT 0, 1, 2 Figure 1-1. MCU Block Diagram LS USB TRANSCEIVER (1) Pins have 5V logic. (2) Pins have integrated pullup device. (3) Pins have software configurable pullup device. () Pins are open-drain when configured as output. (5) Pins have 10mA sink capability. (6) Pins have 25mA sink capability. DDRA PTA DDRB PTB DDRC PTC DDRD PTD DDRE PTE PTA7/KBA7 (3) : PTA0/KBA0 (3) PTB7 PTB0 (3) PTC7 PTC0 (3) PTD7 PTD6 () PTD5 PTD2 () (5) () (6) PTD1 PTD0 (3) () (5) PTE/D (3) () (5) PTE3/D+ PTE2/TCH1 (3) PTE1/TCH0 (3) PTE0/TCLK (3) General Description MCU Block Diagram

32 General Description 1.5 Pin Assignments PTA2/KBA2 PTA3/KBA3 PTC7 PTC6 PTC5 PTC PTE0/TCLK PTE2/TCH1 PTA/KBA PTA5/KBA5 PTA6/KBA6 PTE3/D+ PTE/D PTC0 PTC1 PTC2 PTC3 IRQ PTD7 PTD6 PTA7/KBA OSC2 OSC1 V SS PTB3 PTB PTB5 PTB6 PTB7 RST PTA0/KBA0 PTA1/KBA1 V REG V DD PTB2 PTB1 PTB0 PTD0 PTD1 PTD2 PTD3 PTD PTE1/TCH0 PTD5 Figure Pin QFP Pin Assignments Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev General Description Freescale Semiconductor

33 General Description Pin Assignments V SS 1 28 RST OSC PTA0/KBA0 OSC PTA1/KBA1 V REG 25 PTA2/KBA2 V DD 5 2 PTA3/KBA3 PTD PTE0/TCLK Pins not available on 28-pin package: PTD PTE2/TCH1 PTB0 PTD2 PTD3 PTD PTE1/TCH0 PTE3/D+ PTE/D PTC PTA/KBA PTA5/KBA5 PTA6/KBA6 PTA7/KBA7 PTD5 PTD6 IRQ PTB1 PTC1 PTB2 PTC2 PTB3 PTC3 PTB PTC PTB5 PTC5 PTB6 PTC6 PTB7 PTC7 PTD7 Internal pads are unconnected. Figure Pin SOIC Pin Assignments V SS 1 20 RST PTD0/1 pin: PTD0 and PTD1 internal pads are bonded together to PTD0/1 pin. OSC PTA0/KBA0 Pins not available on 20-pin package: OSC PTA1/KBA1 PTB0 PTE0/TCLK V REG V DD PTD0/1 PTE1/TCH0 PTE3/D+ PTE/D PTC PTA2/KBA2 PTA3/KBA3 PTA/KBA PTA5/KBA5 PTA6/KBA6 PTA7/KBA7 IRQ PTB1 PTC1 PTB2 PTC2 PTD2 PTE2/TCH1 PTB3 PTC3 PTD3 PTB PTC PTD PTB5 PTC5 PTD5 PTB6 PTC6 PTD6 PTB7 PTC7 PTD7 Internal pads are unconnected. Figure Pin PDIP and SOIC Pin Assignments NOTE: In 20-pin package, the PTD0 and PTD1 internal pads are bonded together to PTD0/1 pin. MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor General Description 33

34 General Description Power Supply Pins (V DD, V SS ) V DD and V SS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5 shows. Place the bypass capacitors as close to the MCU power pins as possible. Use high-frequency-response ceramic capacitors for C BYPASS. C BULK are optional bulk current bypass capacitors for use in applications that require the port pins to source high current levels. MCU V DD V SS C BYPASS 0.1 F + C BULK V DD NOTE: Values shown are typical values. Figure 1-5. Power Supply Bypassing Voltage Regulator Out (V REG ) V REG is the 3.3 V output of the on-chip voltage regulator. V REG is used internally for the MCU operation and the USB data driver. It is also used to supply the voltage for the external pullup resistor required on the USB s D line. The V REG pin requires an external bulk capacitor.7 F or larger and a 0.1 F ceramic bypass capacitor as Figure 1-6 shows. Place the bypass capacitors as close to the V REG pin as possible. Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev General Description Freescale Semiconductor

35 General Description Pin Assignments V REG MCU V SS C REGBYPASS 0.1 F + C REGBULK >.7 F V REG Figure 1-6. Regulator Supply Capacitor Configuration Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit External Reset Pin (RST) A logic zero on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. The RST pin contains an internal pullup device to V DD. (See Section 8. System Integration Module (SIM).) External Interrupt Pins (IRQ, PTE/D ) IRQ is an asynchronous external interrupt pin. IRQ is also the pin to enter monitor mode. The IRQ pin contains a software configurable pullup device to V DD. PTE/D can be programmed to trigger the IRQ interrupt. (See Section 13. External Interrupt (IRQ).) MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor General Description 35

36 General Description Port A Input/Output (I/O) Pins (PTA7/KBA7 PTA0/KBA0) PTA7/KBA7 PTA0/KBA0 are general-purpose bidirectional I/O port pins. (See Section 12. Input/Output Ports (I/O).) Each pin contains a software configurable pullup device to V REG when the pin is configured as an input. (See 12.8 Port Options.) Each pin can also be programmed as an external keyboard interrupt pin. (See Section 1. Keyboard Interrupt Module (KBI).) Port B (I/O) Pins (PTB7 PTB0) PTB7 PTB0 are general-purpose bidirectional I/O port pins. Each pin contains a software configurable pullup device to V REG when the pin is configured as an input. (See 12.8 Port Options.) Port C I/O Pins (PTC7 PTC0) PTC7 PTC0 are general-purpose bidirectional I/O port pins. (See Section 12. Input/Output Ports (I/O).) Each pin contains a software configurable pullup device to V REG when the pin is configured as an input. (See 12.8 Port Options.) Port D I/O Pins (PTD7 PTD0) PTD7 PTD0 are general-purpose bidirectional I/O port pins; open-drain when configured as output. (See Section 12. Input/Output Ports (I/O).) PTD5 PTD2 are software configurable to be 10mA sink pins for direct LED connections. PTD1 PTD0 are software configurable to be 25mA sink pins for direct infrared LED connections. (See 12.8 Port Options.) Port E I/O Pins (PTE/D, PTE3/D+, PTE2/TCH1, PTE1/TCH0, PTE0/TCLK) Port E is a 5-bit special function port that shares two of its pins with the USB module and three of its pins with the timer interface module. Each PTE2 PTE0 pin contains a software configurable pullup device to V REG when the pin is configured as an input or output. Technical Data MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev General Description Freescale Semiconductor

37 General Description Pin Assignments When the USB module is disabled, the PTE and PTE3 pins are general-purpose bidirectional I/O port pins with 10mA sink capability. Each pin is open-drain when configured as an output; and each pin contains a software configurable 5k pullup to V DD when configured as an input. The PTE pin can also be enabled to trigger the IRQ interrupt. When the USB module is enabled, the PTE/D and PTE3/D+ pins become the USB module D and D+ pins. The D pin contains a software configurable 1.5k pullup to V REG. (See Section 11. Timer Interface Module (TIM), Section 9. Universal Serial Bus Module (USB) and Section 12. Input/Output Ports (I/O).) Summary of the pin functions are provided in Table 1-1. Table 1-1. Summary of Pin Functions PIN NAME PIN DESCRIPTION IN/OUT VOLTAGE LEVEL V DD Power supply. IN.0 to 5.5V V SS Power supply ground. OUT 0V V REG Regulated 3.3V output from MCU. OUT V REG (3.3V) RST Reset input; active low. With internal pullup to V DD and schmitt trigger input. IN/OUT V DD IRQ External IRQ pin; with programmable internal pullup to V DD and schmitt trigger input. IN V DD Used for mode entry selection. IN V REG to V DD +V HI OSC1 Crystal oscillator input. IN V REG OSC2 Crystal oscillator output; inverting of OSC1 signal. OUT V REG PTA0/KBA0 : PTA7/KBA7 PTB0 PTB7 8-bit general-purpose I/O port. IN/OUT V REG Pins as keyboard interrupts, KBA0 KBA7. IN V REG Each pin has programmable internal pullup to V REG when configured as input. IN V REG 8-bit general-purpose I/O port. IN/OUT V REG Each pin has programmable internal pullup to V REG when configured as input. IN V REG MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Rev. 2.3 Technical Data Freescale Semiconductor General Description 37