Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

Size: px
Start display at page:

Download "Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices"

Transcription

1 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008, ver. 1.1 Introduction LVDS is becoming the most popular differential I/O standard for high-speed transmission in the industry. The advantages of LVDS include high noise tolerance in the form of common-mode rejection, low power, and low noise generation. Improved signal to noise rejection of LVDS allows signal swing to be dropped to only a few hundred millivolts, which in turn enables faster data rates. However, many high-speed applications require more than just point-to-point communication. The desire for multipoint communication has spawned a new variant of LVDS called Bus LVDS (BLVDS), which extends the capability of LVDS to multipoint configuration such as high-speed backplane applications. There are several bus topologies for BLVDS I/O standard, such as multi-drop bus with single or double termination, and multipoint. This application note describes how to implement BLVDS interface in Cyclone III, Stratix III, and Stratix IV devices for high-performance multipoint application. Performance analysis of a multipoint application with the Cyclone III BLVDS example is also shown in this application note. The following topics are discussed in this application note: Overview of Bus LVDS BLVDS Technology in Altera Devices Power Consumption of BLVDS Design Example Performance Analysis Overview of Bus LVDS Figure 1 illustrates a typical multipoint BLVDS system which consists of a number of transmitters and receiver pairs (transceivers) that are connected to the bus. This configuration provides bidirectional half duplex communication while minimizing interconnect density. Any transceiver can assume the role of transmitter, with the remaining transceivers acting as receivers (for example, only one transmitter can be active at a time). Bus traffic control, either through protocol or hardware solution is typically required to avoid driver contention on the bus. The performance of a multipoint BLVDS is greatly affected by the capacitive loading on the bus and termination on the bus. This section explains the calculations of the effective differential impedance of a fully loaded bus (referred to as effective impedance) and the propagation delay through the bus. Other multipoint BLVDS design considerations include fail-safe biasing, connector type and connecter pinout, bus trace layout on the PCB, and driver edge rate specifications. Detailed description of each factor is beyond the scope of this application note. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

2 2 2 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Overview of Bus LVDS Figure 1. Multipoint BLVDS R T R T R T R T R T R T The effective impedance depends on the bus trace characteristic impedance Z o and capacitive loading on the bus. The connectors, the stub on the plug-in card, the packaging, and the receiver input capacitance all contribute to capacitive loading, which reduces the bus effective impedance. Equation 1 can be used to approximate the effective differential impedance of the loaded bus, Z eff. Equation 1. * Z eff = Z diff C O + C O (NC L /H) C O = Z diff * + C O C d Where Z diff (Ω) 2 * Z O = the differential characteristic impedance of the bus C O (pf/inch) = characteristic capacitance per unit length of the bus C L (pf) = capacitance of each load N = number of loads on the bus H (inch) = d * N = total length of the bus d (inch) = spacing between each plug-in card C d (pf/inch) = C L /d = distributed capacitance per unit length across the bus The increment in load capacitance or closer spacing between plug-in cards reduces the effective impedance. To optimize the system performance, it is important to select low capacitance transceiver, low capacitance connector, and keep each receiver stub length between the connector and the transceiver I/O pin as short as possible. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

3 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 3 Overview of Bus LVDS Figure 2 illustrates the effects of distributed capacitance on the normalized effective impedance. Figure 2. Normalized Effective Impedance vs. Cd/Co Z eff / Z diff C d / C o Termination is required at each end of the bus while the data flows in both directions. It is important to match the termination resistor to the effective impedance to reduce reflections and ringing on the bus. For a system with C d /C o = 3, the effective impedance is 0.5 times of Z diff. With double terminations on the bus, the driver would see an equivalent load of 0.25 times of Z diff. This reduces the signals swing and the differential noise margin across the receiver inputs if standard LVDS driver is used. BLVDS driver addresses this issue by increasing the drive current to achieve similar voltage swing at the receiver inputs. The propagation delay (t PD = Z o * C o ) is the time delay through the transmission line per unit length. It depends on the characteristic impedance and characteristic capacitance of the bus. For a loaded bus, the effective propagation delay can be calculated with Equation 2. The time for the signal to propagate from a driver A to a receiver B can then be calculated as t PDEFF * length of line between A and B. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

4 2 4 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices BLVDS Technology in Altera Devices Equation 2. t PDEFF = 1 t PD * + C d Co BLVDS Technology in Altera Devices In Cyclone III, Stratix III and Stratix IV devices, BLVDS interface is supported in any row or column I/O banks that are powered by a V CCIO of 2.5-V and is supported on all differential I/O pins, except clock pins in these I/O banks. The BLVDS transmitter uses two single-ended (SE) output buffers with the second output buffer programmed as inverted, while the BLVDS receiver uses a dedicated LVDS input buffer. In multi-drop application, either input or output buffer is used depending on if the device is intended for driver or receiver. In multipoint application, the output buffers and input buffer share the same I/O pins. An output enable (OE) signal is required to tri-state the output buffers when not transmitting or when the LVDS input buffer is receiving signal. Figure 3. BLVDS I/O Buffers in Cyclone III, Stratix III, and Stratix IV devices Output Data OE SE Output Buffer Near-End Series Termination Input Data Diff Input Buffer To FPGA Core Bi-directional Pins Output Data OE SE Output Buffer (inverted) In Cyclone III devices, there is a BLVS I/O standard to support BLVDS interface, in which 2.5-V Differential SSTL current strength is used as the BLVDS current strength. The available current strength options are 8 ma, 12 ma (default), and 16 ma. The slew rate settings are slow, medium, and fast (default), in which the corresponding settings in Quartus II software are 0, 1, and 2, respectively. On-chip series and parallel termination are not supported in a Cyclone III device BLVDS I/O standard. Pad placement rules for BLVDS I/O should follow those of LVDS I/O standard. f For more information about Cyclone III BLVDS I/O features and electrical specifications, refer to the Cyclone III Device I/O Features chapter in volume 1 of the Cyclone III Device Handbook and the DC and Switching Characteristics chapter in volume 2 of the Cyclone III Device Handbook. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

5 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 5 Power Consumption of BLVDS In Stratix III and Stratix IV devices, BLVDS interface can be implemented using 2.5-V Differential SSTL Class I or II, depending on the current strength requirement. The current strength and slew rate options are based on those available for the 2.5-V Differential SSTL I/O standard in Stratix III and Stratix IV devices. The slew rate settings in Quartus II software are 0, 1, 2, and 3 where 0 is slow slew rate and 3 is fast slew rate. On-chip series termination for the output buffer should not be enabled. External resistor at the output buffer should be used to provide impedance matching to the stub on the plug in card. On-chip differential termination for the differential input buffer should not be enabled because the bus termination is usually implemented using external termination resistors at both ends of the bus. Table 1 summarizes the I/O standards and features for implementing BLVDS in Cyclone III, Stratix III, and Stratix IV devices. Table 1. I/O standard and features support for BLVDS interface Current Strength Option (ma) Device I/O Standard V CCIO (V) Column I/O Row I/O Slew Rate Option Cyclone III BLVDS 2.5 8, 12, 16 8, 12, 16 slow, medium, fast Stratix III Differential SSTL-2 Class I or II 2.5 8, 10, 12, 16 8, 12, 16 slow, medium, medium fast, fast Stratix IV Differential SSTL-2 Class I or II 2.5 8, 10, 12, 16 8, 12, 16 slow, medium, medium fast, fast f f For more information about Stratix III 2.5-V Differential SSTL I/O standard electrical specifications and features, refer to the Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook, and the DC and Switching Characteristics chapter in volume 2 of the Stratix III Device Handbook. For more information about Stratix IV 2.5-V Differential SSTL I/O standard electrical specifications and features, refer to the Stratix IV Device I/O Features chapter in volume 1 of the Stratix IV Device Handbook, and the DC and Switching Characteristics chapter in volume 4 of the Stratix IV Device Handbook. Power Consumption of BLVDS One of the benefits of BLVDS is its low power consumption. Compared to other high performance bus technology such as GTL that uses more than 40 ma, BLVDS typically drives out current in the range of 10 ma. As an example, based on Cyclone III Early Power Estimator (EPE) estimation, for a typical power characteristics Cyclone III device in ambient temperature of 25 C, the average power consumption of a BLVDS bidirectional buffer at data rate of 50 MHz and output enabled 50% of the time is around 17 mw. Figure 4 illustrates the BLVDS I/O entry in the Cyclone III EPE. BLVDS with the same setting in Stratix III and Stratix IV devices consumes about the same amount of power. For Stratix III and Stratix IV devices, select 2.5-V Differential SSTL Class I or Class II under I/O standard column in Stratix III and Stratix IV EPE. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

6 2 6 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Design Example Prior to designing the device, you can use the Excel-based Cyclone III/Stratix III/Stratix IV EPE version 8.0 to get a magnitude estimate of the BLVDS I/O power consumption. For input and bidirectional pins, the BLVDS input buffer is always enabled. It consumes power when there is any activity on the bus (for example, other transceivers are sending and receiving data on the bus, but the Cyclone III device is not the intended recipient). If you use the Cyclone III/Stratix III/Stratix IV BLVDS as an input buffer in multi-drop or as a bidirectional buffer in multipoint application, Altera recommends entering a toggle rate that includes all the activities on the bus, not just the activities intended for the Cyclone III/Stratix III/Stratix IV BLVDS. Figure 4. Example of BLVDS I/O Data Entry in Cyclone III EPE After your design is completed, Altera recommends using the Quartus II PowerPlay Power Analyzer to perform an accurate BLVDS I/O power analysis. The PowerPlay Power Analyzer estimates power based on the specifics of the design after place-and-route is completed. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, combined with the detailed circuit models, can yield very accurate power estimates. f f For more information about Cyclone III EPE and the Quartus II PowerPlay Power Analyzer, refer to the Cyclone III Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook. For more information about Stratix III and Stratix IV EPE, refer to the Stratix III and Stratix IV Early Power Estimator User Guide. Design Example The design example illustrates how to instantiate BLVDS I/O buffer in Cyclone III, Stratix III and Stratix IV devices using ALTIOBUF megafunction in the Quartus II software. You must explicitly specify the following in your design: A differential input buffer Two SE output buffers with OE controlled by the same signal A signal splitter which connects the two SE output buffers Assign I/O standard to the bidirectional pins with the BLVDS I/O standard for Cyclone III devices, or 2.5-V Differential SSTL Class I or Class II for Stratix III or Stratix IV devices Its functions are to receive a serial data stream from the FPGA core through doutp input port, create an inverted version of the data, and transmit the data through the two SE output buffers connected to the p and n bidirectional pins. During a read operation, the differential input buffer receives the data from the bus through the p and n bidirectional pins, and sends the serial data to the FPGA core through din port. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

7 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 7 Design Example The OE port provides output enable signal from the FPGA core to enable or disable the SE output buffers. The OE signal should be kept low to tri-state the output buffers during read operation. The function of the AND gate is to stop the transmitted signal from going back into the FPGA core while the differential input buffer is always enabled. f You can download the design examples from the application notes web page at Figure 5. Design Example of a Block Diagram The block diagram of the design example in the Quartus II software is illustrated in Figure 5. Procedure f For more information about the ALTIOBUF megafunction, refer to the I/O Buffer Megafunction (ALTIOBUF) User Guide. The following steps describe the design flow for the design example. It is assumed that you are familiar with creating a new project in the Quartus II software. The illustrations in this section assumes Cyclone III device. They are applicable to Stratix III and Stratix IV devices. Make sure you select the right device. 1. To create the SE output buffers, instantiate ALTIOBUF Megafunction using MegaWizard Plug-in Manager. Configure the module as an output buffer, enter 1 for the What is the number of buffers to be instantiated box, and check the Use output enable port(s) option as shown in Figure 6. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

8 2 8 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Design Example Figure 6. Configuring BLVDS SE Output Buffer 2. To create the differential input buffer, instantiate ALTIOBUF megafunction. Configure the module as an input buffer, enter 1 for the What is the number of buffers to be instantiated box, and check the use differential model option as shown in Figure 7. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

9 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 9 Design Example Figure 7. Configuring BLVDS Differential Input Buffer 3. Instantiate the signal splitter function. To do so, in the Edit menu, select Insert Symbol. Select pdo symbol under Project directory. This is a custom function that comes with the design example. By using this function, the inversion of the data input from the core is implemented in the IO element to ensure minimum skew between the p and n output signals. 4. Connect the modules and the input and output ports as shown in Figure In Assignment Editor, assign BLVDS I/O standard to the bidirectional p and n pins for Cyclone III devices as shown in Figure 8. For Stratix III or Stratix IV devices, assign Differential 2.5-V SSTL Class I or II. You can also set the current strength and slew rate options. Otherwise, the Quartus II software assumes the default settings. Figure 8. BLVDS I/O Assignment in Quartus III Assignment Editor 6. Compile and perform timing simulation using the vector waveform file (BLVDS.vwf). Figure 9 illustrates the simulation waveforms. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

10 2 10 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Figure 9. Example of Timing Simulation Results Performance Analysis Performance analysis of a multipoint BLVDS based on the Cyclone III BLVDS input output buffer information specification (IBIS) model simulation in HyperLynx is presented in this section. The analyses demonstrate the impacts of bus termination, loading, driver and receiver characteristics, and locations on the performance of the system. You should use Stratix III or Stratix IV 2.5-V Differential SSTL IBIS model for the simulation if you use Stratix III or Stratix IV devices. f System Setup You can download the Cyclone III and Stratix III IBIS models at Figure 10 illustrates the schematic of a multipoint topology loaded with ten Cyclone III BLVDS transceivers (named U1, U2, U10). The bus transmission line is assumed to be a stripline of characteristic impedance of, characteristic capacitance of 3.6 pf per inch and length 10 inches. The bus differential characteristic impedance is approximately 100 Ω. The spacing between each transceiver is 1 inch. The bus is terminated at both ends with termination resistor R T. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

11 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 11 Performance Analysis Figure 10. Multipoint BLVDS with Cyclone III BLVDS Transceivers 3.3 V 3.3 V 130 KΩ 130 K Ω R T R T 100 KΩ GND 100 K Ω GND OE Cyclone III Device OE Cyclone III Device OE Cyclone III Device R S R S R S R S R S R S U1 U2 U10 Output data Input data Output data Input data Output data Input data Fail-safe biasing resistors of 130 kω and 100 kω are used to pull the bus to a known state when all the drivers are tri-stated, removed or powered off. The magnitude of the fail-safe resistors should be one to two orders higher than R T to prevent excessive loading to the driver and waveform distortion. The mid-point of the fail-safe bias should be close to the offset voltage of the driver (+1.25-V) to prevent a large common-mode shift from occurring between active and tri-state bus conditions. The bus can be powered off by common 2.5-V or 3.3-V power supplies. The Cyclone III BLVDS transceivers assume default 12 ma drive strength and slow slew rate settings, unless otherwise stated. The pin capacitance of each transceiver is 6 pf. The stub on each BLVDS transceiver is a 1-inch microstrip of characteristic impedance of and characteristic capacitance of 3 pf per inch. The capacitance of the connection (connector, pad, and via in PCB) of each transceiver to the bus is assumed to be 2 pf. Hence, the total capacitance of each load is approximately 11 pf. For 1-inch load spacing, the distributed capacitance is equal to 11 pf per inch. An impedance matching resistor R S is placed at the output of each transceiver to reduce reflection caused by the stubs, and also to attenuate the signals coming out of the driver. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

12 2 12 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Bus Termination Substituting the bus characteristic capacitance and the distributed capacitance per unit length of the above setup into Equation 1, the effective impedance of the fully loaded bus is 52 Ω. R T should be matched to 52 Ω for optimum signal integrity. Figure 11 to Figure 14 illustrate the effects of matched-, under-,and over-termination on the differential waveform (V ID ) at the receiver input pins. The data rate is 100 Mbps. For Figure 11 and Figure 12, U1 acts as the transmitter and U2 to U10 are the receivers, whereas for Figure 13 and Figure 14, U5 is the transmitter and the rest are receivers. For both cases, under-termination (R T = 25 Ω) results in reflections and the noise margin is greatly reduced, in some case even violated the receiver threshold, V TH = ± 100 mv. When R T is changed to, there is a substantial noise margin with respect to V TH and the reflection is negligible. Figure 11. Effect of Bus Termination (Driver in U1, Receiver in U2) RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.2 V ID (V) Time (ns) Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

13 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 13 Performance Analysis Figure 12. Effect of Bus Termination (Driver in U1, Receiver in U10) RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.2 V ID (V) Time (ns) November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

14 2 14 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Figure 13. Effect of Bus Termination (Driver in U5, Receiver in U6) RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.2 V ID (V) Time (ns) Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

15 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 15 Performance Analysis Figure 14. Effect of Bus Termination (Driver in U5, Receiver in U10) RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.2 V ID (V) Time (ns) The relative position of the driver and receiver on the bus also affects the received signal quality. It is observed that the nearest receiver to the driver experiences worst transmission line effect because at this location, the edge rate is the fastest. This is made worse when the driver is located at the middle of the bus. For example, compare Figure 11 and Figure 13, V ID at receiver U6 (driver at U5) shows larger ringing than that at receiver U2 (driver at U1). On the other hand, edge rate is slowed down when receiver is located further away from the driver. The largest rise time recorded is 1.14 ns with the driver located at one end of the bus (U1) and the receiver at the other end (U10) of the bus. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

16 2 16 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Stub Length Figure 15 compares the V ID at U10 when stub length is increased from 1 inch to 2 inches and the driver is at U1. Longer stub length not only increases the flight time from the driver to the receiver, but also results in larger load capacitance, which causes larger reflection. Figure 15. Effect of Increasing Stub Length (Driver in U1, Receiver in U10) inch stub 2 inch stub V ID (V) Time (ns) Stub Termination It is important to match the driver impedance to the stub characteristic impedance. Placing a series termination resistor R S at the driver output greatly reduces adverse transmission line effect caused by long stub and fast edge rates. In addition, R S can be changed to attenuate the V ID to meet the specification of the receiver. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

17 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 17 Performance Analysis Figure 16 compares the V ID at U2 and U10 when U1 is transmitting. Figure 16. Effect of Stub Termination (Driver in U1, Receiver in U2 and U10) RS=50 Ohm; U2 RS=50 Ohm; U10 RS=0 Ohm; U2 RS=0 Ohm; U V ID (v) Time (ns) Driver Slew Rate Figure 17 shows the driver slew rate effect. Comparison is made between slow and fast slew rate with 12 ma drive strength. The driver is at U1 and the differential waveforms at U2 and U10 are examined. Fast slew rate helps to improve rise time, especially at the receiver furthest from the driver. However, faster slew rate also magnifies ringing due to reflection. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

18 2 18 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Figure 17. Effect of Driver Edge Rate (Driver in U1, Receiver in U2 and U10) 0.6 fast; U2 slow; U2 fast; U slow; U V ID (V) Time (ns) Overall System Performance The highest data rate supported by a multipoint BLVDS is determined by looking at the eye diagram at the furthest receiver from a driver. At this location, the edge rate of the transmitted signal has slowed the most and affects the eye opening. Even though the quality of the received signal and the noise margin goal depend on the applications, the wider the eye opening the better. However, the receiver nearest to the driver should also be checked because the transmission line effects tend to be worse if the receiver is located closer to the driver. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

19 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 19 Summary Figure 18 illustrates the eye diagrams at U2 (red curve) and U10 (blue curve) for a data rate at 400 Mbps. Random jitter of 1% unit interval is assumed in the simulation. The driver is at U1 with default current strength and slew rate settings. The bus is fully loaded with optimum R T =. It is seen that the smallest eye opening is at U10, which is furthest from U1. The eye height sampled at 0.5 unit interval is 692 mv and 543 mv for U2 and U10, respectively. There is substantial noise margin with respect to V TH = ±100mV for both cases. Figure 18. Eye Diagram at 400 Mbps (Driver in U1, Receiver in U2 and U10) Summary Multipoint BLVDS offers an efficient solution for multipoint backplane applications. A good multipoint design should consider the capacitive load and termination on the bus to obtain better signal integrity. Minimizing the load capacitance can be achieved by selecting transceiver with low pin capacitance, connector with low capacitance and keeping the stub length short. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices

20 2 20 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Referenced Documents Cyclone III, Stratix III and Stratix IV devices provide low cost, low power solution to the implementation of BLVDS interface in multipoint backplane applications. In addition, the programmable features drive strength and slew rate options enable system designers to customize their multipoint system for maximum performance. The designer should perform simulation or measurement based on their specific system setup and application to determine the maximum data rate supported. Referenced Documents This application note references the following documents: Cyclone III Device I/O Features chapter in volume 1 of the Cyclone III Device Handbook DC and Switching Characteristics chapter in volume 2 of the Cyclone III Device Handbook Cyclone III Early Power Estimator User Guide PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook I/O Buffer Megafunction (ALTIOBUF) User Guide Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook DC and Switching Characteristics chapter in volume 2 of the Stratix III Device Handbook Stratix IV Device I/O Features chapter in volume 1 of the Stratix IV Device Handbook DC and Switching Characteristics chapter in volume 2 of the Stratix IV Device Handbook Stratix III and Stratix IV Early Power Estimator User Guide Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation

21 Document Revision History Table 2. Document Revision History Table 2 shows the revision history for this application note. Date and Document Version Changes Made Summary of Changes November 2008 Updated to new template v1.1 Updated Introduction chapter July 2008 v1.0 Updated BLVDS Technology in Altera Devices chapter Updated Power Consumption of BLVDS chapter Updated Design Example chapter Replaced Figure 5 on page 7 Updated Procedure chapter Updated Performance Analysis chapter Updated Bus Termination chapter Updated Summary chapter Initial release 101 Innovation Drive San Jose, CA Technical Support Copyright November Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems

Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems Interfacing Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems April 2008 AN-447-1.1 Introduction Altera Cyclone III devices are compatible and support 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards. This application

More information

Implementing LVDS in Cyclone Devices

Implementing LVDS in Cyclone Devices Implementing LVDS in Cyclone Devices March 2003, ver. 1.1 Application Note 254 Introduction Preliminary Information From high-speed backplane applications to high-end switch boxes, LVDS is the technology

More information

QDR II SRAM Board Design Guidelines

QDR II SRAM Board Design Guidelines 8 emi_dg_007 Subscribe The following topics provide guidelines for you to improve your system's signal integrity and layout guidelines to help successfully implement a QDR II or QDR II+ SRAM interface

More information

Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs

Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs White Paper Introduction Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs Signal integrity has become a critical issue in the design of high-speed systems. Poor signal integrity can mean

More information

AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/ LVCMOS I/O Systems

AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/ LVCMOS I/O Systems AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/ LVCMOS I/O Systems Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents Interfacing Intel FPGA Devices with 3.3/3.0/2.5

More information

Stratix II FPGA Family

Stratix II FPGA Family October 2008, ver. 2.1 Errata Sheet Introduction This errata sheet provides updated information on Stratix II devices. This document addresses known device issues and includes methods to work around the

More information

MIPI D-PHY Solution with Passive Resistor Networks in Altera Low Cost FPGA

MIPI D-PHY Solution with Passive Resistor Networks in Altera Low Cost FPGA 2015.12.23 MIPI D-PHY Solution with Passive Resistor Networks in Altera Low Cost FPGA AN-754 Subscribe Introduction to MIPI D-PHY The Mobile Industry Processor Interface (MIPI) is an industry consortium

More information

AN 523: Cyclone III Devices Configuration Interface Guidelines with EPCS Devices

AN 523: Cyclone III Devices Configuration Interface Guidelines with EPCS Devices AN 523: Devices Configuration Interface Guidelines with Devices February 2014 AN-523-1.3 Introduction This application note provides the guidelines to Cyclone III family devices ( and LS devices) interfacing

More information

MAX 10 FPGA Signal Integrity Design Guidelines

MAX 10 FPGA Signal Integrity Design Guidelines 2014.12.15 M10-SIDG Subscribe Today s complex FPGA system design is incomplete without addressing the integrity of signals coming in to and out of the FPGA. Simultaneous switching noise (SSN) often leads

More information

Multi-Drop LVDS with Virtex-E FPGAs

Multi-Drop LVDS with Virtex-E FPGAs Multi-Drop LVDS with Virtex-E FPGAs XAPP231 (Version 1.0) September 23, 1999 Application Note: Jon Brunetti & Brian Von Herzen Summary Introduction Multi-Drop LVDS Circuits This application note describes

More information

6. I/O Features in Arria II Devices

6. I/O Features in Arria II Devices 6. I/O Features in Arria II Devices December 2011 AIIGX51006-4.2 AIIGX51006-4.2 This chapter describes how Arria II devices provide I/O capabilities that allow you to work in compliance with current and

More information

Stratix vs. Virtex-II Pro FPGA Performance Analysis

Stratix vs. Virtex-II Pro FPGA Performance Analysis White Paper Stratix vs. Virtex-II Pro FPGA Performance Analysis The Stratix TM and Stratix II architecture provides outstanding performance for the high performance design segment, providing clear performance

More information

Implementing OCT Calibration in Stratix III Devices

Implementing OCT Calibration in Stratix III Devices Implementing OCT Calibration in Stratix III Devices October 2007, version 1.0 Application Note 465 Introduction Use of the on-chip termination (OCT) scheme in Stratix III devices eliminates the need for

More information

Low Power Design Techniques

Low Power Design Techniques Low Power Design Techniques August 2005, ver 1.0 Application Note 401 Introduction This application note provides low-power logic design techniques for Stratix II and Cyclone II devices. These devices

More information

AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current

AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current January 2009 AN-547-10 Introduction To save power, the MAX II CPLD can be completely powered down into hibernation mode

More information

Intel Stratix 10 General Purpose I/O User Guide

Intel Stratix 10 General Purpose I/O User Guide Intel Stratix 10 General Purpose I/O User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel Stratix 10 I/O

More information

Intel Stratix 10 General Purpose I/O User Guide

Intel Stratix 10 General Purpose I/O User Guide Intel Stratix 10 General Purpose I/O User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix 10 I/O

More information

Stratix FPGA Family. Table 1 shows these issues and which Stratix devices each issue affects. Table 1. Stratix Family Issues (Part 1 of 2)

Stratix FPGA Family. Table 1 shows these issues and which Stratix devices each issue affects. Table 1. Stratix Family Issues (Part 1 of 2) January 2007, ver. 3.1 Errata Sheet This errata sheet provides updated information on Stratix devices. This document addresses known issues and includes methods to work around the issues. Table 1 shows

More information

PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs

PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: QII v9.0 SP2 Document Version: 2.0 Document Date: June 2009 UG-01013-2.0

More information

Enhanced Configuration Devices

Enhanced Configuration Devices Enhanced Configuration Devices October 2007, Version 1.2 Errata Sheet Introduction Intel-Flash- Based EPC Device Protection f This errata sheet provides updated information on enhanced configuration devices

More information

FPGA Power Management and Modeling Techniques

FPGA Power Management and Modeling Techniques FPGA Power Management and Modeling Techniques WP-01044-2.0 White Paper This white paper discusses the major challenges associated with accurately predicting power consumption in FPGAs, namely, obtaining

More information

AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs

AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents AN 754: MIPI D-PHY Solution with Passive

More information

Design Guidelines for Intel FPGA DisplayPort Interface

Design Guidelines for Intel FPGA DisplayPort Interface 2018-01-22 Design Guidelines for Intel FPGA DisplayPort Interface AN-745 Subscribe The design guidelines help you implement the Intel FPGA DisplayPort IP core using Intel FPGA devices. These guidelines

More information

9. Hot Socketing and Power-On Reset in Stratix IV Devices

9. Hot Socketing and Power-On Reset in Stratix IV Devices February 2011 SIV51009-3.2 9. Hot Socketing and Power-On Reset in Stratix IV Devices SIV51009-3.2 This chapter describes hot-socketing specifications, power-on reset (POR) requirements, and their implementation

More information

MAX 10 General Purpose I/O User Guide

MAX 10 General Purpose I/O User Guide MAX 10 General Purpose I/O User Guide Subscribe UG-M10GPIO 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents MAX 10 I/O Overview... 1-1 MAX 10 Devices I/O Resources Per Package...1-1

More information

4. Hot Socketing and Power-On Reset in MAX V Devices

4. Hot Socketing and Power-On Reset in MAX V Devices December 2010 MV51004-1.0 4. Hot Socketing and Power-On Reset in MAX V Devices MV51004-1.0 This chapter provides information about hot-socketing specifications, power-on reset (POR) requirements, and their

More information

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: 8.1 Document Version: 4.0 Document Date: November 2008 UG-MF9504-4.0

More information

6. I/O Features in Stratix IV Devices

6. I/O Features in Stratix IV Devices 6. I/O Features in Stratix IV Devices September 2012 SIV51006-3.4 SIV51006-3.4 This chapter describes how Stratix IV devices provide I/O capabilities that allow you to work in compliance with current and

More information

High-Performance FPGA PLL Analysis with TimeQuest

High-Performance FPGA PLL Analysis with TimeQuest High-Performance FPGA PLL Analysis with TimeQuest August 2007, ver. 1.0 Application Note 471 Introduction f Phase-locked loops (PLLs) provide robust clock management and clock synthesis capabilities for

More information

Intel MAX 10 General Purpose I/O User Guide

Intel MAX 10 General Purpose I/O User Guide Intel MAX 10 General Purpose I/O User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel MAX 10 I/O Overview...3

More information

Enhanced Configuration Devices

Enhanced Configuration Devices Enhanced Configuration Devices July 2008, Version 1.3 Errata Sheet Introduction Intel-Flash- Based EPC Device Protection f This errata sheet provides updated information on enhanced configuration devices

More information

Using Flexible-LVDS Circuitry in Mercury Devices

Using Flexible-LVDS Circuitry in Mercury Devices Using Flexible-LVDS Circuitry in Mercury Devices November 2002, ver. 1.1 Application Note 186 Introduction With the ever increasing demand for high bandwidth and low power consumption in the telecommunications

More information

Intel MAX 10 High-Speed LVDS I/O User Guide

Intel MAX 10 High-Speed LVDS I/O User Guide Intel MAX 10 High-Speed LVDS I/O User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel MAX 10 High-Speed LVDS

More information

Transient Voltage Protection for Stratix GX Devices

Transient Voltage Protection for Stratix GX Devices White Paper Devices Introduction This document addresses the phenomenon known as transient voltage in a system using Stratix GX devices. Hot socketing is identified as the major source of transient voltage.

More information

POS-PHY Level 4 MegaCore Function

POS-PHY Level 4 MegaCore Function POS-PHY Level 4 MegaCore Function November 2004, MegaCore Version 2.2.2 Errata Sheet Introduction This document addresses known errata and documentation changes for version v2.2.2 of the POS-PHY Level

More information

White Paper Performing Equivalent Timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace

White Paper Performing Equivalent Timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace Introduction White Paper Between Altera Classic Timing Analyzer and Xilinx Trace Most hardware designers who are qualifying FPGA performance normally run bake-off -style software benchmark comparisons

More information

ByteBlaster II Download Cable User Guide

ByteBlaster II Download Cable User Guide ByteBlaster II Download Cable User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com UG-BBII81204-1.1 P25-10324-00 Document Version: 1.1 Document Date: December 2004 Copyright

More information

AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices

AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 AN-610-1.0 This application note describes how to implement deterministic latency for Common Public Radio

More information

White Paper Using the MAX II altufm Megafunction I 2 C Interface

White Paper Using the MAX II altufm Megafunction I 2 C Interface White Paper Using the MAX II altufm Megafunction I 2 C Interface Introduction Inter-Integrated Circuit (I 2 C) is a bidirectional two-wire interface protocol, requiring only two bus lines; a serial data/address

More information

Using I/O Standards in the Quartus Software

Using I/O Standards in the Quartus Software White Paper Using I/O Standards in the Quartus Software This document shows how to implement and view the selectable I/O standards for APEX TM 20KE devices in the Quartus TM software and give placement

More information

Using Flexible-LVDS I/O Pins in

Using Flexible-LVDS I/O Pins in Using Flexible-LVDS I/O Pins in APEX II Devices August 2002, ver. 1.1 Application Note 167 Introduction Recent expansion in the telecommunications market and growth in Internet use have created a demand

More information

Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices

Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices November 2005, ver. 3.1 Application Note 325 Introduction Reduced latency DRAM II (RLDRAM II) is a DRAM-based point-to-point memory device

More information

7. High-Speed Differential Interfaces in the Cyclone III Device Family

7. High-Speed Differential Interfaces in the Cyclone III Device Family December 2011 CIII51008-4.0 7. High-Speed Dierential Interaces in the Cyclone III Device Family CIII51008-4.0 This chapter describes the high-speed dierential I/O eatures and resources in the Cyclone III

More information

ALTDQ_DQS2 Megafunction User Guide

ALTDQ_DQS2 Megafunction User Guide ALTDQ_DQS2 Megafunction ALTDQ_DQS2 Megafunction 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01089-2.2 Feedback Subscribe 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE,

More information

Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander

Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander March 2004, ver 2.0 Application Note 265 Introduction Advantages of Using MAX II & MAX 3000A Devices Many microcontroller and microprocessors

More information

8. Selectable I/O Standards in Arria GX Devices

8. Selectable I/O Standards in Arria GX Devices 8. Selectable I/O Standards in Arria GX Devices AGX52008-1.2 Introduction This chapter provides guidelines for using industry I/O standards in Arria GX devices, including: I/O features I/O standards External

More information

USB BitJetLite Download Cable

USB BitJetLite Download Cable USB BitJetLite Download Cable User Guide, Inc. (USA) 14100 Murphy Avenue San Martin, CA 95046 (408) 852-0067 http://www.slscorp.com Product Version: 1.0 Document Version: 1.0 Document Date: Copyright 2010,.All

More information

Arria II GX FPGA Development Board

Arria II GX FPGA Development Board Arria II GX FPGA Development Board DDR2 SODIMM Interface 2011 Help Document DDR2 SODIMM Interface Measurements were made on the DDR2 SODIMM interface using the Board Test System user interface. The Address,

More information

Section 3 - Backplane Architecture Backplane Designer s Guide

Section 3 - Backplane Architecture Backplane Designer s Guide Section 3 - Backplane Architecture Backplane Designer s Guide March 2002 Revised March 2002 The primary criteria for backplane design are low cost, high speed, and high reliability. To attain these often-conflicting

More information

DDR and DDR2 SDRAM Controller Compiler User Guide

DDR and DDR2 SDRAM Controller Compiler User Guide DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Operations Part Number Compiler Version: 8.1 Document Date: November 2008 Copyright 2008 Altera

More information

Designing RGMII Interface with FPGA and HardCopy Devices

Designing RGMII Interface with FPGA and HardCopy Devices Designing RGMII Interface with FPGA and HardCopy Devices November 2007, ver. 1.0 Application Note 477 Introduction The Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the IEEE

More information

Implementing LED Drivers in MAX and MAX II Devices. Introduction. Commercial LED Driver Chips

Implementing LED Drivers in MAX and MAX II Devices. Introduction. Commercial LED Driver Chips Implementing LE rivers in MAX and MAX II evices October 2008 AN-286-2.3 Introduction iscrete LE driver chips are common on many system boards. Altera MAX II, MAX 7000B, MAX 7000A, MAX 3000A, and MAX 7000S

More information

Arria II GX FPGA Development Board

Arria II GX FPGA Development Board Arria II GX FPGA Development Board Overview 2011 Signal Integrity Report Introduction Signal Integrity Analysis The ArriaII GX development kit board has several high speed interfaces. Each of these interfaces

More information

Introduction. Synchronous vs. Asynchronous Memory. Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs

Introduction. Synchronous vs. Asynchronous Memory. Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs Converting from synchronous to Synchronous for Stratix & Stratix GX esigns November 2002, ver. 2.0 pplication Note 210 Introduction The Stratix TM and Stratix GX device families provide a unique memory

More information

8. Migrating Stratix II Device Resources to HardCopy II Devices

8. Migrating Stratix II Device Resources to HardCopy II Devices 8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy II devices and Stratix II devices are both manufactured on a 1.2-V, 90-nm process technology and

More information

Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide

Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide 11 Innovation Drive San Jose, CA 95134 www.altera.com Software Version 8. Document Version: 2. Document Date: June 28

More information

Using the Nios Development Board Configuration Controller Reference Designs

Using the Nios Development Board Configuration Controller Reference Designs Using the Nios Development Board Controller Reference Designs July 2006 - ver 1.1 Application Note 346 Introduction Many modern embedded systems utilize flash memory to store processor configuration information

More information

ByteBlaster II Parallel Port Download Cable

ByteBlaster II Parallel Port Download Cable ByteBlaster II Parallel Port Download Cable December 2002, Version 1.0 Data Sheet Features Allows PC users to perform the following functions: Program MAX 9000, MAX 7000S, MAX 7000AE, MAX 7000B, MAX 3000A,

More information

White Paper Compromises of Using a 10-Gbps Transceiver at Other Data Rates

White Paper Compromises of Using a 10-Gbps Transceiver at Other Data Rates White Paper Compromises of Using a 10-Gbps Transceiver at Other Data Rates Introduction Many applications and designs are adopting clock data recovery-based (CDR) transceivers for interconnect data transfer.

More information

9. Reviewing Printed Circuit Board Schematics with the Quartus II Software

9. Reviewing Printed Circuit Board Schematics with the Quartus II Software November 2012 QII52019-12.1.0 9. Reviewing Printed Circuit Board Schematics with the Quartus II Sotware QII52019-12.1.0 This chapter provides guidelines or reviewing printed circuit board (PCB) schematics

More information

DSP Development Kit, Stratix II Edition

DSP Development Kit, Stratix II Edition DSP Development Kit, Stratix II Edition August 2005, Development Kit version 1.1.0 Errata Sheet This document addresses known errata and documentation changes the DSP Development Kit, Stratix II Edition

More information

Nios II Embedded Design Suite 6.1 Release Notes

Nios II Embedded Design Suite 6.1 Release Notes December 2006, Version 6.1 Release Notes This document lists the release notes for the Nios II Embedded Design Suite (EDS) version 6.1. Table of Contents: New Features & Enhancements...2 Device & Host

More information

LVDS applications, testing, and performance evaluation expand.

LVDS applications, testing, and performance evaluation expand. Stephen Kempainen, National Semiconductor Low Voltage Differential Signaling (LVDS), Part 2 LVDS applications, testing, and performance evaluation expand. Buses and Backplanes D Multi-drop D LVDS is a

More information

2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features

2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential

More information

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Description. Features. Block Diagram DATASHEET

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Description. Features. Block Diagram DATASHEET DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs

More information

Using the Serial FlashLoader With the Quartus II Software

Using the Serial FlashLoader With the Quartus II Software Using the Serial FlashLoader With the Quartus II Software July 2006, ver. 3.0 Application Note 370 Introduction Using the Joint Test Action Group () interface, the Altera Serial FlashLoader (SFL) is the

More information

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Features

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Features DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) input pairs and

More information

National Semiconductor Application Note 1115 John Goldie July FIGURE 2. Device Configurations

National Semiconductor Application Note 1115 John Goldie July FIGURE 2. Device Configurations DS92LV010A Bus LVDS Transceiver Ushers in a New Era of High-Performance Backplane Design Bus LVDS (BLVDS) is a new family of bus interface circuits invented by based on LVDS technology. This family of

More information

DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description The DS90LV004 is a four channel 1.5 Gbps LVDS buffer/repeater. High speed data paths and flow-through pinout minimize internal

More information

Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public

Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary

More information

Recommended Protocol Configurations for Stratix IV GX FPGAs

Recommended Protocol Configurations for Stratix IV GX FPGAs Recommended Protocol s for Stratix IV GX FPGAs AN-577-3.0 Application Note The architecture of the Altera Stratix IV GX FPGA is designed to accommodate the widest range of protocol standards spread over

More information

Intel Quartus Prime Standard Edition User Guide

Intel Quartus Prime Standard Edition User Guide Intel Quartus Prime Standard Edition User Guide PCB Design Tools Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Simultaneous Switching

More information

DDR & DDR2 SDRAM Controller Compiler

DDR & DDR2 SDRAM Controller Compiler DDR & DDR2 SDRAM Controller Compiler August 2007, Compiler Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version

More information

System Debugging Tools Overview

System Debugging Tools Overview 9 QII53027 Subscribe About Altera System Debugging Tools The Altera system debugging tools help you verify your FPGA designs. As your product requirements continue to increase in complexity, the time you

More information

Power Optimization in FPGA Designs

Power Optimization in FPGA Designs Mouzam Khan Altera Corporation mkhan@altera.com ABSTRACT IC designers today are facing continuous challenges in balancing design performance and power consumption. This task is becoming more critical as

More information

Fairchild Semiconductor Application Note December 2000 Revised June What is LVDS? FIGURE 2. Driver/Receiver Schematic

Fairchild Semiconductor Application Note December 2000 Revised June What is LVDS? FIGURE 2. Driver/Receiver Schematic LVDS Fundamentals Introduction With the recent developments in the communications market, the demand for throughput is becoming increasingly more crucial. Although older differential technologies provide

More information

Dynamic Reconfiguration of PMA Controls in Stratix V Devices

Dynamic Reconfiguration of PMA Controls in Stratix V Devices Dynamic Reconfiguration of PMA Controls in Stratix V Devices AN-645-1.0 Application Note This application note describes how to use the transceiver reconfiguration controller to dynamically reconfigure

More information

Design Guidelines for 100 Gbps - CFP2 Interface

Design Guidelines for 100 Gbps - CFP2 Interface 2014.01.16 AN-684 Subscribe This document shows an example layout design that implements a 4 x 25/28 Gbps CFP2 module interface that meets the insertion and return loss mask requirements proposed in the

More information

RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications. Revision Date: March 18, 2005

RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications. Revision Date: March 18, 2005 RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications Revision Date: March 18, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed in conjunction with

More information

Simulating the ASMI Block in Your Design

Simulating the ASMI Block in Your Design 2015.08.03 AN-720 Subscribe Supported Devices Overview You can simulate the ASMI block in your design for the following devices: Arria V, Arria V GZ, Arria 10 Cyclone V Stratix V In the Quartus II software,

More information

White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices

White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices Introduction White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices One of the challenges faced by engineers designing communications equipment is that memory devices

More information

5. Using MAX V Devices in Multi-Voltage Systems

5. Using MAX V Devices in Multi-Voltage Systems June 2017 MV51005-2017.06.16 5. Using MAX V Devices in Multi-Voltage Systems MV51005-2017.06.16 This chapter describes how to implement Altera devices in multi-voltage systems without damaging the device

More information

4. Hot Socketing & Power-On Reset

4. Hot Socketing & Power-On Reset 4. Hot Socketing & Power-On Reset CII51004-3.1 Introduction Cyclone II devices offer hot socketing (also known as hot plug-in, hot insertion, or hot swap) and power sequencing support without the use of

More information

Increase Current Drive Using LVDS

Increase Current Drive Using LVDS Application Report SLLA100 May 2001 Increase Current Drive Using LVDS Steve Corrigan DSBU LVDS ABSTRACT The most common configuration for an LVDS connection is the one-way transmission topology. A single

More information

Errata Sheet for Cyclone IV Devices

Errata Sheet for Cyclone IV Devices Errata Sheet for Cyclone IV Devices ES-01027-2.3 Errata Sheet This errata sheet provides updated information on known device issues affecting Cyclone IV devices. Table 1 lists specific Cyclone IV issues,

More information

Programmable CMOS LVDS Transmitter/Receiver

Programmable CMOS LVDS Transmitter/Receiver SPECIFICATION 1. FEATURES Technology TSMC 0.13um CMOS 3.3 V analog power supply 1.2 V digital power supply 1.2V CMOS input and output logic signals 8-step (3-bit) adjustable transmitter output current

More information

Q Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height

Q Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height Application Note Q Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height Copyrights and Trademarks Copyright 2004 Samtec, Inc. Developed in conjunction with Teraspeed Consulting

More information

4. Selectable I/O Standards in Stratix II and Stratix II GX Devices

4. Selectable I/O Standards in Stratix II and Stratix II GX Devices 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices,

More information

Increasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface

Increasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface Increasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface Steven Strell Senior Applications Engineer, Altera Corporation (408) 544-7624 sstrell@altera.com 1 Abstract Today s high-speed,

More information

13. Power Management in Stratix IV Devices

13. Power Management in Stratix IV Devices February 2011 SIV51013-3.2 13. Power Management in Stratix IV Devices SIV51013-3.2 This chapter describes power management in Stratix IV devices. Stratix IV devices oer programmable power technology options

More information

Logic Optimization Techniques for Multiplexers

Logic Optimization Techniques for Multiplexers Logic Optimiation Techniques for Multiplexers Jennifer Stephenson, Applications Engineering Paul Metgen, Software Engineering Altera Corporation 1 Abstract To drive down the cost of today s highly complex

More information

Intel Stratix 10 Analog to Digital Converter User Guide

Intel Stratix 10 Analog to Digital Converter User Guide Intel Stratix 10 Analog to Digital Converter User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix

More information

Intel Cyclone 10 LP Device Family Pin Connection Guidelines

Intel Cyclone 10 LP Device Family Pin Connection Guidelines Intel Cyclone 10 LP Device Family Pin Connection Guidelines Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents... 3 Intel Cyclone 10 LP Pin Connection Guidelines...4 Clock and

More information

On-Chip Memory Implementations

On-Chip Memory Implementations On-Chip Memory Implementations Using Cyclone Memory Blocks March 2003, ver. 1.1 Application Note 252 Introduction Cyclone devices feature embedded memory blocks that can be easily configured to support

More information

Using DCFIFO for Data Transfer between Asynchronous Clock Domains

Using DCFIFO for Data Transfer between Asynchronous Clock Domains Using DCFIFO for Data Transfer between Asynchronous Clock Domains, version 1.0 Application Note 473 Introduction In the design world, there are very few designs with a single clock domain. With increasingly

More information

PowerPlay Early Power Estimator User Guide

PowerPlay Early Power Estimator User Guide PowerPlay Early Power Estimator 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01070-7.1 Feedback Subscribe 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX,

More information

DDR & DDR2 SDRAM Controller Compiler

DDR & DDR2 SDRAM Controller Compiler DDR & DDR2 SDRAM Controller Compiler march 2007, Compiler Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 7.0.

More information

Features. Applications

Features. Applications HCSL-Compatible Clock Generator for PCI Express General Description The is the smallest, high performance, lowest power, 2 differential output clock IC available for HCSL timing applications. offers -130dBc

More information

Technical Note. ONFI 4.0 Design Guide. Introduction. TN-29-83: ONFI 4.0 Design Guide. Introduction

Technical Note. ONFI 4.0 Design Guide. Introduction. TN-29-83: ONFI 4.0 Design Guide. Introduction Introduction Technical Note ONFI 4.0 Design Guide Introduction The ONFI 4.0 specification enables high data rates of 667 MT/s and 800 MT/s. These high data rates, along with lower input/output capacitance,

More information

Design Verification Using the SignalTap II Embedded

Design Verification Using the SignalTap II Embedded Design Verification Using the SignalTap II Embedded Logic Analyzer January 2003, ver. 1.0 Application Note 280 Introduction The SignalTap II embedded logic analyzer, available exclusively in the Altera

More information