PRODUCT PREVIEW TNETV1050 IP PHONE PROCESSOR. description

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1 C55x DSP Operating at 125 MHz, Providing up to 250 MIPS MIPS32 4KEc 32-Bit RISC Processor, Operating at 165 MHz, Providing up to 223 Dhrystone MIPS On-Chip Peripherals Include: External Memory Interface (EMIF) Universal 4-Channel DMA Controller 52 General-Purpose I/O Terminals 8 8 Keypad Interface Universal Asynchronous Receiver/Transmitter (UART) Two VLYNQ Serial Communication Ports Sequencer-Based Serial Port USB1.1 Host or Device Controller With Compliant PHY Liquid Crystal Display (LCD) Controller description Ethernet Subsystem Two Integrated 10/100 Base-T Ethernet MAC/PHY Ports Integrated 3-Port Wire Speed Layer-2 Ethernet Switch Telephony Subsystem Integrated Dual-Channel Audio Codec With Programmable 8/16 KBPS Sample Rate Dedicated Multichannel Buffered Serial Port (McBSP) for Internal Audio Codec Generic McBSP for External Attachment Generic McBSP Dedicated McBSP for Internal Codec Attachment Integrated Voltage Regulator 324-Terminal Plastic Ball Grid Array (PBGA) Package The TNETV1050 is a communications processor based on a MIPS32 reduced-instruction-set computer (RISC) processor, along with a C55x digital signal processor (DSP). The device has a rich peripheral set architected specifically for VoIP Phone applications, which results in a reduced bill of materials, reduced complexity, and time to develop an IP Phone. The TNETV1050 combines the key processor, communication, and peripheral functions necessary to build a basic or advanced IP Phone. The TNETV1050 architecture uses advanced design features to provide flexibility and performance throughput, while conserving power consumption. Combined with Telogy Software for IP Phone applications, the TNETV1050 provides a complete hardware/software solution capable of reducing system design cycle times. The RISC processor supplies the overall system services and performs user interface, network management, protocol stack management, call processing, and task scheduling functions. The DSP provides real-time voice processing functions such as echo cancellation, compression, PCM processing, and tone generation and detection. The two 10/100Base-T Ethernet MAC/PHY units are attached to an integrated Layer-2 3-port Ethernet switch, providing a complete Ethernet solution for telephony applications. IP phone designs are simplified through on-chip peripherals such as a 16-bit color LCD controller, 8 8 keypad interface, USB 1.1 controller (host or device), UART serial interface, programmable serial port, two VLYNQ interfaces, and several general-purpose I/Os. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Microwire is a trademark of National Semiconductor Corporation. MIPS32 and 4 KEc are trademarks of MIPs Tecchnologies Inc. C55x and VLYNQ are trademarks of Texas Instruments Incorporated. Telogy Software is a trademark of Telogy Networks Inc., a Texas Instruments company. information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 The integrated dual-channel 16-bit Codec includes the critical functions needed for IP Phone applications, including two ADCs (with five programmable inputs) and two DACs (with four programmable outputs). Other features include analog and digital sidetone control, antialiasing filter, programmable gain options, and programmable sampling rate (8 or 16 ksps). In addition to the voice Codec, an external McBSP serial interface and telephony interface provide glueless attachment to a wide variety of telephony peripherals. functional block diagram Display Controller UART DMA 4-channel Ethernet Switch (3-port) PHY MAC (10/100) MDIO, MII & LED PHY MAC (10/100) Serial Flexible GPIO (8 to 52) Keypad (8x8) External Memory Regulator MIPS (4KEc, 165 MHz) I-Cache (16KB) D-Cache I Cache (16KB) Interrupt Timers (x3) RAM (4KB) ROM (4KB) DSP (C55x, 125 MHz) I-Cache (12KW) RAM (64KW) Timer (x2) Interrupt DMA 4-channel USB Host USB Device VLYNQ (3 terminal) VLYNQ (5 terminal) Telephony Interface McBSP pdma McBSP Codec 2-channel PHY 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 MIPS32 4KEc 32-Bit RISC Processor 165 MHz, providing up to 223 Dhrystone MIPS 16K-byte 4-way set-associative instruction cache 16K-byte 4-way set-associative data cache Programmable Memory Management Unit (MMU) 4K-byte RAM on chip 4K-byte ROM on chip, with boot code Interrupt Handler: 40 primary interrupts with programmable priority 5 primary interrupts may be sourced externally 32 secondary interrupts with fixed priority Three 16-bit timers with prescaled clock: Two universal timers One dedicated watchdog timer Enhanced JTAG IEEE Standard debug interface Digital Signal Processor (DSP) C55x 125 MHz, providing up to 250 MIPS 12K-word 2-way set-associative instruction cache 64K-word RAM on chip: 32K-word dual access 32K-word single access Interrupt Handler Two 16-bit timers with prescaled clock: One universal timer One dedicated watchdog timer Universal 4-channel DMA controller Dedicated peripheral DMA controller JTAG IEEE standard debug interface POST OFFICE BOX DALLAS, TEXAS

4 On-Chip Peripherals: External Memory Interface, supporting: Two SDRAM chip selects, providing 128M byte Three chip selects, providing 16M byte each, RAM or ROM One chip select, providing 32M byte, FLASH Universal 4-channel DMA controller 52 general-purpose I/O signals: Eight general-purpose I/O, primary I/O functions 44 general-purpose I/O, secondary I/O functions Keypad interface, featuring: 8 8 matrix, accommodating 64 keys Expand key range with general-purpose I/O Hardware debounce feature Universal Asynchronous Receiver/Transmitter (UART) with hardware Auto Flow Control Sequencer-based serial port, providing programmable configuration for these standard serial interfaces: Serial-Port Interface (SPI) Inter-Integrated Circuit (I 2 C) Microwire Numerous standard and nonstandard variations Universal Serial Bus (USB), featuring: USB 1.1 device controller USB 1.1 host controller USB 1.1 compliant PHY, connecting host or device Two VLYNQ serial communication ports: One 3-terminal port One 5-terminal port A liquid crystal display (LCD) controller, supporting the following display types: Alphanumeric character displays Rasterized graphic displays up to pixels Micro interface graphic displays Ethernet Subsystem: 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 Two Ethernet ports, each featuring: Integrated IEEE Standard 802.3/802.3u 10/100Base-T PHY in both half and full duplex, with 100Base-FX support: Autonegotiation Parallel detection Supports IEEE Standard 802.3af in-line power through glueless connection to the TI device TPS2370 Integrated IEEE Standard Media Access Controller (MAC): Full duplex Jumbo packet Copy short/error frames Hardware flow control Address filtering (Unicast, Multicast, Broadcast, or Promiscuous Mode) Rule-based Multicast Ingress/Egress External Media Independent Interface (MII) and LED status indicators available Remote Network Monitoring (RMON) Management Information Base (MIB) statistics-gathering registers 3-port wire speed Ethernet switch, featuring: Layer-2 Ethernet switch functionality IEEE Standard 802.1p, with up to eight configurable prioritization queues, including priority regeneration Nonblocking architecture to ensure fast packet delivery with up to 64 MAC address table lookup and packet forwarding via store-and-forward architecture Software management capabilities: IEEE Standard 802.1D, Spanning Tree Protocol (STP) IEEE Standard 802.1Q, with shared and independent VLAN learning (SVL/IVL) for up to 16 FID VLAN tag insertion/deletion based on port VLAN parameters GMRP multicast support Broadcast storm protection Dedicated 32K-byte packet memory with automated remote overflow expandability 64-bit x 64-bit Content Addressable Memory (CAM) Dedicated host DMA controller POST OFFICE BOX DALLAS, TEXAS

6 Telephony Subsystem: Integrated audio Codec, featuring: Dual-channel 16-bit ADCs and DACs. Programmable sample rate 8/16 Kbps Selectable FIR/IIR filter with a bypass option Five inputs to the ADC Four outputs from the DAC ADC gain programmable (0 to 54 db) DAC gain programmable (0 to -54 db) Analog and digital sidetone A dedicated multichannel buffered serial port (McBSP) for internal Codec attachment A generic McBSP for external attachment Telephony interface, providing glueless attachment to a wide variety of telephony peripherals 6 POST OFFICE BOX DALLAS, TEXAS 75265

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