Computer Architecture: Part V. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

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1 Computer Architecture: Part V First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

2 Outline Addition and Subtraction Multiplication Algorithm Array Multiplier Peripheral Devices Input Output Interface Main Memory : Computer Organization and Architecture 2

3 Addition and Subtraction of Signed Magnitude Numbers We designate the magnitude of the two numbers by A and B. When the signed numbers are added or subtracted, we find that there are eight different conditions to consider, depending on the sign of the numbers and the operation performed. These conditions are listed in the first column of table in slide number 4. The other columns in the table show the actual operation to be performed with the magnitude of the numbers. The last column is needed to prevent a negative zero, when two equal numbers are subtracted, the result should be +0 not : Computer Organization and Architecture 3

4 Addition and Subtraction of Signed Magnitude Numbers : Computer Organization and Architecture 4

5 Hardware for signed magnitude addition and subtraction It consists of register A and B and sign flip flop flop A s and B s. Subtraction is done by adding A to the 2 s complement of B. Theoutputcarry is transferred to flip flope E, where it can be checked to determine the relative magnitudes of the two numbers. The add overflow flip flop AVF holds the overflow bit when A and B are added. The addition of A plus B is done through the parallel adder : Computer Organization and Architecture 5

6 Hardware for signed magnitude addition and subtraction The S (sum) output tof the adder is applied to the input of the A register. The complementer provides and output of B or the complement of B depending on the state of the mode control lm. When M = 0, the output of B is transferred to the adder, the input carry is 0, and the output of the adder is equal to the sum A + B. When M = 1, the 1 s complement of B is applied to the adder, the input carry is 1, and output S = A + B + 1 = A B : Computer Organization and Architecture 6

7 Hardware for signed magnitude addition and subtraction : Computer Organization and Architecture 7

8 Hardware Implementation A and B are registers. A S and B S are sign flip flops. E is an output carry flip flop. flop EA is a register that combines E and A. AVF is an add overflow flip flop. S is sum. M is mode control. M = 0, A + B + 0 = A + B M = 1, A + B + 1 = A B : Computer Organization and Architecture 8

9 Multiplication Algorithm : Computer Organization and Architecture 9

10 Hardware for multiply operation The multiplier is stored in the Q register and its sign in Qs. The sequence counter SC is initially set to a number equal to the number of bits in the multiplier. The counter is decremented dby 1 after forming each partial product. When the content of the counter reaches zero, the product is formed and the process stops : Computer Organization and Architecture 10

11 Hardware for multiply operation Initially, i the multiplicand li li dis in register B and the multiplier in Q. The sum of A and B forms partial product which h is transferred to the EA register. Both partialproductandmultiplierareshiftedto product and are to the right. The 0 is shifted into E. After the shift, one bit of the partial product is shifted into Q, pushing the multiplier bits one position to the right. In this manner, the rightmost flip flopinflop in register Q, designated by Q n, will hold the bit of the multiplier, which must be inspected next : Computer Organization and Architecture 11

12 Hardware for multiply operation : Computer Organization and Architecture 12

13 Numerical Example for Binary Multiplier : Computer Organization and Architecture 13

14 Array Multiplier The multiplicand bits are b 1 and b 0, the multiplier bits are a 1 and a 0, and the product is c 3 c 2 c 1 c 0. The first partial product is formed by multiplying a 0 by b 1 b 0. The multiplication of two bits such as a 0 and b 0 produces a 1 if both thbits are 1; otherwise, it produces a 0. This is identical to a AND operation and can be implemented with an AND gate : Computer Organization and Architecture 14

15 Array Multiplier The two partial ilproducts are added d with ihtwo half adder (HA) circuits. Usually, there are more bits in the partial products and it will be necessary to use full adders to produce the sum. Note that the least significant bit of the product does not have to go through an adder since it is formed by the output of the first AND gate : Computer Organization and Architecture 15

16 2 bit by 2 bit array multiplier : Computer Organization and Architecture 16

17 Peripheral Devices and Input Output Interface provides a method for transferring information between internal storage and external I/O devices. Peripherals connected to a computer need special communication links for interfacing them with the central processing unit. resolve the differences that exist between the central computer and each peripheral : Computer Organization and Architecture 17

18 I/O Bus and Interface Modules The I/O bus consists of data lines, address lines, and control lines. Each peripheral device has associated with it an interface unit. Each interface decodes the address and control received from the I/O bus, interprets them for the peripheral, and provides signals for the peripheral controller : Computer Organization and Architecture 18

19 Connection of I/O bus to input output devices : Computer Organization and Architecture 19

20 I/O versus Memory Bus The memory bus contains data, address, and read/write control lines. There are three ways that computer buses can be used to communicate with memory and I/O 1. Use two separate buses, one for memory and the other for I/O. 2. Use one common bus for both memory and I/O but have separate control lines for each. 3. Use one common bus for memory and I/O with common control lines : Computer Organization and Architecture 20

21 Example of I/O interface unit It consists of two data registers called ports, a control register, a status register, bus buffers, and timing and control circuits. The interface communicates with the CPU through the data bus. The chip select and register select inputs determine the address assigned to the interface. The I/O read and write are two control lines that specify an input or output, respectively. The four registers communicate directly with the I/O device attached to the interface : Computer Organization and Architecture 21

22 Example of I/O interface unit This circuit enables the chip select (CS) input when the interface is selected by the address bus. The two register select inputs RS1 and RS0 select one of the four registers in the interface as specified in the table accompanying the diagram. The content of the selected register is transfer into the CPU via the data bus when the I/O read signal is enabled. The CPU transfers binary information into the selected register via the data bus when the I/O write input is enabled : Computer Organization and Architecture 22

23 Example of I/O interface unit : Computer Organization and Architecture 23

24 Memory Hierarchies The memory hierarchy system consists of all storage devices employed in a computer system from the slow but high capacity auxiliary memory to a relatively faster main memory, to an even smaller and faster cache memory accessible to the high speed h processing logic. At the bottom of the hierarchy are the relatively slow magnetic tapes used to store removable files. Next are the magnetic disks used as backup storage : Computer Organization and Architecture 24

25 Memory Hierarchies The main memory occupies a central position by bi being able to communicate directly with ihthe CPU and with auxiliary memory devices through an I/O processor. When programs not residing in main memory are needed by the CPU, they are brought in from auxiliary memory. Programs not currently needed in main memory are transferred into auxiliary memory to provide space for currently used programs and data : Computer Organization and Architecture 25

26 Memory Hierarchies A special very high speed memory called a cache is sometimes used to increase the speed of processing by making current programs and data available lbl to the CPU at a rapid rate. The cache memory is employed in computer systems to compensate for the speed differential between main memory access time and processor logic. CPU logic is usually faster than main memory access time, with the result that processing speed is limited primarily by the speed of main memory : Computer Organization and Architecture 26

27 Memory hierarchy in a computer system : Computer Organization and Architecture 27

28 Main Memory RAM is used for storing the bulk of the programs and data that are subject to change. ROM is used for storing programs that are permanently resident in thecomputer and for tables of constants that do not change in value once the production of the computer is completed : Computer Organization and Architecture 28

29 Typical RAM chip The capacity of the memory is 128 words of eight bits (one byte) )per word. This requires a 7 bit address and an 8 bit bidirectional data bus. The read and write inputs specify the memory operation and the two chips select (CS) control inputs are for enabling the chip only when it is selected by the microprocessor : Computer Organization and Architecture 29

30 Typical RAM chip The function table listed in slide number 31 specifies the operation of the RAM chip. The unit is in operation only when CS1 = 1 and CS2 = 0. If the chip select inputs are not enabled, or if they are enables but the read or write inputs are not enabled, the memory is inhibited and its data bus is in a high impedance state : Computer Organization and Architecture 30

31 Typical RAM chip : Computer Organization and Architecture 31

32 Typical ROM chip : Computer Organization and Architecture 32

33 Memory Address Map for Microprocessor The component column specifies whether a RAM or a ROM chip is used. The hexadecimal address column assigns a range of hexadecimal equivalent addresses for each chip. The small xs x s under the address bus lines designate those lines that must be connected to the address inputs in each chip. The RAM chips have 128 bytes and need seven address line. The ROM chip has 512 bytes and needs 9 address line. We choose bus lines 8 and 9 to represent four distinct binary combinations. Note that any other pair of unused bus lines can be chosen for this purpose : Computer Organization and Architecture 33

34 Memory Address Map for Microprocessor The distinction between a RAM and ROM address is done with another bus line. Here we choose line 10 for this purpose. The equivalent hexadecimal address for each chip is obtained from the information under the address bus assignment. The address bus lines are aesubdivided ded into groups of four bits each so that each group can be represented with a hexadecimal digit. The x s represent a binary number that can range from an all 0 s to an all 1 s value : Computer Organization and Architecture 34

35 Memory Address Map for Microprocessor : Computer Organization and Architecture 35

36 Reference M. Moris Mano, Computer System Architecture, 3 rd ed. NJ: Prentice Hall, : Computer Organization and Architecture 36

Computer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

Computer Architecture: Part III First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Decoders Multiplexers Registers Shift Registers Binary Counters Memory