Memory Management. Minsoo Ryu. Real-Time Computing and Communications Lab. Hanyang University.

Transcription

1 Memory Management Minsoo Ryu Real-Time Computing and Communications Lab. Hanyang University

2 Topics Covered Introduction Memory Allocation and Fragmentation Address Translation Paging Segmentation 2 2

3 Introduction CPU scheduling allows processes to share CPU Improving both the CPU utilization and the response speed To realize this, We must keep several processes in memory This entails many complex problems for memory management Memory management is one of the most complex parts of the OS Serves many different purposes 3 3

4 Introduction General goals of memory management Provide a single contiguous, protected memory space to each process, make memory sharing easy for different processes, and allow for flexible memory management Provide a larger separate memory space to every process than the physically available memory space Every process can be allowed to use a 4GB memory space even though the physical memory is 1GB Tricks used by OS Noncontiguous physical memory allocation and address translation Paging or segmentation Differentiate addresses seen by each process from the real addresses Allocate memory on demand (demand paging) 4 4

5 Background: Address Binding Address binding Assign memory addresses to all instructions and data Three phases of address binding Compile time If memory location can be known a priori, Absolute code can be generated; must recompile code if starting location changes Load time A compiler may generate relocatable code if memory location is not known at compile time Execution time Binding is delayed until run time if the process can be moved during its execution from one memory segment to another 5 5

6 Multistep Processing of a User Program 6 6

7 Translation Hierarchy 7 7

8 Contiguous Memory Allocation Contiguous memory allocation to multiple processes Hole block of available memory; holes of various size are scattered throughout memory When a process arrives, it is allocated memory from a hole large enough to accommodate it Operating system maintains information about: a) allocated partitions b) free partitions (hole) process 2 process 2 process 2 process 2 process 5 process 5 process 5 process 5 process 8 process 9 process 9 process 10 OS OS OS OS 8 8

9 Contiguous Memory Allocation Algorithms How to satisfy a request of size n from a list of free holes? Three algorithms First-fit: allocate the first hole that is big enough Best-fit: allocate the smallest hole that is big enough Must search entire list, unless ordered by size Produces the smallest leftover hole Worst-fit: allocate the largest hole Must also search entire list Produces the largest leftover hole First-fit and best-fit are better than worst-fit In terms of speed and storage utilization 9 9

10 Fragmentation Problem Two types of fragmentation External Fragmentation Total memory space exists to satisfy a request, but it is not contiguous Internal Fragmentation Allocated memory may be slightly larger than requested memory This size difference is memory internal to a partition, but not being used 10 10

11 Fragmentation proc 1 proc 1 proc 2 free new proc 9? proc 2 free fragmentation problem! proc 7 proc 7 free? free proc 4 Physical Memory proc 4 Physical Memory 11 11

12 Solutions to Fragmentation Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block Compaction is possible only if relocation is dynamic, and is done at execution time Another solution Noncontiguous memory allocation with address translation 12 12

13 Address Translation Programs use logical (virtual) addresses and OS/HW translate them into physical (real) addresses Purposes of address translation Flexible memory placement Memory protection Memory sharing Sparse addresses 13 13

14 Logical vs. Physical Address Space The concept of a logical address space that is bound to a separate physical address space is central to proper memory management Logical (virtual) address Generated by the CPU Also referred to as virtual address Physical address Seen by the memory unit 14 14

15 MMU Memory-Management Unit (MMU) Hardware device that maps virtual to physical address The user program Deals with logical addresses It never sees the physical addresses 15 15

16 Dynamic Relocation Using a Relocation Register 16 16

17 Hardware Support for Relocation and Limit Registers 17 17

18 Noncontiguous Memory Allocation with Address Translation Segmentation Allocate memory on a segment basis Process memory = code segment + data segment + stack segment + Different segments have different sizes Paging Allocate memory on a page basis Process memory = page + page + page Pages have the same fixed size

19 Segmentation proc 1 code seg. data seg. stack seg. proc 1 proc 7 proc 2 proc 4 proc 2 proc 4 proc 1 proc 1 proc 7 proc 2 Physical Memory free segment free free free free free reduced fragmentation 19 19

20 Paging free proc 1 proc 2 proc 4 proc 7 free page free free no (external) fragmentation free free Physical Memory 20 20

21 Paging Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes) Divide logical memory into blocks of same size called pages Keep track of all free frames To run a program of size n pages, need to find n free frames and load program Page-to-frame mapping OS and HW need to maintain page-to-frame mapping information A naïve approach would require too many relocation registers Page table is a reasonable solution 21 21

22 Page Table and Address Translation Page table for each process is kept in main memory Two registers are used to locate the page table Page-table base register (PTBR) points to the page table Page-table length register (PRLR) indicates size of the page table Address generated by CPU is divided into: Page number (p) used as an index into a page table which contains base address of each page in physical memory Page offset (d) combined with base address to define the physical memory address that is sent to the memory unit 22 22

23 Address Translation Architecture 23 23

24 Paging Example 24 24

25 Paging and Address Translation 0x CPU 0x page number page offset 0x x x x x x x x x x x x x x x Page Table Physical Memory 25 25

26 Implementation of Page Table Page table for each process is kept in main memory Page table in modern systems is very large One million entries It is not possible to use fast registers Every data/instruction access requires two memory accesses One for the page table and one for the data/instruction 26 26

27 Translation Look-Aside Buffer The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) TLB is a special and small hardware cache Associative memory parallel search Address translation (A, A ) = (key, value) If A is in associative register, get frame # out Otherwise get frame # from page table in memory Page # Frame # 27 27

28 Paging Hardware With TLB 28 28

29 Hit ratio: H Effective Memory-Access Time The percentage of times that a particular page number is found in the TLB TLB search time: T Memory access time: M Effective Access Time H (T + M) + (1 - H) (T + M + M) e.g. H = 80%, T = 20 nanosec, M = 100 nanosec, 0.8 x ( ) x ( ) =

30 Memory Protection Memory protection implemented by associating protection bit with each frame Valid-invalid bit attached to each entry in the page table: valid indicates that the associated page is both legal and in the memory invalid indicates that the page is not legal or not in the memory 30 30

31 Valid (v) or Invalid (i) Bit In A Page Table 31 31

32 Hierarchical Paging Hashed Page Tables Inverted Page Tables Page Table Structure 32 32

33 Hierarchical Page Tables Most modern systems support a large logical address space (2^32 to 2^64) Page table becomes excessively large If the page size is 4KB (2^12) Then a page table may consist of one million entries (2^20) If each entry size is 4Bytes Then each process may need up to 4MB for the page table alone We want to allocate the page table contiguously Break up the logical address space into multiple page tables A simple technique is a two-level page table 33 33

34 Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits a page offset consisting of 12 bits Since the page table is paged, the page number is further divided into: page number page offset a 10-bit page number p i p 2 d a 10-bit page offset Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table 34 34

35 Two-Level Page-Table Scheme 35 35

36 Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture 36 36

37 Two-Level Page Table 0x x x CPU 0x p 1 p 2 0x x x x x01bc0035 p 1 0x0a x x01bc0035 0x x p 2 0x x x x x x x x x Outer Page Table Page Table Physical Memory 37 37

38 Hashed Page Tables Common in address spaces > 32 bits The virtual page number is hashed into a page table This page table contains a chain of elements hashing to the same location Virtual page numbers are compared in this chain searching for a match If a match is found, the corresponding physical frame is extracted 38 38

39 Hashed Page Table 39 39

40 Inverted Page Table One entry for each real page of memory Only one page table in the system 64-bit UltraSPARC and PowerPC Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs Use hash table to limit the search to one or at most a few page-table entries 40 40

41 Inverted Page Table Architecture 41 41

42 Shared code Shared Pages Reentrant code can be shared among processes (i.e., text editors, compilers, window systems) Two or more processes can execute the same code Shared page Only one copy of the shared code needs to be kept in physical memory Some systems implement shared memory IPC using shared pages Systems that use inverted page tables have difficulty implementing shared memory Single physical address Multiple virtual addresses 42 42

43 Shared Pages Example 43 43

44 Segmentation Memory-management scheme that supports user view of memory Most users prefer to view memory as a collection of variablesized segments A segment may include one of the following main program, subroutines, stack, symbol table, 44 44

45 User s View of a Program 45 45

46 Logical View of Segmentation user space physical memory space 46 46

47 What s in an Object File or Executable? Header magic number indicates type of image. Section table an array of (offset, len, startva) program sections Used by linker; may be removed after final link step and strip. header text idata wdata symbol table relocation records program instructions p immutable data (constants) hello\n writable global/static data j, s j, s,p,sbuf int j = 327; char* s = hello\n ; char sbuf[512]; int p() { int k = 0; j = write(1, s, 6); return(j); } 47 47

48 The Program and the Process VAS (Virtual Address Space) Process text segment is initialized directly from program text section. sections Process data segment(s) are initialized from idata and wdata sections. Text and idata segments may be write-protected. header text idata wdata symbol table relocation records program text data BSS user stack args/env kernel process VAS Process stack and BSS (e.g., heap) segment(s) are zero-filled. BSS Block Started by Symbol (uninitialized global data) e.g., heap and sbuf go here. segments Process BSS segment may be expanded at runtime with a system call (e.g., Unix sbrk) called by the heap manager routines. Args/env strings copied in by kernel when the process is created

49 Virtual Addressing User processes address memory through virtual addresses. The kernel and the machine collude to translate virtual addresses to physical addresses. virtual memory (big) text data BSS user stack args/env kernel physical memory (small) The kernel controls the virtual-physical translations in effect for each space. The machine does not allow a user process to access memory unless the kernel says it s OK. virtual-to-physical translations The specific mechanisms for memory management and address translation are machine-dependent

50 Segmentation Architecture Logical address consists of a two tuple <segment-number, offset> Segment table Maps two-dimensional physical addresses Each table entry has base contains the starting physical address where the segments reside in memory. limit specifies the length of the segment

51 Segmentation Hardware 51 51

52 Example of Segmentation 52 52

53 Advantages and Disadvantages of Segmentation Protection Segments represent semantically defined portion of the program All entries are used in the same way Protection among segments in the same program We can protect read-only and execute-only segments from others Protection among programs Any illegal memory reference is automatically checked by the hardware Sharing Code or data sharing When entries in the segment tables of two different processes point to the same physical location Fragmentation Segments are of variable length 53 53

54 Segmentation with Paging MULTICS The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment, but rather the base address of a page table for this segment 54 54

55 MULTICS Address Translation Scheme 55 55

56 Intel Address Translation 56 56