This Part-A course discusses techniques that are used to reduce noise problems in the design of large scale integration (LSI) devices.

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1 Course Introduction Purpose This Part-A course discusses techniques that are used to reduce noise problems in the design of large scale integration (LSI) devices. Objectives Understand the requirement for electromagnetic noise countermeasures. Learn approaches and design methods for minimizing the electromagnetic interference (EMI) emitted by LSI devices. Gain insight into how Renesas applies these techniques for handling noise problems in its microcomputer products. Content 16 pages Learning Time 20 minutes 1

2 Noise Can Cause Big Problems Two types of noise: Noise = Unwanted electrical signals that produce undesirable effects in the circuits of control systems in which they occur. Electromagnetic Compatibility (EMC) issues encompass both types Noise reduction approaches: Techniques for reducing EMI (Electromagnetic Interference) Cutting the noise emitted by a specific system, circuit or device that causes other devices/circuits to operate incorrectly Techniques for decreasing EMS (Electromagnetic Susceptibility) minimizing the effect that external noise has on the operation of a system, circuit or device Noise reduction: a goal common to both microcontroller (MCU) designers and the system engineers who apply those devices 2

3 Why Is EMI Reduction Important? Example of real-world effects: EMI can cause problems in the AV equipment and CIS products in an automobile Noise is emitted by MCU and harness, causing EMI Antenna picks up EMI noise, which degrades radio reception Battery Audio-visual equipment, CIS products MCU Wiring harness (power line) LSI device 3

4 If measures are taken to deal only with elements of primary importance 60 Effect: -3dB Action: 10 db reduction -10dB 4 No source of noise should be overlooked! Primary Sources of EMI Secondary Sources Total EMI Primary Sources Secondary Sources Total EMI EMI level (db) Before After If measures are taken to deal with all important noise elements 60 Effect: -5dB 50 Primary Sources of EMI Secondary Sources Total EMI Primary Sources Secondary Total EMI EMI level (db) Minimize ALL Sources of EMI EMI reduction requires a comprehensive design approach and attention to detail If measures are taken to deal only with secondary elements 60 Effect: -0.2dB dB Before countermeasure Before After Primary Sources of EMI Secondary Sources Total EMI Primary Sources Secondary Total EMI EMI level (db) Action: 10 db reduction After countermeasure

5 Explanation of Terms Core CPG Driver buffer EMC EMI EMS Harness I/O OSC PLL POR/LVD Power supply SSCG WDT A microcontroller chip is composed of a core, I/O ports, and power supply circuitry. The core consists of the CPU, ROM, RAM, and blocks implementing timers, communication, and analog functions. Clock Pulse Generator Output circuit transistors as well as output circuits for driving signals with large load capacitance and I/O port output transistors. Clock/bus driver, signals between blocks, etc. Electromagnetic Compatibility Electromagnetic Interference Electromagnetic Susceptibility Cables (wires) connecting a board and power supply or connecting one unit in a system to another. Input/Output Port Oscillator Phase Locked Loop Power-On Reset/Low-Voltage Detect functions Two power supplies are applied to the LSI: and. The core power supply internal to the LSI is VCL (internal step-down). The -based power supply routed through the LSI is VSL. Spread-Spectrum Clock Generator Watchdog Timer 5

6 Pin Assignments Help Reduce EMI Microcontroller pin assignments should provide power supply and signal pin placements that closely match those of external LSI devices Allows short interconnections Helps prevent crossed wires Improves noise control Facilitates crosstalk countermeasures Renesas microcontroller External LSI Reduces parasitic loads 6

7 Arrangement of Key Pins Pins should be arranged in an electrical potential gradient Pin layout should concentrate key pins in one area Arrangement should make it easy to mount bypass capacitors for noise countermeasures Standardized layouts promote design consistency Key pins are concentrated in a single location Effects of electrical potential differences are minimized BYTE CNVSS XCIN XCOUT /RESET XOUT VSS XIN VCC / NMI Capacitor for Reset Oscillation capacitors GND To Reset IC GND 7 VCC Oscillation capacitors Ceramic bypass capacitor Pin arrangement makes it easy to mount bypass capacitors between power supply lines and ground lines. Tantalum bypass capacitor

8 Power Supply Pin Assignments Placing power supply pins in pairs near each other makes it easy to mount bypass capacitors where they can be effective C3 I/O PORT-1 power supply pin CORE-1 power supply pin I/O PORT-1 CORE-1 CORE-2 CORE-2 power supply pin e e C2 C4 Vcl (Vdd) Vcl (Vdd) CA core CB core C1, C2, C3, C4 = Power supply bypass capacitors C1 8 I/O PORT-2 I/O PORT-2 power supply pin CA, CB = Step-down power supply (Vdd) stabilization capacitors

9 Analog vs. Digital Signal Pins For best analog circuit performance, some types of digital signal pins must not be located close to the analog signal pins AVCC AVSS AVREF Analog signal pins The following types of digital signal pins should not be placed in these locations: High-current ports Clock-related ports High-speed telecom ports 9

10 Power Supply Circuit Internal step-down power supply circuit runs off 5V, produces precise lower voltage (Vdd) for core The lower the core voltage, the greater the EMI reduction A slower slew rate cuts EMI A low Vdd reduces power consumption, too. 5V I/O Step-down circuit External step-down power supply circuit stabilization capacitor = 5.0V Vdd (core voltage) = 1.2V Step-down voltage None Low Vcl Vsl or Core: CPU ROM RAM TIMERS SCI Etc. A/D, D/A EMI High Reduced Layout of internal step-down circuit (conceptual) 10

11 Step-down Power Supply Voltage Step-down voltage is used at the 0.5µm process generation and below to reduce EMI Process limitations at 0.35µm and 0.5µm process generations and below mandate lower core voltages Further decreases in Vdd are expected, allowing additional EMI reductions and power savings Core power supply voltage (Vdd), typ. [V] Core voltage aimed at preventing EMI 0.8µm 0.5µm 3.0V Ultralow-noise version 0.5µm (with internal step-down voltage specification) µm Process limitations 1.8V Ultralow-noise version 0.18µm 1.2V I/O = 5V Further reductions in core voltage Process generation

12 EMI Filter in Step-down Supply π - type R-C filter is located between step-down circuit and core Uses parasitic capacitances of step-down transistors and core and parasitic resistance of internal power supply lines Electromagnetic filter circuit To external stabilization capacitor Internal step-down circuit Parasitic resistance of internal power supply lines Parasitic capacitances Vdd CORE 12

13 Wiring for Power Supply Lines In devices with multiple power supply pins, and should be... Supplied in pairs Located near each other This design approach ensures that the chip s internal power supply lines do not cross Core-A power supply I/O-A I/O-B CORE -A I/O-B Power supply I/O-A power supply CORE -B Core-B power supply 13

14 Main Power Supply Lines in Core Power supply lines to I/O and core are separated Mesh configuration is used for supply lines to core Bonding pads CORE Primary core supply lines CORE TIMER CPU SCI CPG RAM ROM I/O circuits 14

15 Capacitors in Power Supply Lines Capacitors can be placed in various locations within the LSI device They deliver supplemental charge needed for driving digital-circuit switching Without embedded capacitors, ripple component of power supply waveform is large With capacitors, ripple component is small and EMI is reduced 5V-I/O Step-down circuit Embedded Capacitor A/D, D/A 15

16 Course Summary Types of noise (EMI and EMS) in microcomputers Importance of EMC Reducing EMI by using optimum methods for pin assignments, step-down power supply design, and on-chip power wiring For more information on specific devices and related support products and material, please visit our Web site: 16

This Part-B course discusses design techniques that are used to reduce noise problems in large-scale integration (LSI) devices.

This Part-B course discusses design techniques that are used to reduce noise problems in large-scale integration (LSI) devices. Course Introduction Purpose This Part-B course discusses design techniques that are used to reduce noise problems in large-scale integration (LSI) devices. Objectives Learn approaches and design methods

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