MC68HC908GR8A MC68HC908GR4A Data Sheet

Transcription

1 MC68HC908GR8A MC68HC908GRA Data Sheet M68HC08 Microcontrollers MC68HC908GR8A Rev. 5 0/2007 freescale.com

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3 MC68HC908GR8A MC68HC908GRA Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash technology licensed from SST. Freescale Semiconductor, Inc., 2005, All rights reserved. Freescale Semiconductor

4 Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date April, 200 October, 200 Revision Level Description Page Number(s) 0 Initial release N/A 1 Module construction and style updated to meet current publications standards. Throughout IRQ1 changed to IRQ Throughout Mask option register changed to configuration register Throughout Deleted references to DMA module and bits Throughout FLASH memory operation details updated Conversion Clarified ADC details ADC Status and Control Register Corrected COCO bit functionality 51 Table -1. Numeric Example Corrected and improved examples 61 Table -. Example Filter Component Values Added more values 7 Chapter 5 Configuration Register (CONFIG) Updated COP timeout selections 75, Functional Description Updated block diagram and timeout values 79, 80 Table 7-1. Instruction Set Summary Corrected STOP and added WAIT instruction 92, 9 8. Functional Description Updated IRQ description IRQ Pin Updated IRQ description 97 Chapter 12 Input/Output (I/O) Ports Corrected Figures 12-, 12-11, , 12, 126 Figure 1-. SCI Module Block Diagram Corrected diagram 1 Figure 1-5. SCI Transmitter Updated diagram 16 Figure 1-6. SCI Receiver Block Diagram Updated Diagram 19 Chapter 1 System Integration Module (SIM) Clarified SIM features and functionality Functional Description Updated TBM description 195 Table 17-. Mode, Edge, and Level Selection Added software compare condition 21 Chapter 18 Development Support Combined Break and Monitor Mode modules Functional Description Corrected Break description Monitor Module (MON) Reworked for clarity V DC Electrical Characteristics Changed V TST max to 8.5 V V DC Electrical Characteristics Changed V TST max to 8.5 V CGM Component Specifications Corrected and updated values CGM Electrical Specifications Corrected and updated values Memory Characteristics Updated memory characteristics table 28 Freescale Semiconductor

5 Revision History Date October, 200 June, 2005 March, 2006 April, 2007 Revision Level 2 5 Description Memory Characteristics Corrected values for FLASH read bus clock frequency Absolute Maximum Ratings Corrected value for supply voltage V DC Electrical Characteristics Corrected stop IDD and I/O ports Hi-Z leakage current values V DC Electrical Characteristics Corrected stop IDD and I/O ports Hi-Z leakage current values Package Dimensions Updated package information Clock Generator Module (CGM) Updated description to remove erroneous information. Page Number(s) Chapter 5 Configuration Register (CONFIG) Replaced COPCLK with CGMXCLK and corrected what set and cleared indicate for bit 75 CONFIG1_COPRS Stop Mode Replaced COPCLK with CGMXCLK Freescale Semiconductor 5

6 Revision History 6 Freescale Semiconductor

7 List of Chapters Chapter 1 General Description Chapter 2 Memory Chapter Analog-to-Digital Converter (ADC) Chapter Clock Generator Module (CGM) Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) Module Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Power Modes Chapter 11 Low-Voltage Inhibit (LVI) Chapter 12 Input/Output (I/O) Ports Chapter 1 Serial Communications Interface (SCI) Module Chapter 1 System Integration Module (SIM) Chapter 15 Serial Peripheral Interface (SPI) Module Chapter 16 Timebase Module (TBM) Chapter 17 Timer Interface Module (TIM1 and TIM2) Chapter 18 Development Support Chapter 19 Electrical Specifications Chapter 20 Ordering Information and Mechanical Specifications Freescale Semiconductor 7

8 List of Chapters 8 Freescale Semiconductor

9 Table of Contents Chapter 1 General Description 1.1 Introduction Features Standard Features Features of the CPU MCU Block Diagram Pin Assignments Pin Functions Power Supply Pins (V DD and V SS ) Oscillator Pins (OSC1 and OSC2) External Reset Pin (RST) External Interrupt Pin (IRQ) CGM Power Supply Pins (V DDA and V SSA ) External Filter Capacitor Pin (V CGMXFC ) ADC Power Supply/Reference Pins (V DDAD /V REFH and V SSAD /V REFL ) Port A Input/Output (I/O) Pins (PTA/KBD PTA0/KBD0) Port B I/O Pins (PTB5/AD5 PTB0/AD0) Port C I/O Pins (PTC1 and PTC0) Port D I/O Pins (PTD6/T2CH0 PTD0/SS) Port E I/O Pins (PTE1/RxD and PTE0/TxD) Chapter 2 Memory 2.1 Introduction Unimplemented Memory Locations Reserved Memory Locations Input/Output (I/O) Section Random-Access Memory (RAM) FLASH Memory (FLASH) Functional Description FLASH Control Register FLASH Page Erase Operation FLASH Mass Erase Operation FLASH Program/Read Operation FLASH Block Protection FLASH Block Protect Register Wait Mode Stop Mode Freescale Semiconductor 9

10 Table of Contents Chapter Analog-to-Digital Converter (ADC).1 Introduction Features Functional Description ADC Port I/O Pins Voltage Conversion Conversion Time Conversion Accuracy and Precision Interrupts Low-Power Modes Wait Mode Stop Mode I/O Signals ADC Analog Ground Pin (V SSAD )/ADC Voltage Reference Low Pin (V REFL ) ADC Analog Power Pin (V DDAD )/ADC Voltage Reference High Pin (V REFH ) ADC Voltage In (V ADIN ) I/O Registers ADC Status and Control Register ADC Data Register ADC Clock Register Chapter Clock Generator Module (CGM).1 Introduction Features Functional Description Crystal Oscillator Circuit Phase-Locked Loop Circuit (PLL) PLL Circuits Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Programming the PLL Special Programming Exceptions Base Clock Selector Circuit CGM External Connections I/O Signals Crystal Amplifier Input Pin (OSC1) Crystal Amplifier Output Pin (OSC2) External Filter Capacitor Pin (CGMXFC) PLL Analog Power Pin (V DDA ) PLL Analog Ground Pin (V SSA ) Oscillator Enable Signal (SIMOSCEN) Oscillator Stop Mode Enable Bit (OSCSTOPENB) Crystal Output Frequency Signal (CGMXCLK) CGM Base Clock Output (CGMOUT) CGM CPU Interrupt (CGMINT) Freescale Semiconductor

11 .5 CGM Registers PLL Control Register PLL Bandwidth Control Register PLL Multiplier Select Register High PLL Multiplier Select Register Low PLL VCO Range Select Register PLL Reference Divider Select Register Interrupts Special Modes Wait Mode Stop Mode CGM During Break Interrupts Acquisition/Lock Time Specifications Acquisition/Lock Time Definitions Parametric Influences on Reaction Time Choosing a Filter Chapter 5 Configuration Register (CONFIG) 5.1 Introduction Functional Description Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction Functional Description I/O Signals CGMXCLK STOP Instruction COPCTL Write Power-On Reset Internal Reset COPD (COP Disable) COPRS (COP Rate Select) COP Control Register Interrupts Monitor Mode Low-Power Modes Wait Mode Stop Mode COP Module During Break Mode Chapter 7 Central Processor Unit (CPU) 7.1 Introduction Features Freescale Semiconductor 11

12 Table of Contents 7. CPU Registers Accumulator Index Register Stack Pointer Program Counter Condition Code Register Arithmetic/Logic Unit (ALU) Low-Power Modes Wait Mode Stop Mode CPU During Break Interrupts Instruction Set Summary Opcode Map Chapter 8 External Interrupt (IRQ) 8.1 Introduction Features Functional Description IRQ Pin IRQ Module During Break Interrupts IRQ Status and Control Register Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction Features Functional Description Keyboard Initialization Low-Power Modes Wait Mode Stop Mode Keyboard Module During Break Interrupts I/O Registers Keyboard Status and Control Register Keyboard Interrupt Enable Register Chapter 10 Low-Power Modes 10.1 Introduction Wait Mode Stop Mode Analog-to-Digital Converter (ADC) Wait Mode Stop Mode Break Module (BRK) Wait Mode Stop Mode Freescale Semiconductor

13 10. Central Processor Unit (CPU) Wait Mode Stop Mode Clock Generator Module (CGM) Wait Mode Stop Mode Computer Operating Properly Module (COP) Wait Mode Stop Mode External Interrupt Module (IRQ) Wait Mode Stop Mode Keyboard Interrupt Module (KBI) Wait Mode Stop Mode Low-Voltage Inhibit Module (LVI) Wait Mode Stop Mode Serial Communications Interface Module (SCI) Wait Mode Stop Mode Serial Peripheral Interface Module (SPI) Wait Mode Stop Mode Timer Interface Module (TIM1 and TIM2) Wait Mode Stop Mode Timebase Module (TBM) Wait Mode Stop Mode Exiting Stop Mode Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction Features Functional Description Polled LVI Operation Forced Reset Operation Voltage Hysteresis Protection LVI Trip Selection LVI Status Register LVI Interrupts Low-Power Modes Wait Mode Stop Mode Freescale Semiconductor 1

14 Table of Contents Chapter 12 Input/Output (I/O) Ports 12.1 Introduction Port A Port A Data Register Data Direction Register A Port A Input Pullup Enable Register Port B Port B Data Register Data Direction Register B Port C Port C Data Register Data Direction Register C Port C Input Pullup Enable Register Port D Port D Data Register Data Direction Register D Port D Input Pullup Enable Register Port E Port E Data Register Data Direction Register E Chapter 1 Serial Communications Interface (SCI) Module 1.1 Introduction Features Pin Name Conventions Functional Description Data Format Transmitter Character Length Character Transmission Break Characters Idle Characters Inversion of Transmitted Output Transmitter Interrupts Receiver Character Length Character Reception Data Sampling Framing Errors Baud Rate Tolerance Receiver Wakeup Receiver Interrupts Error Interrupts Low-Power Modes Wait Mode Stop Mode Freescale Semiconductor

15 1.6 SCI During Break Module Interrupts I/O Signals PTE0/TxD (Transmit Data) PTE1/RxD (Receive Data) I/O Registers SCI Control Register SCI Control Register SCI Control Register SCI Status Register SCI Status Register SCI Data Register SCI Baud Rate Register Chapter 1 System Integration Module (SIM) 1.1 Introduction SIM Bus Clock Control and Generation Bus Timing Clock Startup from POR or LVI Reset Clocks in Stop Mode and Wait Mode Reset and System Initialization External Pin Reset Active Resets from Internal Sources Power-On Reset Computer Operating Properly (COP) Reset Illegal Opcode Reset Illegal Address Reset Low-Voltage Inhibit (LVI) Reset Monitor Mode Entry Module Reset (MODRST) SIM Counter SIM Counter During Power-On Reset SIM Counter During Stop Mode Recovery SIM Counter and Reset States Exception Control Interrupts Hardware Interrupts SWI Instruction Interrupt Status Registers Reset Break Interrupts Status Flag Protection in Break Mode Low-Power Modes Wait Mode Stop Mode SIM Registers SIM Break Status Register SIM Reset Status Register SIM Break Flag Control Register Freescale Semiconductor 15

16 Table of Contents Chapter 15 Serial Peripheral Interface (SPI) Module 15.1 Introduction Features Functional Description Master Mode Slave Mode Transmission Formats Clock Phase and Polarity Controls Transmission Format When CPHA = Transmission Format When CPHA = Transmission Initiation Latency Queuing Transmission Data Error Conditions Overflow Error Mode Fault Error Interrupts Resetting the SPI Low-Power Modes Wait Mode Stop Mode SPI During Break Interrupts I/O Signals MISO (Master In/Slave Out) MOSI (Master Out/Slave In) SPSCK (Serial Clock) SS (Slave Select) I/O Registers SPI Control Register SPI Status and Control Register SPI Data Register Chapter 16 Timebase Module (TBM) 16.1 Introduction Features Functional Description Interrupts Low-Power Modes Wait Mode Stop Mode Timebase Control Register Chapter 17 Timer Interface Module (TIM1 and TIM2) 17.1 Introduction Features Freescale Semiconductor

17 17. Pin Name Conventions Functional Description TIM Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Buffered Output Compare Pulse Width Modulation (PWM) Unbuffered PWM Signal Generation Buffered PWM Signal Generation PWM Initialization Interrupts Low-Power Modes Wait Mode Stop Mode TIM During Break Interrupts I/O Signals I/O Registers TIM Status and Control Register TIM Counter Registers TIM Counter Modulo Registers TIM Channel Status and Control Registers TIM Channel Registers Chapter 18 Development Support 18.1 Introduction Break Module (BRK) Functional Description Flag Protection During Break Interrupts TIM During Break Interrupts COP During Break Interrupts Break Module Registers Break Status and Control Register Break Address Registers SIM Break Status Register SIM Break Flag Control Register Low-Power Modes Monitor Module (MON) Functional Description Normal Monitor Mode Forced Monitor Mode Monitor Vectors Data Format Break Signal Baud Rate Commands Security Freescale Semiconductor 17

18 Table of Contents Chapter 19 Electrical Specifications 19.1 Introduction Absolute Maximum Ratings Functional Operating Range Thermal Characteristics V DC Electrical Characteristics V DC Electrical Characteristics V Control Timing V Control Timing Output High-Voltage Characteristics Output Low-Voltage Characteristics Typical Supply Currents ADC Characteristics V SPI Characteristics V SPI Characteristics Clock Generation Module Characteristics CGM Component Specifications CGM Electrical Specifications Timer Interface Module Characteristics Memory Characteristics Chapter 20 Ordering Information and Mechanical Specifications 20.1 Introduction MC Order Numbers Package Dimensions Freescale Semiconductor

19 Chapter 1 General Description 1.1 Introduction The MC68HC908GR8A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. This document also describes the MC68HC908GRA. The MC68HC908GRA is a device identical to the MC68HC908GR8A except that it has less FLASH memory. Only when there are differences from the MC68HC908GR8A is the MC68HC908GRA specifically mentioned in the text. 1.2 Features For convenience, features have been organized to reflect: Standard features Features of the CPU Standard Features Features include: High-performance M68HC08 architecture optimized for C-compilers Fully upward-compatible object code with M6805, M16805, and M68HC05 Families 8-MHz internal bus frequency Clock generation module supporting 1-MHz to 8-MHz crystals FLASH program memory security (1) On-chip programming firmware for use with host personal computer which does not require high voltage for entry In-system programming (ISP) System protection features: Optional computer operating properly (COP) reset Low-voltage detection with optional reset and selectable trip points for.0-v and 5.0-V operation Illegal opcode detection with reset Illegal address detection with reset Low-power design; fully static with stop and wait modes Standard low-power modes of operation: Wait mode Stop mode 1. No security feature is absolutely secure. However, Freescale s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor 19

20 General Description Master reset pin and power-on reset (POR) 7680 bytes of on-chip FLASH memory on the MC68HC908GR8A and 096 byes of on-chip FLASH memory on the MC68HC908GRA with in-circuit programming capabilities of FLASH program memory. 8 bytes of on-chip random-access memory (RAM) 5 bytes of FLASH programming routines read-only memory (ROM) Serial peripheral interface (SPI) module Serial communications interface (SCI) module One 16-bit, 2-channel timer (TIM1) and one 16-bit, 1-channel timer (TIM2) interface modules with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel Up to 6-channel, 8-bit successive approximation analog-to-digital converter (ADC) depending on package choice BREAK (BRK) module to allow single breakpoint setting during in-circuit debugging Internal pullups on IRQ and RST to reduce system cost Up to 21 general-purpose input/output (I/O) pins Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis. During output mode, pullups are disengaged. High current 10-mA sink/source capability on all port pins Higher current 15-mA sink/source capability on PTC0 PTC1 Timebase module (TBM) with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source during stop mode for periodic wakeup from stop using an external crystal User selection of having the oscillator enabled or disabled during stop mode -bit keyboard wakeup port Available packages: 2-pin low-profile quad flat pack (LQFP) 28-pin plastic dual in-line package (DIP) 28-pin small outline integrated circuit (SOIC) Specific features of the MC68HC908GR8A in 28-pin DIP and 28-pin SOIC are: Port B is only bits: PTB0 PTB; -channel ADC module No port C bits Features of the CPU08 Features of the CPU08 include: Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Efficient C language support 20 Freescale Semiconductor

21 MCU Block Diagram 1. MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GR8A. CPU REGISTERS M68HC08 CPU ARITHMETIC/LOGIC UNIT (ALU) INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE DDRA PORTA PTA/KBD PTA0/KBD0 (1) CONTROL AND STATUS REGISTERS 6 BYTES MC68HC908GR8A USER FLASH 7680 BYTES MC68HC908GRA USER FLASH 096 BYTES USER RAM 8 BYTES MONITOR ROM 10 BYTES SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE -BIT KEYBOARD INTERRUPT MODULE DDRB PORTB PTB5/AD5 PTB/AD PTB/AD PTB2/AD2 PTB1/AD1 PTB0/AD0 FLASH PROGRAMMING (BURN-IN) ROM 5 BYTES 2-CHANNEL TIMER INTERFACE MODULE 1 DDRC PORTC (1), (2) PTC1 (1), (2) PTC0 USER FLASH VECTOR SPACE 6 BYTES OSC1 OSC2 CGMXFC RST () IRQ () V DDAD /V REFH V SSAD /V REFL V DD V SS V DDA V SSA CLOCK GENERATOR MODULE 1 8-MHz OSCILLATOR PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE POWER 1-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE SERIAL PERIPHERAL INTERFACE MODULE MONITOR MODULE MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE DDRD DDRE PORTD PORTE SECURITY MODULE PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD/T1CH0 (1) PTD/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS (1) PTE1/RxD PTE0/TxD MONITOR MODE ENTRY MODULE 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins. Pin contains integrated pullup device Figure 1-1. MCU Block Diagram Freescale Semiconductor 21

22 General Description 1. Pin Assignments Figure 1-2 illustrations the pin assignments for the 2-pin LQFP. Figure 1- illustrate the pin assignments for the 28-pin DIP and 28-pin SOIC. OSC1 OSC2 CGMXFC V SSA V DDA PTC1 PTC0 PTA/KBD RST PTA2/KBD2 PTE0/TxD 2 2 PTA1/KBD1 PTE1/RxD 22 PTA0/KBD0 IRQ 21 V SSAD /V REFL PTD0/SS 5 20 V DDAD /V REFH PTD1/MISO 6 19 PTB5/AD5 PTD2/MOSI 7 18 PTB/AD PTD/SPSCK PTB/AD V SS V DD PTD/T1CH0 PTD5/T1CH1 PTD6/T2CH0 PTB0/AD0 PTB1/AD1 PTB2/AD2 2 Figure Pin LQFP Pin Assignments CGMXFC 1 28 V SSA OSC V DDA OSC1 26 PTA/KBD RST 25 PTA2/KBD2 PTE0/TxD 5 2 PTA1/KBD1 PTE1/RxD 6 2 PTA0/KBD0 IRQ 7 22 V SSAD /V REFL PTD0/SS 8 21 V DDAD /V REFH PTD1/MISO 9 20 PTB/AD PTD2/MOSI PTB2/AD2 PTD/SPSCK PTB1/AD1 V SS PTB0/AD0 V DD 1 16 PTD6/T2CH0 PTD/T1CH PTD5/T1CH1 NOTE: Ports PTB, PTB5, PTC0, and PTC1 are available only with the LQFP. Figure Pin DIP and SOIC Pin Assignments 22 Freescale Semiconductor

23 Pin Functions 1.5 Pin Functions Descriptions of the pin functions are provided here Power Supply Pins (V DD and V SS ) V DD and V SS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1- shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MCU V DD V SS C1 0.1 F + C Oscillator Pins (OSC1 and OSC2) Figure 1-. Power Supply Bypassing OSC1 and OSC2 are the connections for an external crystal, resonator, or clock circuit. See Chapter Clock Generator Module (CGM) External Reset Pin (RST) A 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor. See Chapter 1 System Integration Module (SIM) External Interrupt Pin (IRQ) V DD Note: Component values shown represent typical applications. IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Chapter 8 External Interrupt (IRQ). Freescale Semiconductor 2

24 General Description CGM Power Supply Pins (V DDA and V SSA ) V DDA and V SSA are the power supply pins for the analog portion of the clock generator module (CGM). Decoupling of these pins should be as per the digital supply. See Chapter Clock Generator Module (CGM) External Filter Capacitor Pin (V CGMXFC ) CGMXFC is an external filter capacitor connection for the CGM. See Chapter Clock Generator Module (CGM) ADC Power Supply/Reference Pins (V DDAD /V REFH and V SSAD /V REFL ) V DDAD and V SSAD are the power supply pins to the analog-to-digital converter (ADC). V REFH and V REFL are the reference voltage pins for the ADC. V REFH is the high reference supply for the ADC, and by default the V DDAD /V REFH pin should be externally filtered and connected to the same voltage potential as V DD. V REFL is the low reference supply for the ADC, and by default the V SSAD /V REFL pin should be connected to the same voltage potential as V SS. See Chapter Analog-to-Digital Converter (ADC) Port A Input/Output (I/O) Pins (PTA/KBD PTA0/KBD0) PTA PTA0 are special-function, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins. See Chapter 12 Input/Output (I/O) Ports and Chapter 9 Keyboard Interrupt Module (KBI). These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis Port B I/O Pins (PTB5/AD5 PTB0/AD0) PTB5 PTB0 are special-function, bidirectional I/O port pins that can also be used for analog-to-digital converter (ADC) inputs. See Chapter 12 Input/Output (I/O) Ports and Chapter Analog-to-Digital Converter (ADC) Port C I/O Pins (PTC1 and PTC0) PTC1 and PTC0 are general-purpose, bidirectional I/O port pins. PTC1 PTC0 are only available on the 2-pin LQFP package. See Chapter 12 Input/Output (I/O) Ports. These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis Port D I/O Pins (PTD6/T2CH0 PTD0/SS) PTD6 PTD0 are special-function, bidirectional I/O port pins. PTD PTD0 can be programmed to be serial peripheral interface (SPI) pins, while PTD6 PTD can be individually programmed to be timer interface module (TIM1 and TIM2) pins. See Chapter 17 Timer Interface Module (TIM1 and TIM2), Chapter 15 Serial Peripheral Interface (SPI) Module, and Chapter 12 Input/Output (I/O) Ports. These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. 2 Freescale Semiconductor

25 Port E I/O Pins (PTE1/RxD and PTE0/TxD) Pin Functions PTE1 and PTE0 are special-function, bidirectional I/O port pins. These pins can also be programmed to be serial communications interface (SCI) pins. See Chapter 1 Serial Communications Interface (SCI) Module and Chapter 12 Input/Output (I/O) Ports. NOTE Any unused inputs and I/O ports should be tied to an appropriate logic level (either V DD or V SS ). Although the I/O ports of the MC68HC908GR8A do not require termination, termination is recommended to reduce the possibility of static damage. Freescale Semiconductor 25