Digital Input and Output

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Jessica Campbell
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1 Digital Input and Output Topics: Parallel Digital I/O Simple Input (example) Parallel I/O I/O Scheduling Techniques Programmed Interrupt Driven Direct Memory Access Serial I/O Asynchronous Synchronous Switches Debounce Buffers Enable Decoder 2 Switch Input Normal Switch can make or break a circuit several times on a single transition e.g. 0V +5 V R Debounce Circuit + 5V +5V Switch Closed 0 V >ms Time 3 + 5V 4 Tri-State Buffer Simple Output (Example) In Out Enable When Enable is High, the Input is disconnected from the output When Enable is Low, the Input is connected to the output Latches Enable Decoder Decode Seven Segment Found in packages of - an Octal Buffer 5 6

2 I/O Scheduling Techniques. Programmed I/O Under CPU control at all times. Controlled by main program: Programmed (or polled) I/O 2 Interrupt Driven 3 Direct Memory Access (DMA) Input from Switches Test switch values Initialise NO any set? YES Special Actions 7 Programmed I/O Good and Bad Points 6522 VIA (Versatile Interface Adapter) Advantages Simple Software Simple Hardware Disadvantages Overhead of polling - Software Overhead Response not immediate Real-Time - Response of Compute System is sufficiently fast for any delay to be neglected Programmable I/O Device 6 Internal Registers 2 External Input and/or Output Ports CA CA2 PORT A PORT B CB CB2 RS0 RS RS2 RS3 Chip Enable A0 A A2 A3 R/W (φ) IRQ µ processor es 9 0 Simple I/O on VIA VIA ORA, ORB, and DDR's Use four main registers in the VIA: Memory (on Lab µproc.) C0000 ORB PORT B Output Register (ORB) PORT A PORT B Output Register (ORA) Direction Register B (DDRB) C000 ORA PORT A Direction Register A (DDRA) C0002 DDRB (outputs) a '' in a bit of DDR makes corresponding bit of Output Register an OUTPUT C DDRA (inputs) a '0' makes it an INPUT All VIA registers are bits 2 2

3 eg Simple VIA program Example 600 VIA program 'copy' VIA_ORB = 0xC0000 Output Register B VIA_ORA = 0xC000 Output Register A VIA_DDRB = 0xC0002 Direction Register B VIA_DDRA = 0xC0003 Direction Register A _main: Set up VIA clr.b VIA_DDRA Initialise PORT A to be inputs move.b #0xFF, VIA_DDRB Initialise PORT B to be outputs clr.b D0 Initialise data register D0 LOOP: Do the business move.b VIA_ORA, D0 Get the value from the switches move.b D0, VIA_ORB Store value on output LEDS jmp LOOP Do it again! 3 Programmed I/O with Handshaking Can read and write without having to consider whether there is data to be read or a device is ready to accept data written to it. Consider a simple printer that takes a finite amount of time to print a character (this time is very much greater than the processor instruction time) -> processor cannot write to printer without first ensuring that the printer is ready to receive data Printer can signal to CPU that it is READY CPU signals to printer that NEW DATA is being sent 4 Handshaking Figure Timing Diagram Output port B CB2 NEW DATA latch Ready New Port B time µcomputer system CB READY Printer CPU responds to the printer being ready by placing a new character on port B output and signalling new data Handshaking is performed independently from the CPU clock - ie asynchronously 5 6 Use: Handshaking on VIA PORT B as Output CB control line as READY CB2 control line as NEW DATA Need to set up Peripheral Control Register (PCR) on VIA x x x x x = don't care CA Control CA2 Control CB Control CB2 Control 7 READY The peripheral device signals to the VIA that it is ready to receive more data by asserting CB low. CB "READY" Falling edge of CB is recorded by VIA setting bit 4 of its Interrupt Flag Register (IFR) to. Also sets CB2 output. Need to disable interrupts by writing 7F to Interrupt Enable Register (IER) - we will discuss interrupts later Program to output alphabet to hypothetical printer follows: 3

4 Eg Printer Handshake Print Alphabet VIA_ORB = 0xC0000 Output Register B VIA_ORA = 0xC000 Output Register A VIA_DDRB = 0xC0002 Direction Register B VIA_DDRA = 0xC0003 Direction Register A VIA_PCR = 0xC000C Peripheral Control Register VIA_IFR = 0xC000D Interrupt Flag Register VIA_IER = 0xC000E Interrupt Enable Register _main: clr.b D0 Use D0 for character clr.b D Use D for checking READY Set up VIA LOOP: clr.b VIA_DDRA Initialise PORT A to be inputs move.b #0xFF, VIA_DDRB Initialise PORT B to be outputs move.b #0x0, VIA_PCR Initialise PCR move.b #0x7F, VIA_IER Disable VIA interrupts move.b #0x4, D0 ASCII 'A' Do the business move.b VIA_IFR, D read VIA interrupt flags and.b #0x0, D See if bit four is set (CB) beq LOOP If clear then loop until READY If READY then moveb D0,VIA_ORB Output character add.b #0x0, D0 and increment to next character cmp.b #0x5B, D0 Are we at the end of the alphabet? bne LOOP if not do it again 9 Programmed I/O with Handshaking Advantages: Simple hardware and software (low cost) Synchronises CPU with asynchronous events from slow peripheral devices Disadvantages: "Software Overhead" of synchronising CPU to external events Main uses: Simple systems with few I/O devices where CPU time can be traded for hardware complexity Interrupt Driven I/O CPU only responds when its attention is required by I/O device. Avoids problem with programmed I/O where multiple devices may require attention simultaneously Interrupts on 6000 (overview) These appear as three lines of the Control (input pins on the CPU chip) Interrupt IPL0 IPL IPL2 From External Devices 6000 MAIN Program Interrupt Handler a nested interrupt 2 Inputs specify an interrupt priority level between 0 and 7 0 = no interrupt request 7 = highest priority request 22 Interrupt response External device signals interrupt 2 CPU COMPLETES CURRENT INSTRUCTION 3 Push PC onto Stack Push Status Register onto Stack 4 Load PC with address of Interrupt Handler Return from Interrupt Pull Status register from Stack Pull PC from Stack 2 Resume program execution Interrupts: Good and Bad Points Disadvantages All data transfers still controlled by CPU More complex hardware and software Advantages Fast response no software polling overhead good in real-time environments

5 3. Direct Memory Access DMA Motivation: I/O techniques so far are slowed down by the CPU Output Memory CPU Input Memory CPU Bottleneck DMA avoids CPU -> Faster I/O (output) I/O (input) 25 DMA is used where large amounts of data are to be transferred at high speed. Control of the system buses is surrendered by the CPU to a DMA Controller. The DMAC is a dedicated device that controls the three system buses during the data transfer. The DMAC is optimised for one operation, data transfer. The CPU is more general purpose, it both transfers data and is a processor of information. Typical programmed I/O may take >0 times longer to transfer a byte than DMA (putting an unacceptable limit on peripheral data transfer speeds). 26 DATA DMA Operation DMA Operation Modes Memory CPU ADDRESS DMA Req DMA Ack DMAC Start Addr Word Count I/O Req I/O Ack Input/ Output ) Cycle Stealing DMAC uses the system buses when they are not being used by the CPU - usually by grabbing available memory access cycles not used by the CPU, hence name. DMA transfer requested by I/O 2 DMAC passes request to CPU 3 CPU initialises DMAC: i) Input or Output ii) Start address -> DMAC Reg iii) # of words to transfer -> Count Reg iv) CPU enables DMAC 4 DMAC requests use of system buses 5 CPU responds with DMA Acknowledge when ready to surrender system buses. 27 2) Burst Mode DMAC requires system buses for extended transfer of large amount of data at high speed and locks the slower CPU out of using the system buses for a fixed time, or until the transfer is complete, (or until the CPU receives an interrupt from a device of greater priority) 2 Serial Input / Output Two major types of serial I/O: Asynchronous 2 Synchronous Serial I/O uses a single communication channel (eg a pair of wires) to send data. Advantage over parallel I/O is that using single channel reduces cost - cheaper Disadvantage is that a single serial channel cannot carry as much information in a given time as multiple (parallel) channels - slower Use: Long distance data communications 29 Asynchronous Used to send small packets of data, typically characters, eg between computers and terminals. at transmitter (Tx) and Receiver (Rx) are only of approximately the same frequency. Synchronisation established at start of transmission and lasts only for the duration of one packet (character). Cheap, short range, used for channels with low density utilisation. Synchronous Used to send bulk data at high speeds over long distances. Synchronisation maintained by embedding clock signal in with data. Maximises use of expensive high speed data comms 30 5

6 Asynchronous Serial I/O -bit parallel data load Channel -bit parallel Rx store Asynchronous Serial Format Serial Shift Generator f = N Hz Serial Shift Generator f N Hz Synchroniser No common clock Local clocks are at approximately same frequency Once synchronisation established it can only be maintained for a short period of time 3 Start D0 D D2 D3 D4 D5 D6 D7 STOP STOP2 time Packet consists of: START Bit, always a zero 2 between 5 and data bits 3 PARITY bit, error detection (even parity shown) 4, / 2, or 2 STOP bits (force gap between packets) 5 When not active channel carries MARKING (NB data above is 00000) Parity 32 Synchronisation Baud Rate Start D0 time Falling edge of START triggers Rx circuit 2 One half bit time later the input is sampled for START 3 Sample the data at intervals of one bit time 4 Sample PARITY one bit time later: check parity bit with parity of the received data bits: error if not same 5 Sample STOP bits at intervals of one bit time. If stop bits are not one then Framing Error. b t D7 Parity STOP STOP2 33 Baud Rate of a serial line is the number of bits transmitted per second. It includes the overhead of the non-data bits. If the bit time, b t, is the time for one bit then: Baud Rate = Often clock rate applied to serial communication circuits is or 6 times higher than the baud rate. There may be many samples taken per bit time rather than the single sample indicated previously. b t 34 Typical Use of Asynchronous Serial Communication Synchronous Serial Communication ACIA Tx data Rx data Control REMOTE TERMINAL keyboard + CRT Communication distance ~ tens of metres 35 Serial & Generator Channel & Separation Serial and data are combined into one signal Serial data is synchronised by transmission of special bit patterns Once synchronised many bits may be transmitted (multiple characters at once) 36 6

7 Synchronous Serial Format Example - Phase Coding Each data value of: is replaced by a positive transition, and 0 is replaced with a negative transition can be extracted from transitions. Example I/O RS 232C Mark below -3 Volts (typically - 2 V) 0 Space above +3 Volts (typically +2 V) NB Voltages need converting buffers (to 0V and 5V). Phase Coded D0 D D2 D3 D4 D5 D6 D ISDN (Integrated Services Digital Network) - standard for transmitting audio, video and data (c960), can achieve 600Mbits/s using fibre. ATM (Asynchronous Transfer Mode) - uses packets of 53 bytes, works at 55Mbits/s and upwards

6 Direct Memory Access (DMA)

6 Direct Memory Access (DMA) 1 License: http://creativecommons.org/licenses/by-nc-nd/3.0/ 6 Direct Access (DMA) DMA technique is used to transfer large volumes of data between I/O interfaces and the memory. Example: Disk drive controllers,