MODULE 12 APPLICATIONS OF MEMORY DEVICES:

Transcription

1 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 1 MODULE 12 APPLICATIONS OF MEMORY DEVICES: CONCEPT 12-1: REVIEW OF HOW MEMORY DEVICES WORK Memory consists of two parts. There are the individual memory cells or the little pockets of 1s and 0s that make up the data, and the logic that accesses the different memory cells. The Logic that accesses the memory cells is a matrix of "Decoder" lines where each line decodes an individual block of data. The data blocks can be single bytes or 8 bits, 16 bit words, 32 bit double words, etc. Each Decoder line effectively connects one data block to the external data bus (the outside world). Figure 1 below shows the block diagram of a typical memory device. Notice that the address bits select the individual data lines that correspond to a block or in this case a row of data. FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MEMORY DEVICE The individual memory cells can be anything that when selected, can pull the decoded data line to a logical 1 or 0. This gives rise to several different types of Memory. In general, there are two classes of memory, Read Only Memory (ROM) which means just that. The memory cannot be rewritten. It will always be the same, even after the devices is powered off and back on again. This makes ROM devices "NON-VOLATILE". Similarly, program data stored in such a device is called "FIRMWARE" because it will not go away when the device is powered down. The simplest ROM memory cell is just a diode matrix. If the diodes are put in when the memory is manufactured, it can only be programmed with what it comes with from the manufacturer. By adding fused connections to a separate diode at each bit location, the fuses can be burned open at each location where the designer desires a logical 1. This device, shown in Figure 2 below, is a Programmable Read Only Memory (PROM).

2 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 2 FIGURE 12-2: A MATRIX OF PROGRAMMABLE READ ONLY MEMORY CELLS If the fused link is substituted for transistor switch, two designs can be realized. Controlling the switch can make the bit cell soft programmable and each cell can be written to or read from. This type of readable/writeable memory is call "Random Access Memory" or (RAM). The name is a little confusing since both RAM and ROM are random accessible but RAM will hence forth mean memory you can both read and write to on the fly. The single transistor version of RAM actually stores its memory as charge on the MOS transistor gate. In time the charge can bleed off and the memory cell can forget what it is. If it is periodically accessed or read, it refreshes itself and the gate charge build back up. This is called Dynamic RAM or (DRAM) because it must be refreshed about every 10 ms. In computer time compared to our time it would be like us having to read the memory once every hundred years. Figure 3 shows a typical DRAM memory cell. FIGURE12-3: A TYPICAL DYNAMIC RANDOM ACCESS MEMORY CELL (DRAM) If the same DRAM memory cell has a small metal plate or "buried gate" placed just under the main MOS transistor control gate as shown in Figure 4, the "buried gate" can be charged externally but the charge does not bleed off but is trapped and will stay there for hundreds of years. The cell will be programmed with the MOS transistor that switches the diode high or low, held at a logical 1 or 0 according to the trapped charge. To erase the trapped charge, the junction is flooded with ultra violet light that breaks up the trapped charge and clears the bit cell. This type of Read Only Memory shown in Figure 4, is called Erasable Programmable Read Only Memory of (EPROM).

3 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 3 FIGURE 12-4: ERASABLE PROGRAMMABLE READ ONLY MEMORY It was later discovered that by not burying the "buried gate" quite so deep in the MOS transistor, the trapped charge could be changed by an external electric field. This gave rise the the next generation of ROM, Electrically Erasable Programmable Read Only Memory or (EEPROM). FIGURE 5 shows the last type of memory device will discuss in this module overview, Static Random Access Memory or (SRAM). An SRAM uses a transistor flip flop in each memory cell. This means that the cell which can be written to or read at any time, does not need to be refreshed to retain its data. This type of memory is typically faster and does not need refreshing but as you can see in figure 5, it requires about six transistors. The added complexity raises the price of this type of memory proportionally. If the transistor are CMOS types transitors, the amount of current each memory cell requires is in the pico- Amperes. This makes it possible to keep the memory alive with a little battery. Many computers use CMOS memory to retain data such as time, data, and computer set up configuration. FIGURE 12-5: STATIC RANDOM ACCESS READ ONLY MEMORY

4 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 4 CONCEPT 12-2: DECODING AND MAPPING MEMORY INTO A COMPUTER Computers have a finite memory space based on the number of address bits the computer puts out on the address bus. A typical microprocessor used to control piece equipment will have sixteen address bits. Sixteen bits can address up to address locations. If a microcomputer with a sixteen bit address bus uses memory devices with 8K X 8 bytes of data, it can support up to eight of these devices. Each of the eight memory devices must connect in parallel to the same data input/output bus. This requires each to be electrically disconnected when not being directly addressed. This is accomplished by using a memory decoder device which only allows one of the 8K X 8 memory devices to be connected to the data bus at a time. The memory address decoder uses the three highest order address bits to divide the 64K memory space up into eight 8K X 8 blocks of memory space. The decoder outputs go to the Chip Select, (CS), inputs on the memory devices. When the CS line on a memory device is pulled low by the decoder, that device is electrically connected to the computer data bus and that memory device is enabled. The address locations where each of these devices is located is called a Memory Map. The figure below illustrates this how memory is populated and assigned by using a 74LS138 1 of 8 decoder. FIGURE 12-6: MEMORY DECODING ON A MICROCOMPUTER BUS

5 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 5 FIGURE 12-7: MEMORY MAP FOR 64K MICROPROCESSOR CONCEPT 12-3: DESIGNING ROM CONTROLLERS A read only memory (ROM) can be programmed and used as a state machine. One output bit is used for each desired state variable. The remainder of the output bits can be used as control bits. If three bits of an eight bit ROM are fed back as state variables, the ROM controller can cycles through eight states and output five control bits. The three state variable bits go to a latch that holds them until the latch is clocked. The state variables then go to the lower order address input bits on the ROM. In this way the output state variable bits are used to cause the machine to sequence. The most powerful thing about the ROM controller is that the rest of the unused ROM address input bits can be used as input variables and each combination of input bits and redirect the ROM controller to a totally unique program path. For designs that require more than eight output bits, several ROMs can be connected in parallel with the same address and control inputs. If two ROMS are connected together in this manner, the outputs can be then used like a ROM with sixteen output bits instead of just eight. The best way to understand how to design a ROM controller is to go through a design step by step. The following is the design of a combination lock. The lock requires a sequence of three HEX characters (4 bits) that must be given in the correct order. It will tolerate one mistake per character and will give out a warning. Two mistakes in a row will set off an alarm. The combination lock state machine has eight states or requires three state variables fed back to the ROM controller address inputs. It outputs four control signals. One is a Ready light by the HEX number entry key pad. The next is a yellow warning light. The third is an alarm signal. The fourth unlocks the door. The block diagram of the combination lock is shown below in figure 12-8.

6 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 6 FIGURE 12-8: BLOCK DIAGRAM OF A ROM CONTROLLER The ROM controller uses a state path very similar to the ones we have used to design state machines using AND OR logic. The only difference is the Present State Next State sequence is programmed in as an Address Data out sequence where the external control bits go into the address inputs and change the ROM output path by changing its address. This is all formally set

7 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 7 up and planned by first making a State Graph just like we have done before and then mapping it into a State Table designed especially for ROM controllers. FIGURE 12-9: COMBINATION LACK STATE GRAPH Each state has two paths, one for a correct response and the other for an error. We can assume that if no entries happen for a fixed time, the system resets itself to S0. We can also assume that the combinations are build into the lock program in a special combination ROM that is addressed by the same state variables as the controller ROM. If the controller ROM is also a 32K X 8 EPROM, it can hold up to 4096 different combinations. Each employee of a small company could have their own unique combination. This way a record could be kept of who unlocked the door. The next thing to do is to create the State Table. This uses the controller ROM output to generate the next state as state variables A0, A1, and A2. A3 is the external input which is equal to 1 if the entry is correct, and 0 if the entry is incorrect. Outputs O4, O5, O6, and O7 are used to generate the Ready, Warning, Alarm, and the Unlock signals. The Table is generated below:

8 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 8 FIGURE 12-10: ROM CONTROLLER STATE TABLE

9 Introduction to Digital Electronic Design, Module 12 Application of Memory Devices 9 The ROM controller is programmed with the above bytes in its active program memory as: K X 8 EPROM ADDRESS DATA A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 (Address bits A14 thru A4 select a control program.) X X X X X X X X X X X X X X X X Most EPROM programmers allow the user to program in any desired data into the memory cells. This is typically done as a matrix of bytes originated at the address of interest. If we were using the very first 16 address locations in the EPROM to put our program, address bits A14 throught A4 would all be 0 s and the above table of data would fill the first sixteen data memory locations. Notice that since D3 is not used in our design, it is an X which means it can be a 1 or a 0.