PCI Express Signal Quality Test Methodology

Transcription

1 PCI Express Signal Quality Test Methodology Users Guide LeCroy SDA 6000 October 2003 Revision 0.7 Document Number: XXXX

2 DISCLAIMER OF WARRANTIES THIS SPECIFICATION IS PROVIDED AS IS AND WITH NO WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, NO WARRANTY OF NONINFRINGEMENT, NO WARRANTY OF MERCHANTABILITY, NO WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE, NO WARRANTY OF TITLE, AND NO WARRANTY ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE, ALL OF WHICH WARRANTIES ARE EXPRESSLY DISCLAIMED. WITHOUT LIMITING THE GENERALITY OF THE FOREGOING, INTEL CORPORATION AND THE AUTHORS OF THE SPECIFICATION DO NOT WARRANT OR REPRESENT THAT USE OF THE SPECIFICATION WILL NOT INFRINGE THE INTELLECTUAL PROPERTY RIGHTS OF OTHERS. USERS OF THE SPECIFICATIONASSUME ALL RISK OF SUCH INFRINGEMENT, AND AGREE THAT THEY WILL MAKE NO CLAIM AGAINST INTEL CORPORATION OR THE AUTHORS IN THE EVENT OF CLAIMS OF INFRINGEMENT. INTEL CORPORATION IS NOT LIABLE FOR ANY CONSEQUENTIAL, SPECIAL OR OTHER DAMAGES ARISING OUT OF THE USE OF THE SPECIFICATION. LICENSE FOR INTERNAL USE ONLY INTEL CORPORATION HEREBY GRANTS A LICENSE TO REPRODUCE AND TO DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, IS GRANTED HEREWITH, AND NO LICENSE OF INTELLECTUAL PROPERTY RIGHTS IS GRANTED HEREWITH. All product names are trademarks, registered trademarks, or service marks of their respective owners. 2 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

3 Contents 1 Introduction PCI Express Signal Quality Test Plan Required Equipment Test Software Installing SIGTEST Calibrating the Digital Storage Oscilloscope Test Procedure Connecting the Signal Quality Load Board Transmitter Signal Quality Test Appendix A Appendix B PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 3

4 Figures Figure 1-1 Connectors Example Figure 1-2 General Connection Example... 9 Figure 2-1 Sigtest Installation Example Figure 2-2 Sigtest Installation Example Figure 2-3 Sigtest Installation Example Figure 2-4 Sigtest Installation Example Figure 2-5 Sigtest Installation Example Figure 2-6 Sigtest Installation Example Figure 2-7 Sigtest Installation Example Figure 3-1 Auto Calibration Figure 3-2 Deskew Connections Figure 3-3 Deskew Menu Figure 3-4 Channel Skew Figure 3-5 Skew Minimized Figure 4-1 SMA Probing Option Figure 4-2 Resistor Terminations for Lanes without SMA Probing Figure 4-3 Connecting Up the PCI Express Signal Quality Test Fixture Figure 4-4 Compliance Baseboard (CBB) Add-in Card Fixture Figure 4-5 CBB SMA Probing Option Figure 4-6 CBB Active Probing Option Figure 4-7 Waveform Clipping Example Figure 4-8 Vertical Setup Menu Figure 4-9 Waveform Example Figure 4-10 Setup to Export CSV Figure 4-11 Opening the SIGTEST User GUI Figure 4-12 Signal Quality Eye Rendering Program Main Menu Figure 4-13 Import the CSV Data File Figure 4-14 Verify Data Button Figure 4-15 Error Window Example Figure 4-16 Template Choices Figure 4-17 TEST Button Figure 4-18 Results Screen Figure 4-19 Results Button Figure 4-20 Worst Non Transition Eyes Button Figure 4-21 Non Transition Eyes Figure 4-22 Worst Transition Eyes Button Figure 4-23 Transition Eyes Figure 4-24 Voltage Data Button Figure 4-25 Voltage Data PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

5 Revision History Document No. Rev. No. Description Rev. Date <XXXX> 0.3 Initial Draft Updated for SigTest 2.0 Beta Formatting and minor updates PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 5

6 This page is intentionally left blank. 6 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

7 Introduction 1 Introduction 1.1 PCI Express Signal Quality Test Plan The PCI Express Signal Quality Tool was developed to help verify product compliance to the PCI Express Base Specification and CEM Specifications. The PCI Express Signal Quality Tool consists of a series of tests used to evaluate PCI Express systems/motherboards and PCI Express add-in card products. The test tool kit contains the following components: PCI Express Signal Quality Test Methodology documentation SIGTEST Post Capture Analysis Software Intel s Signal Quality Load Board / PCI Express Compliance Load Board Test Fixture Oscilloscope Configuration Files Sample PCI Express Test Data This document contains the PCI Express Signal Quality Test Procedure for gauging the signal quality of implemented designs. The following sections will contain detailed procedures on calibrating test equipment and setting up the Signal Quality Load Board as well as information on how to use the SIGTEST post analysis software. Sample outputs will also be provided for reference. Note: The tests described in this document are intended to provide a quick check of the electrical health of the DUT. This testing is not a replacement for an exhaustive test validation plan. 1.2 Required Equipment Intel does not endorse any particular tool vendor. The list of equipment cited in this example is for reference purposes only. The test methodology contained in this document was developed using the following test equipment: Real Time Digital Storage Oscilloscope o o Any Real Time Digital Storage Oscilloscope with a minimum 6 GHz bandwidth and capable of a sampling rate of 20GS/s (50 ps sample interval) can be used. This document was developed using the LeCroy SDA GS/s Digital Storage Oscilloscope SMA interface option for signal inputs to scope o This document was developed using LeCroy Model LPA-SMA, qty = 2 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 7

8 Introduction Active or differential probes o For best results the probe bandwidth must be much greater than that of the signal being measured. o This document was developed using D600 LeCroy 6 GHz active probe, qty = 2 50-ohm Coax Cable With SMA Male Connectors 24-inch or less RG316/U or similar (2 sets of matched length pairs) SMA T-adapter BNC to SMA male adapter Test PC Computer Minimum configuration of Intel Pentium III 700MHz with 256MB memory or equivalent loaded with Microsoft Windows XP Professional or 2000 Professional operating system. Figure 1-1 Connectors Example 1 Although this test methodology document features the LeCroy SDA 6000 (the "test scope"), equivalent 3rd party scopes and probes can be substituted. 8 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

9 Introduction Figure 1-2 General Connection Example PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 9

10 Test Software 2 Test Software 2.1 Installing SIGTEST SIGTEST is the post analysis software packaged with the PCI Express Signal Quality Tool. Data captured with the Digital Storage Oscilloscope is imported into this software for analysis. SIGTEST is capable of rendering the signal quality eye captured with the Digital Storage Oscilloscope. The eye is then checked against the specified pass/fail boundaries. OS Requirements: Microsoft Windows XP or Windows 2000 Professional operating system is required. 1. Open the subdirectory that the Test Tool installation file was copied to. Figure 2-1 Sigtest Installation Example 1 2. Double click on SigTest 2.0 Beta.msi. 10 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

11 Test Software Figure 2-2 Sigtest Installation Example 2 3. Make sure there are no Windows programs running in the background. Click Next to begin the installation. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 11

12 Test Software Figure 2-3 Sigtest Installation Example 3 4. Read the license agreement and select accept. Click Next to continue. 12 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

13 Test Software Figure 2-4 Sigtest Installation Example 4 5. Read the release notes by using the right scroll bar. Click Next to continue. Figure 2-5 Sigtest Installation Example 5 6. Choose the destination directory and click Next to continue. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 13

14 Test Software Figure 2-6 Sigtest Installation Example 6 7. Click Next to begin the installation. 14 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

15 Test Software Figure 2-7 Sigtest Installation Example 7 8. Click Finish to complete the installation. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 15

16 Calibrating the Digital Storage Oscilloscope 3 Calibrating the Digital Storage Oscilloscope Internal Diagnostic and Calibration Cycle: 1. Allow the Digital Storage Oscilloscope to warm up for at least 20 minutes. 2. The SDA 6000 performs its own calibration, both at turn-on and throughout the use of the scope. No formal procedures are needed for calibration. Vertical Input Calibration: The SDA 6000 performs calibration both at turn-on and during use of the instrument. Autocalibration is performed automatically when instrument temperature changes occur. Confirm this Automatic Calibration feature is enabled within the Preferences Menu. Figure 3-1 Auto Calibration Auto-calibration is automatically completed when selections of vertical attenuation and time base settings are made. Channel De-skew: 1) Connect the matched SMA coax cable pair, one to Channel 2 and one to Channel PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

17 Calibrating the Digital Storage Oscilloscope 2) With the use of SMA to BNC adaptors, connect both Channel 2 & 3 inputs to the BNC T-adaptor. Connect this to the SDA6000 s AUX OUT jack. Refer to the figure below for reference. Figure 3-2 Deskew Connections 3) Load the SDA6000 deskew setup from the File, Recall Setup menu. Press the Browse button to find the file named LeCroy_SMA_Deskew.lss, select it, then press Recall Now. A falling edge of the 5 MHz square wave is shown in a 500ps/div horizontal scale. The upper portion of the screen shows channel 2 and channel 3 superimposed on one another. The lower portion of the screen is the differential signal of channel 2 minus channel 3. The top two traces provide for visual inspection of relative time skew between the two channels. The bottom trace provides for visual presentation of unwanted differential mode signal resulted from relative channel skew (and to a much lesser extent from inevitable other channel mismatch parameters like gain and non-linearity). 4) From the Vertical_Channel 3 Setup menu, select Deskew and adjust it until the skew is minimized. Refer to figures below. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 17

18 Calibrating the Digital Storage Oscilloscope Figure 3-3 Deskew Menu Figure 3-4 Channel Skew Figure 3-4 shows Channel 3 skewed relative to Channel 2 and the Math trace is the difference between both of these input channels. 18 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

19 Calibrating the Digital Storage Oscilloscope Figure 3-5 Skew Minimized Figure 3-5 shows Channel 3 deskewed to Channel 2 and the Math trace is the difference between both of these input channels. Once de-skewing is complete, the matched pair of RG-316 SMA cables should not be swapped during the electrical tests PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 19

20 Test Procedure 4 Test Procedure 4.1 Connecting the Signal Quality Load Board There are multiple pairs of SMA connectors on the PCI Express Signal Quality Test Fixtures. Each pair maps to the transmit differential pair or receive differential pair for the Add-in Card or System/motherboard transmitter lane under test. For System/motherboard testing: 1. With the system/motherboard powered off, connect the Compliance PCI Express Signal Quality Load Board into the connector under test. The PCI Express Signal Quality Load Board has edge fingers for x1, x4, x8 and x16 connectors. Not all lanes have SMA probing options. For signal quality testing of the remaining lanes you will need to use high bandwidth differential or single ended probes. Minimum recommended BW of 6 Ghz. 2. The PCI Express Signal Quality Load Board will cause a PCI Express 1.0A Base Specification System/motherboard to enter the compliance sub-state of the polling state. During this state the device under test will repeatedly send out the compliance pattern defined in the PCI Express Base Specification. Figure 4-1 SMA Probing Option 20 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

21 Test Procedure Figure 4-2 Resistor Terminations for Lanes without SMA Probing 3. Connect cables up as follows: a. For a system/motherboard connector as the device under test connect 1. Digital Storage Oscilloscope to channel 2 TX LANE 1 P (where Lane 1 is under test) 2. Digital Storage Oscilloscope to channel 3 to TX LANE 1 N (where Lane 1 is under test) Figure 4-3 Connecting Up the PCI Express Signal Quality Test Fixture For Add-in Card testing: 1. With the Add-in card fixture power supply powered off, connect the power supply connector to the Add-in card test fixture, and connect the device under test add-in card to the by-16 or by-1 connector slot. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 21

22 Test Procedure Figure 4-4 Compliance Baseboard (CBB) Add-in Card Fixture 22 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

23 Test Procedure Figure 4-5 CBB SMA Probing Option 2. Connect cables up as follows: a. Digital Storage Oscilloscope to channel 2 TX LANE 1 P (where Lane 1 is under test) b. Digital Storage Oscilloscope to channel 3 to TX LANE 1 N (where Lane 1 is under test) Note: The CBB labeled PCITX Rev silkscreen incorrectly labels the add-in card transmitter probing locations as RX. 3. Connect adequate load to the power supply to assure it is regulating and turned on. Generally one IDE hard drive will provide adequate load. 4. Turn on the power supply. DS1 LED should turn on. If the LED is on, but the power supply does not turn on, check that the jumper J7 is installed between J7-1 and J7-2. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 23

24 Test Procedure Figure 4-6 CBB Active Probing Option 4.2 Transmitter Signal Quality Test 1. Verify the Digital Storage Oscilloscope is armed. The Normal button should be lit. 2. On the Digital Storage Oscilloscope load the LeCroy_PCIE_SMA_M2_CH23_Test1_5.lss setup file using the Recall Setup function: If this setup file is not available refer to Appendix B for a list of detailed steps. 3. Maximize the waveform vertical setting if necessary to take advantage of the full range of the scope display. Note that the waveform should not extend beyond the vertical display boundaries. 24 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

25 Test Procedure Figure 4-7 Waveform Clipping Example a. If the signal vertical scale needs to be adjusted go to the Vertical Setup menu. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 25

26 Test Procedure Figure 4-8 Vertical Setup Menu b. Select Vertical, Channel 2 Setup, and choose the Volts / div setting that uses the full vertical range without clipping the waveforms. Check Variable Gain if necessary. 1. Use the same setting for both channel 2 and channel In the Math, F1 Setup set the Vertical scale/div to be twice the C2 and C3 Volts/div. The waveforms should appear as follows 26 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

27 Test Procedure Figure 4-9 Waveform Example 3. Close the menu to maximize the display. 4. Press the Normal button to stop the data acquisition. It should acquire a transmitted differential signal as in Figure 4-9. a. Using the LeCroy_SMA_M2_CH23_Test1_5.lss setup file, the SDA 6000 captured a depth of 10us at 20 GS/s acquisition rate. This provides about 25,000 Unit Intervals of PCI Express samples. 5. Save the captured sample as a Comma Separated Value (CSV) file: a. Select Save Waveform from the File dropdown menu. b. Select Format: Excel, SubFormat: With Header, in the Data Format section of the menu. c. Select F1 in the Source field. d. Type a descriptive title into the Trace Title field. The file name will be F1 followed by your trace title, followed by for the first file stored, with a.csv extension. e. The destination directory is D:\Waveforms\ by default; there is no need to change it. f. Click the Save Now button at the bottom right of the menu. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 27

28 Test Procedure Figure 4-10 Setup to Export CSV 6. Copy the saved CSV file to a desired folder in the computer with the PCI Express Signal Quality Eye Rendering Program (SIGTEST). 28 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

29 Test Procedure 7. Invoke SIGTEST (PCI Express Post Capture Analysis Software). Figure 4-11 Opening the SIGTEST User GUI PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 29

30 Test Procedure Figure 4-12 Signal Quality Eye Rendering Program Main Menu 8. Click the Data File Browse button to locate the folder where the captured CSV file is located. Select the CSV file to be processed. Figure 4-13 Import the CSV Data File a. If time stamps are included in test data, select that check box option. b. For a single differential data file uncheck Separate Files Per Channel. (This procedure shows the single differential data file case). 30 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

31 Test Procedure 9. Click the verify data button. This runs some quick checks to see if valid test data was selected. Figure 4-14 Verify Data Button a. If the data is the correct format the TEST button will become selectable. Otherwise, it will report Unable to process data file. in the program status bar at the bottom of the screen. Additionally the following error window will be displayed: Figure 4-15 Error Window Example 10. Select the Test All check box unless you are debugging test failures. 11. In the Template File selection window, select the template that corresponds to the probing location template that you wish to test to. a. For add-in card testing, select the PCIEX_TX_ADD_CON_250UI template. b. For system testing, select the PCIEX_TX_ADD_CON_250UI template. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 31

32 Test Procedure Figure 4-16 Template Choices Click on the TEST button Figure 4-17 TEST Button 32 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

33 Test Procedure When the program is finished analyzing the test data a results window is displayed. Figure 4-18 Results Screen The program status bar at the bottom of the screen also should indicate the following: The eye violations field indicates the number of data points that fall within the eye pattern exclusion areas (Red Zones in eye plots). The other fields are direct calculations of parameters obtained from the test data. The radio buttons next to the results field will be green if the item is within the limits set in the template file. The button will be red if they item fails. The values in the template file can be defined by the user to accommodate the probing location (for example, transmitter eye diagram) and any margin the designer wishes to test for. If closed, the results window can be recalled by clicking on the Results button. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 33

34 Test Procedure Figure 4-19 Results Button Selecting the View HTML Report button in the results screen will open the report that is generated by the SIGTEST tool. This report includes an eye diagram plot of the worst non transition signal eye, worst transition signal eye, the signal data plot and the following test summary: 34 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

35 Test Procedure Selecting the Worst Non Transition Eyes button will allow you to view the eye diagrams for deemphasized bits (data bits that do not follow a transition of the data lines). Figure 4-20 Worst Non Transition Eyes Button Figure 4-21 Non Transition Eyes The non-transition and transition eye pattern windows have 6 display options. The View All Eyes display is the default option and is an overlay of all of the other 5 eye patterns that can be PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 35

36 Test Procedure selected. Each of the 5 worst case eye patterns are created from the 250 UI of continuous data. The data is the center 250 UI within a 3500 UI window of the exported scope record. The individual eye diagrams can be viewed separately or all together by clicking on the appropriate button at the bottom of the screen. Selecting the Worst Transition Eyes button opens the transition eye display. Figure 4-22 Worst Transition Eyes Button 36 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

37 Test Procedure Figure 4-23 Transition Eyes Selecting the Worst Transition Eyes button will allow you to view the eye diagrams for the bits following a transition in the differential signal. Note that the specification defines different eye template requirements depending on whether the data is a transition or non-transition (deemphasis) bit. The individual eye diagrams can be viewed separately or all together by clicking on the appropriate button at the bottom of the screen. Selecting the WORST JITTER button displays the eye pattern associated with those transitions that have the worst case jitter on them for all of the test data that was analyzed. In general, one should expect the jitter of a transition bit to be the worst case since the voltage of the signal prior to the transition can vary depending on whether it was a de-emphasized bit or not. Selecting the Voltage Data button displays the differential signal voltage for the test data that was analyzed. PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 37

38 Test Procedure Figure 4-24 Voltage Data Button Figure 4-25 Voltage Data Repeat the process for all other Lanes to be tested. 38 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >

39 Appendix A 5 Appendix A LeCroy_SMA_DESKEW.LSS setup file details: Horizontal Setup Smart Memory Vertical C2 and C3 Trigger Function 1 Sample Mode: Real Time, Active Channels: 2, Delay: 0 ns, Time/div 500ps Time base mode: Set Maximum Memory, 1MS 50mV/div, Offset: -175mV. Coupling: DC Impedance 50 ohms Edge trigger, trigger mode: Auto, Trigger On: channel 2, trigger level +175mV, Slope: Negative. Operator: Difference; Source1: C2, Source2: C3. Vertical Scale: 20mV/div, Offset: 0mV PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX > 39

40 Appendix B 6 Appendix B LECROY_PCIE_SMA_M2_CH23_Test1_5.LSS setup file details: Horizontal Smart Memory Vertical C2 and C3 Trigger Function 1 Function 2 Function 6 Function 7 Sample Mode: Real Time, Active Channels: 2, Delay: 0 ns, Time/div 500ps Time base mode: Set Maximum Memory, 1MS (in this mode, due to the Horizontal settings, acquisition size is 200,000 samples at 20GS/s, automatically). 50mV/div, Offset: -175mV. Coupling: DC Impedance 50 ohms Edge trigger, trigger mode: Auto, Trigger On: channel 2, trigger level +0mV, Slope: Negative. Operator1: Difference; Source1: C2, Source2: C3. Vertical Scale/div: 100mV, Offset: 0mV Operator1: Zoom, Source1: F1, Horizontal Center: 0ps, scale/div: 500ps; Vertical Center: 0mV, scale/div 100mV Operator1: Zoom, Source1: C2, Horizontal Center: 0ps, scale/div: 500ps; Vertical Center: 0mV, scale/div 50mV Operator1: Zoom, Source1: C3, Horizontal Center: 0ps, scale/div: 500ps; Vertical Center: 0mV, scale/div 50mV 40 PCI Express Signal Quality Test Methodology, Rev 0.7 XXXX >