Enabling Intelligent Digital Power IC Solutions with Anti-Fuse-Based 1T-OTP

Transcription

1 Enabling Intelligent Digital Power IC Solutions with Anti-Fuse-Based 1T-OTP Jim Lipman, Sidense David New, Powervation 1 THE NEED FOR POWER MANAGEMENT SOLUTIONS WITH OTP MEMORY As electronic systems gain in complexity, the complexity of the system s power management hardware and software to efficiently and accurately deliver electrical power to the various system components also rises. Digital Power Management Integrated Circuits (PMICs) are becoming commonplace in today s systems to convert unregulated voltages derived from batteries, power lines or other sources, to protected voltage regulators for a variety of loads, including general POL, VCORE and memory. Network, communications and computing systems are examples of systems with very critical power management requirements. For example, such systems often have multiple power supplies per product board with a wide range of current and voltage requirements to power general POLs, ASICs, FPGAs, processors (particularly processor core voltages), and memory. Often these power supplies run for extended time periods without power cycling and often run in environments with elevated temperatures. Digital power-management controller chips designed for these environments must be dependable and high performance. These controller chips have many needs for reliable, field-programmable non-volatile memory (NVM) storage for program code, DSP coefficients, configuration parameters and security codes. Sidense 1T-OTP memory IP, combining high security, high reliability, low cost, field-programmability, high density and low power dissipation, is an ideal fit for these applications and offers several advantages over other OTP memory technologies such as flash, efuse, and ROM. 2 POWERVATION TECHNOLOGY Powervation uses a multiprocessor SoC architecture for its digital power management solutions. The architecture comprises a proprietary dual core (DSP and RISC) processor, both RAM and Sidense 1T-OTP NVM, power conversion blocks, an SMBus serial interface, DSS bus, analog-to-digital converters (ADCs), digital-to-analog converter (DAC), and oscillator and phase-lock-loop (PLL) timing sources. The DSP core is used to solve complex algorithms, such as Powervation s Auto-Control s real-time loop compensation, while the RISC processor provides fast instruction execution while eliminating unneeded overhead and the power dissipation of other processing schemes. The dual-core architecture provides the processing power needed for power management and switched-mode power supply algorithms, and enables a unique voltage regulator for applications that demand high stability and high efficiency. Both cores use Sidense 1T-OTP NVM to store DSP coefficients and RISC configuration parameters. Program code and PMBus parameters are stored in the NVM. On device power-up, the contents of the 1T-OTP NVM are loaded to the RAM for fast access by the processors. August 2013 Copyright 2013 Powervation Ltd. 1

2 Differential Output Voltage Sense Differential Output Current Sense Input Voltage Sense Multi-Processor SoC Digital Power Management Architecture Short Current Protection (SCP) Supply, Bandgap, Reference, LDO Digital Stress Share (DSS TM ) Bus Digital Pulse Width Modulator (DPWM) ADC DSP Temperature Sense (Internal/External) RISC Auto-Control Power/Fault Management Temperature Correction Single Pin Configuration RAM Firmware SMBus Serial Interface (PMBus TM Compliant), SVID RCONFIG Voltage Tracking Anti-Fuse Based Non-Volatile Memory (NVM) Oscillator/PLL Synchronization Figure 1: Powervation Digital Controller Architecture Auto-Control is a real-time adaptive loop compensation technology for switching power converters. The technology is designed to autonomously balance the tradeoffs between dynamic performance and system stability. Auto-Control, embedded in the control architecture of Powervation devices, adjusts proportional-integral-derivative (PID) coefficients each switching cycle to continuously achieve optimum stability over a wide range of disturbances. The continuous nature of Auto-Control allows it to manage system changes that occur in real time, or slowly over time while the power supply is in use. Auto-Control s real-time, self-adaptive loop provides a key advantage for server and other applications that continually run and rarely power cycle, and for those that use efficiency maximization techniques like phase add/drop where the effective output impedance changes significantly as the load current varies. The Auto-Control technology can continuously adjust according to changes in temperature that occur while the power supply is in use, and compensates for other factors such as aging and drift. The Digital Stress Share (DSS) bus is a proprietary single-wire digital communication bus for the interconnection of multiple paralleled digital control ICs. DSS is a combination of a master/slave current sharing architecture with a quasi-democratic average current determination. Active phase current balance provides asymmetric current sharing to help eliminate hot spots and the devices participating in DSS gain knowledge of the highest and lowest stressed device and adjust control to match the average system stress. DSS helps improve efficiency, simplify thermal management, improve reliability, and provide a higher level of redundancy. Manufacturer-specific PMBus commands can be used to configure a variety of parameters relating to DSS. The Powervation mixed-signal digital power management controller combines power management and mixed-signal functions and is able to store and run computational algorithms in firmware. The architecture also allows the digital controllers to be extremely flexible in their configuration and for users to easily store in Sidense 1T-OTP memory a large number of parameters used in the design of switch-mode power supplies, thus maximizing configuration flexibility while eliminating external components. August 2013 Copyright 2013 Powervation Ltd. 2

3 3 1T-OTP IN POWERVATION PRODUCTS Powervation s digital power management SoC products use two types of memory to perform the functions needed for their features and to provide for users. Firmware and DSP code, along with security codes and design and user-specific configuration parameters for the voltage regulator, are stored in Sidense 1T-OTP. Firmware & DSP Block Standard Configuration Storage Security Single Pin CONFIG Storage Block (8 Tables) NVM Block Figure 2: NVM Block Partitioning When the device is powered on, the contents of the OTP memory are loaded to a RAM for fast access to the processing unit. 1T-OTP provides long-term storage of vital code that determines power supply functionality, so it is crucial that this memory be reliable. An anti-fuse-based Split-Channel bit-cell architecture (1T-Fuse ) in 1T-OTP minimizes bit-cell area (and its impact on total chip area) while allowing the memory to be fabricated in standard CMOS processes with no additional masks or process steps, and thus no extra processing cost. Figure 3: The 1T-Fuse Bit Cell is a Patented Split-Channel Architecture that Forms the Basis for Secure and Reliable Embedded OTP Memory Macros August 2013 Copyright 2013 Powervation Ltd. 3

4 Programming the bit-cell from a 0 to a 1 is done using an integrated charge pump that runs off the normal chip voltages. The programming is controllable, irreversible and field-programmable. All programming occurs in the transistor's channel region for high reliability and repeatability. 4 SINGLE-PIN CONFIGURATION TECHNOLOGY Powervation s single-pin CONFIG technology is a highly flexible configuration input that can greatly improve supply chain inventory management. With a single resistor, the user can fully configure a controller for its use in the desired switch mode power supply (SMPS). Additionally, by simply providing a different resistor, the controller can be fully configured per the needs of an alternative design. This technology provides the user access to eight configuration tables within the chips s OTP memory. V IN f SW = 750 khz f SW = 500 khz Master SYNC Line V OUT = 1.2 V OVP = 1.44 V OCP = 25 A f SW = 500 khz Slave DSS Bus V OUT = 0.8 V OVP = 0.96 V OCP = 120 A Figure 4: Interconnection of Multiple Controllers Using DSS Configuration settings are determined during the device s start-up process; in order to minimize controller power consumption, the configuration measurement currents are turned off during normal operation. Device settings determined through the configuration table resistor may be overwritten subsequently by settings retrieved from the 1T-OTP memory or through on-going PMBus communication during normal operation. Powervation uses Sidense SLP OTP macros for its power management products. SLP macros are available in densities up to 256 Kbits per macro and feature very small macro footprints. These macros were designed for very low power applications and include several additional features that provide flexibility in customizing the memory operation to target specific applications. 5 1T-OTP VS. OTHER NVM The 1T-OTP has several advantages over other types of NVM. Since it does not require any additional masks or processing steps, it can be embedded on the power management chip without adding extra processing cost. This eliminates the need for separate-chip August 2013 Copyright 2013 Powervation Ltd. 4

5 NVM, such as flash or EEPROM, which add cost and size to the digital power management system while reducing system security and reliability. Since anti-fuse OTP does not depend on charge storage, it operates at high temperature with long bit-cell retention times, over ten years at 125 C and a 100% read duty cycle and more than 20 years at 125 C with a 50% read duty cycle. 1T-OTP uses a single transistor per bit cell, resulting in memory macros that are very small and minimize the OTP macro s impact on chip area and cost. As an example, Powervation s PV3012 dual phase digital control IC for computing and networking applications uses this memory structure. Even though the device uses 1T-OTP for storing firmware, DSP code, and the device configurations (with enough memory provided for multiple storage cycles of both the standard configuration and Powervation's Single Pin CONFIG feature), the area allocated to the 1T-OTP memory macros only accounts for approximately 3.5% of the total chip area. Anti-fuse-based 1T-OTP is much more secure than floating-gate MTP architectures, such as flash memory, and other types of OTP, such as ROM, efuse or EEPROM. Anti-fuse OTP has no stored charge and programming does not visually change a bit cell. This makes detecting anti-fuse OTP bit-cell states almost impossible using current/voltage scanning, reverse engineering or de-layering techniques. Sidense 1T-OTP memory macros also have additional features to enhance the security of stored information. 6 EMULATED MULTI-TIME PROGRAMMABLE OPERATION (EMTP) The 1T-OTP memory supports custom configuration of power-management products, storage for pre-loaded configuration tables, and storage for firmware code. While the memory is one-time programmable, Powervation SoC products use Sidense s 1T-OTP in an emtp mode to enable multiple writes to memory, such as adjusting values in a configuration table when using Powervation s singlepin configuration feature. emtp operation works by reserving additional, un-programmed 1T-OTP space for new content and allocating some additional storage for a tag to keep track of which memory segment is currently being used. Updatable code, configuration parameters and security codes can be implemented using 1T-OTP in an emtp mode, with bit programming done using an integrated charge pump operating at normal chip voltages. The integrated charge pump in the 1T-OTP enables in-field programming to meet design and customer requirements, both initially and later on if configuration requirements change. Figure 5: Emulated Multi-Time Programmable (emtp) Operation of 1T-OTP Memory is achieved by Writing New Content in Previously Un-Programmed Memory Space August 2013 Copyright 2013 Powervation Ltd. 5

6 7 USER BENEFITS Power control and management is becoming an increasing more critical concern in chip design as chip and system complexity, along with complexity of their power requirements, grows. Powervation s digital power IC technology using Sidense s 1T-OTP embedded memory technology gives users fully automatic adaptive control to DC/DC conversion in a reliable package that reduces design complexity and cost, increases power-supply performance and accelerates time to market. Dense, reliable, secure and low-cost Sidense 1T-OTP helps Powervation meet the rigorous requirements of their high-performance and user-configurable digital powermanagement products. 8 ABOUT THE AUTHORS Jim Lipman is Sidense's marketing director. His work experience includes positions at TechOnLine, VLSI Technology, Hewlett-Packard and Texas Instruments. Jim has a D.Eng from SMU and an MBA from Golden Gate University. He can be reached at jim@sidense.com. David New is Powervation s Director of Product Marketing. Prior to joining Powervation, David held various technical and business management positions at Power Integrations Inc., Maxim Integrated Products, and International Rectifier Corporation Inc. He earned his S.M.E.E. from the Massachusetts Institute of Technology, and B.S. Physics and B.S.E.E. from the University of Arkansas. He can be contacted at davidnew@powervation.com. August 2013 Copyright 2013 Powervation Ltd. 6