This Part-B course discusses design techniques that are used to reduce noise problems in large-scale integration (LSI) devices.
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1 Course Introduction Purpose This Part-B course discusses design techniques that are used to reduce noise problems in large-scale integration (LSI) devices. Objectives Learn approaches and design methods for minimizing electromagnetic interference emitted by LSI devices. Gain insight into how Renesas applies these techniques for handling noise problems in its microcomputer products. Content 26 pages Learning Time 30 minutes 1
2 Reducing EMI EMI reduction is a goal shared by the semiconductor experts who design LSI devices and by the system engineers who apply those devices. Process encompasses techniques for reducing the electromagnetic interference emitted by a specific system, circuit or device that causes other devices/circuits to operate incorrectly. 2
3 Explanation of Terms Core CPG Driver buffer EMC EMI EMS Harness OSC PLL POR/LVD Power supply SSCG WDT A microcontroller chip is composed of a core, ports, and power supply circuitry. The core consists of the CPU, ROM, RAM, and blocks implementing timers, communication, and analog functions. Clock Pulse Generator Output circuit transistors as well as output circuits for driving signals with large load capacitance and port output transistors. Clock/bus driver, signals between blocks, etc. Electromagnetic Compatibility Electromagnetic Interference Electromagnetic Susceptibility Cables (wires) connecting a board and power supply or connecting one unit in a system to another. Input/Output Port Oscillator Phase Locked Loop Power-On Reset/Low-Voltage Detect functions Two power supplies are applied to the LSI: Vcc and Vss. The core power supply internal to the LSI is VCL (internal step-down). The Vss-based power supply routed through the LSI is VSL. Spread-Spectrum Clock Generator Watchdog Timer 3
4 Oscillator Circuit Design For minimum EMI, oscillator s output should be a sine wave "H" Vcc Rf External components Vss Desired output waveform Excessive gain in the oscillator circuit s Vcc inverting amplifier can cause clipping. The EMI that results contaminates Vss power supply lines and other circuits Clipped waveform produces EMI 4
5 Adjusting Gain of Oscillator EMI can be reduced by adjusting the drive-capacity (gain) of the oscillator s amplifier circuit Manual adjustment is via an external resistor, RD Automatic or software-controlled capacity-switching uses logiccontrolled circuits to implement high and low drive Rf Xin VSS Xout RD Ø LSI device "H High gain L Low drive capacity High drive capacity Low gain 5
6 Phase-locked Loop Circuit PLL allows frequency of oscillator circuit to be lowered (decreased by a factor of 1/N), thereby reducing higher frequency harmonics and EMI Circuit can be built with jitter function to disperse high-frequency noise, thereby decreasing overall noise level PLL Circuit fs fo fo = N x fs 6
7 On-chip Oscillator Circuit OCO = Built-in alternative, high-performance oscillator circuit Provides backup for primary crystalcontrolled oscillator circuit Protects application against failure due to loss of system clock Allows system operation to continue or lets application shut down safely Pads Primary oscillator (+ PLL) Oscillation stop detect (OSD) feature provides automatic switching for fail-safe operation OCO CPG System clock Supplied to cores and functions On-chip oscillator circuit 7
8 Spread-spectrum Clock Generator SSCG is an ideal solution for high-speed products Is combined with the PLL circuit in LSI devices Produces modulated waveform with wider spectrum Reduces noise emissions Is a very useful noise reduction technique for devices that can withstand variations in clock frequency Example of SSCG modulation waveform Noise emissions data f -0.5% 33kHz f0 = 1.0GHz Gain (db) With SSCG -7 to -10 db Without SSCG Time -0.5% f0 Freq 8
9 Clock and Bus Driver Capacity Capacity should be matched to the operating frequency and signal load of the lines being driven Excess capacity wastes power and generates unnecessarily high levels of EMI System clock Inadequate capacity causes performance degradation Design challenge is to optimize clock and bus lines and their drive circuits Oscillator (+ PLL) CPG To cores and functions 9
10 Clock and Bus Signal Lines Signal lines with high frequencies and high drive levels should be kept as short as possible ROM RAM CPG CPU TIMERS COMMUNICATION Clock line Bus line 10
11 Transistors in Logic Circuits Transistors should be carefully selected so that size (current capacity) is as small as it can be, considering the design function, to minimize chip area, power, and EMI Can be selected from a large library of different sizes Typical On-chip Module Some transistors are drawn physically large here to indicate a large current capacity. In reality, this may not be the case 11
12 -port Transistors Transistors should match characteristic impedance of circuit-board wiring (~100 to 150Ω when parts are mounted) Mismatches cause ringing at port, producing EMI ~100Ω ~ to 150Ω Impedance Mismatch Vcc ~50Ω ~ Impedance Match Vcc ~100Ω ~ GND ~100Ω ~ GND ~100Ω ~ If required, an external series resistor, (R = 50Ω to 1kΩ) can be used to stabilize the output Vcc ~50Ω ~ R1 ~100Ω ~ 12 GND
13 -port Rush Current Reduction Rush current can be reduced in various ways 1. Staggering timing of port lines 2. Using slew-rate control to limit shoot-through current V P00 Delay ckt Delay ckt t V P01 Delay ckt t Delay ckt V V P07 Delay ckt V NMOS turns on after PMOS turns off Port triggered t Delay ckt t 13
14 -port Rush Current Reduction Rush current can be reduced in various ways 3. Connecting multiple transistors in parallel to terminal output buffers and turning them on in stages t1 t2 t3 4. Using feedback capacitors in the buffers to broaden the output waveform Vdd Vdd Feedback capacitors Vss Vss
15 Rush Current Reduction in Core Rush current in core can be reduced by using capacitors to store a signal s excess charge over a period of time Examples: Clock driver circuit, bus driver circuit Clock driver circuit Bus driver circuit Vdd Vdd Put capacitors near bus-driver transistors Pooled charge Vss C1 CLK Vss C2 Pooled charge BUS 15
16 Rush Current Reduction in Core Rush current can be decreased in core by implementing in the step-up circuit a circuit that limits the current that charges the large storage capacitor Example: Flash ROM Current-limit circuit Vpp Stepup circuit C Flash ROM memory array Vcc Vss 16
17 Rush Current Reduction in Core Another way to reduce rush current in the core is sequence the activation of the various power supplies that drive the core circuits 5V Step-down circuit C1 Vcl Peripheral modules CPU RAM Vcc Vss Vsl or Vss ROM A/D, D/A Vdd 17
18 Module-stop Function The Module-stop function disconnects the supply voltage to a module not being used This saves power and eliminates the noise the module produces CPU System controller CLOCK BUS ROM RAM TIMER-1 SCI TIMER-2 IIC Indicates module-stop signal TIMER-3 CAN 18
19 Clock-signal Control EMI is reduced when the clock distributed within the module is turned off when it isn t needed CPU ROM Module-stop signal CLOCK BUS RAM Clock signal inside module TIMER-1 SCI Clock to module TIMER-2 IIC TIMER-3 CAN Indicates main clock signal 19
20 φ-pin Output Control The φ clock is turned off in Single-chip mode and also when it isn t required for clock synchronization in Extended mode Can be implemented using a switch at the output driver Performs best when the φ clock control is configured at the source Oscillator circuit Clock line for φ CPG System clock line 20
21 Traditional Method The φ clock is turned off in Single-chip mode and also when it isn t required for clock synchronization in Extended mode Can be implemented using a switch at the output driver Performs best when the φ clock control is configured at the source Oscillator circuit Traditional design (not recommended) Clock line for φ remains active CPG System clock line 21
22 Innovative Method The φ clock is turned off in Single-chip mode and also when it isn t required for clock synchronization in Extended mode Can be implemented using a switch at the output driver Performs best when the φ clock control is configured at the source Oscillator circuit Clock line to φ driver is disconnected CPG Improved design System clock line 22
23 Independent High-speed Clock The built-in high-speed clock is generated by an on-chip oscillator and supplied only to peripherals that require it Can be used as a backup for the main system clock CPU ROM 20MHz Osc. ckt. Switch Divide by 2 SYSTEM CLOCK TIMER-1 TIMER-2 High-speed on-chip oscillator (40MHz) 40MHz BUS RAM SCI IIC CAN 20MHz 23 40MHz
24 Low-speed Clock Some Renesas LSI devices have a low-speed clock that is software switched and supplied to the peripheral modules that can operate at lower frequencies CPU ROM 20MHz Osc. Ckt. SYSTEM CLOCK TIMER-1 TIMER-2 PSC 10MHz BUS RAM SCI IIC TIMER-3 10MHz CAN 20MHz 24 10MHz
25 Estimating EMI Noise Levels Can be performed by making simplifying assumptions about the chip, then performing SPICE simulation Simulation circuit diagram (conceptualization) Internal stepdown circuit Internal capacitance of chip CPG Oscillator buffer Package equivalent circuit EMI noise evaluation circuit equivalent circuit Vcc Vss R+L 25
26 Course Summary Techniques for reducing EMI in oscillator circuits Ways to optimize the capacity of clock and bus drivers and clock and bus lines Methods for reducing rush current Ways to slow down a device s overall operating rate Technology for estimating noise levels For more information on specific devices and related support products and material, please visit our Web site: 26
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