Energy Efficient Computing Systems (EECS) Magnus Jahre Coordinator, EECS

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1 Energy Efficient Computing Systems (EECS) Magnus Jahre Coordinator, EECS

2 Who am I? Education Master of Technology, NTNU, 2007 PhD, NTNU, Title: «Managing Shared Resources in Chip Multiprocessor Memory Systems» Current Associate Professor in Computer Architecture (since 2012) Head of CARD research group Coordinator of the Energy Efficient Computing Systems «fyrtårn» Research Interests Memory systems for multi core architectures, heterogeneous computer systems, energy efficiency, computer architecture simulation, compilers and system software

3 Outline 1. Energy Efficient Computing Systems (EECS) 2. Computer Architecture Trends 3. Achieving Energy Efficient Computation 4. The SHMAC Research Project 5. Concluding Remarks

4 Outline 1. Energy Efficient Computing Systems (EECS) 2. Computer Architecture Trends 3. Achieving Energy Efficient Computation 4. The SHMAC Research Project 5. Concluding Remarks

5 Green ICT Improving computing technology Improving energy intensive processes Big potential impact Massive potential impact EECS focus

6 Environmental Motivation Global Energy Consumption Other Computing Systems Sources: International Energy Agency and SSB Research project goal: 10% reduction 80 TWh Global Consumer ICT (800 TWh) Use energy reduction to turn off coal power plants Norway Total Energy (220 TWh) Save 80 M metric tones CO 2 Norway annual CO 2 : 87M metric tones

7 Technical Motivation Energy efficiency is becoming the primary design goal across all market segments Extremely energy sensitive systems Lifetime of system is equal to battery life Lower energy consumption can open new markets Mobile systems Energy: Users want long battery life Limited size of cooling system results in strict power constraints Desktop computers Fixed power budget due to cooling challenges Cannot improve performance without improving energy efficiency Data centers and HPC Energy bill dominates operating cost Power consumption is a significant engineering challenge

8 EECS Structure Vertical approach Leverage strong groups working horizontally Application agnostic Matches focus of high volume international industry Choose demonstrator applications that clearly demonstrates proposed innovations People 6.2 affiliated permanent staff 10 affiliated PhD students 5 affiliated researchers/lecturers SHMAC

9 NTNU EECS Key Assets EECS at a Glance Expertise from nano scale electronics via computer architecture to system software and applications Excellent lab infrastructure for prototype development and significant high performance computing resources Industry partners including ARM and SiLabs The SHMAC Research Infrastructure Single ISA Heterogeneous MAny core Computer An infrastructure for rapid prototyping of heterogeneous computing systems Significant EU Proposal Support Scientific man year allocated to EU proposal processes Significant administrative support 21 researchers from 10 nations Contact: Assoc. Prof. Magnus Jahre (magnus.jahre@idi.ntnu.no), EECS Coordinator

10 Outline 1. Energy Efficient Computing Systems (EECS) 2. Computer Architecture Trends 3. Achieving Energy Efficient Computation 4. The SHMAC Research Project 5. Concluding Remarks

11 Historical Computer Performance Significant performance improvement for each generation The high performance processor industry economy relies on these trends Performance Relative to VAX 11/ Single core performance Year Aggregate performance Enabled by Transistor speed scaling Core microarchitecture techniques Cache memory architecture Performance Relative to VAX 11/ % 52% Year 22%

12 Traditional Transistor Speed Scaling Every generation: Transistor density doubles Performance increases by 40% Supply voltage is reduced by 30% which reduces dynamic energy by 65% Known as Dennard scaling Almost to good to be true Keeping these scaling properties is no longer possible Key question: How can we continue to deliver performance growth to end users?

13 Architectural Advances and Energy Efficiency

14 Pollack s Rule Microarchitectural techniques that exploit the growth in available transistors ( area) deliver a performance growth which is the square root of the number of transistors ( area) Example: Adding techniques that result in doubling the area occupied by the processor increases performance by a factor of 2 1.4

15 DRAM Density and Speed Good: Optimizing for DRAM density gives large memory capacity Bad: Optimizing for DRAM density creates the need to hide latency

16 Performance Observation: Two thirds of the 1000x improvement from the last 30 years is due to technology

17 Business as usual? Business as usual scenario: Add more cores and increase clock frequency Dark Silicon Practical server limit (about 100W) Practical desktop limit (about 65W) Market expects 30x performance improvement over the next decade

18 Outline 1. Energy Efficient Computing Systems (EECS) 2. Computer Architecture Trends 3. Achieving Energy Efficient Computation 4. The SHMAC Research Project 5. Concluding Remarks

19 ACHIEVING ENERGY EFFICIENT COMPUTATION Based on: Borkar et al., The Future of Microprocessors, CACM 2011

20 Challenge 1: Leakage PMOS NMOS A transistor is not a perfect switch Inverter Leakage: The small current that flows through a transistor when it is off Bad news: Leakage increases exponentially with reduction in threshold voltage The increased number of transistors on a chip increases the consequences of this We cannot reduce the threshold voltage further! Threshold voltage reduction is key to reducing energy consumption

21 Challenge 2: Energy limits number of logic transistors Power and energy constraints limit the number of cores and clock frequency of future processors Energy efficiency is the key metric Energy proportional computing will be the goal of both hardware and software Use each additional joule to deliver more value!

22 Challenge 3: Memory Hierarchies (1/2) AMD Barcelona 4 core Processor Which units do actual computation?

23 Challenge 3: Memory Hierarchies (2/2) Modern processors have large memory hierarchies aimed at hiding latency Memory orchestration costs energy Energy consumption of a transfer is proportional to the length of the wire Moving data at high frequency over long distances leaves little energy for computation

24 Challenge 4: Software 1 st major challenge: Parallel software is needed to exploit the performance gains from technology scaling 2 nd major challenge: The parallel software must be energy efficient Trade off: programmability vs. efficiency The programmer needs help to achieve these goals

25 New Thinking Needed Traditional 90/10 optimization Use maximum transistors for the 90% case to improve single thread performance Pollack: Return is square root of invested resources Not energy efficient! New strategy: 10/10 optimization Add accelerators for the 10% cases All accelerators are energy efficient but for different tasks Meet energy budget by carefully choosing which accelerators should be active at a given time Corollary: most accelerators are off most of the time

26 Solution 1: Energy Efficient Programming Trick: Exploit that the system is not fully loaded at all times Sleep modes (application) Turn off the parts of the system that you don t need Retain data vs. not retaining data Very useful in embedded systems Dynamic Voltage and Frequency Scaling (DVFS) (system software) Match the performance to the tasks at hand Very useful for desktops/servers

27 Sleep Modes in EFM 32

28 Solution 2: Multiple cores P P P P P P P P P P P P P P P P Small core Homogenous Large core Homogenous P P P P Asymmetric Multi core Processor P P P P P P P P P P P P P Area = 4 Power = 4 Performance = 2 Area = 1 Power = 1 Performance = 1

29 Example: A Parallel Application Idea: Exploit heterogeneity to by using the simple energy efficient cores in the parallel phase and the fast energy hungry core for the sequential phase

30 Solution 3: Customization Idea: Add specialized units that can execute certain operations in an energy efficient manner Potential: 50x to 500x improvement (application dependent) Possible accelerators: SIMD cores or GPUs Fixed function units (media encoders, crypto, etc.) FPGAs TI OMAP Smartphone SoC

31 Solution 4: Hybrid Networks Idea: increase the size of the local storage to keep data as close to the core as possible Effect: Bandwidth demand is reduced, enabling simpler networks

32 Solution 5: Voltage Scaling (1/2) Reducing supply voltage and frequency increases energy efficiency

33 Solution 5: Voltage Scaling (2/2) Reducing the supply voltage for a powerful core reduces single thread performance Small throughput oriented cores are less sensitive to single thread performance Increase in number of cores offsets performance reduction Challenge: voltage reduction exposes production variability Solution: allow different clock frequencies for different cores

34 Outline 1. Energy Efficient Computing Systems (EECS) 2. Computer Architecture Trends 3. Achieving Energy Efficient Computation 4. The SHMAC Research Project 5. Concluding Remarks

35 Dark Silicon Business as usual scenario: Add more cores and increase clock frequency Dark Silicon Practical server limit (about 100W) Practical desktop limit (about 65W) Dark silicon: The end of Dennard scaling combined with Moore s law creates the situation where only a subset of the transistors can be powered within the power budget

36 The SHMAC Project Dark silicon effect makes heterogeneous processors likely Software for heterogeneous processors is an open research problem Heterogeneity of off the shelf components is limited Simulators have unlimited heterogeneity but are slow Solution: SHMAC = Single ISA Heterogeneous MAny core Computer

37 SHMAC Architecture Tiled multi core design paradigm describing a class of processor architectures Common instruction set and architecture model gives software portability across SHMAC instances SHMAC instances can contain various tile types: Processors with different energy/performance characteristics Optimized processors (vector, OOO, etc.) Accelerators Fast Core Core w/ accelerator Core w/ accelerator Vector core

38 Design Goal: Software Portability All processor tiles are functionally equivalent Performance may be very different Different processor classes and accelerators 0xFFFF FFFF 0xFFFF xFFFE xF System Registers Tile Registers Scratchpad Tile Memory Scratchpad Tile 1 Scratchpad Tile 2... Scratchpad Tile k Uniform architecture Main Memory All processing tiles see the same memory map Tile registers are per tile, other memory locations are global 0x x Exception Table SHMAC Memory Map Research question: What are the costs associated with the Single ISA abstraction?

39 Leveraging Reconfigurability Generic components Benchmarks Operating Systems Runtime Systems In order core Core w/ accelerator Synthesis Vector core SHMAC instance running on an FPGA Scratchpad SHMAC Configuration Measure, evaluate, repeat

40 Project Example 1: Integrating Accelerators Tightly coupled accelerator Loosely coupled accelerator Accelerator research topics: Tightly vs. loosely coupled accelerators Which accelerators should be included? How can accelerators be leveraged by programmers? The most efficient solution will most likely require both software and hardware changes Key SHMAC Components: Accelerator support Processor tiles Memory tiles System Software Benchmarks

41 Project Example 2: Task Based Parallelism (TBP) for Heterogeneous Systems TBP: Program is organized as DAG of tasks (nodes) and dependencies (edges) Task scheduling for energy efficiency : How should tasks be scheduled in a heterogeneous environment? Which hardware feedback mechanisms are needed? SHMAC advantages: Efficient software development, large diversity in systems, possibility to add feedback components Key SHMAC Components: OS support Benchmarks Processor tiles Memory tiles

42 Project Example 3: Exploiting Near /Sub threshold technology Delay Power PDP EDP Reducing the supply voltage to near the threshold gives: Energy per switching is reduced by one order of magnitude Latency increases by 3 4 orders of magnitude How can this technology be leveraged at the microarchitecture level? Key SHMAC Components: Processor tiles System Software Benchmarks Tape out necessary to validate implementation

43 SHMAC Enables Collaboration SHMAC combines generic components and powerful abstractions Reimplement/extend the part(s) involved in your research project SHMAC best suited for cross disciplinary projects where hardware and software innovations are combined Different partners can focus on different parts of the system EECS is one of seven groups at NTNU that receives special support towards Horizon 2020

44 Future Directions Status: Minimal set of tiles to support software development Future hardware Efficient accelerator integration Vector core Out of order core Future software Benchmarks (micro, macro) Operating Systems (conventional, multikernel) Runtime systems Significant effort: 1 Post doc., 2 PhD students, 15 master students

45 How can I help save the world? Choose project/master thesis related to the SHMAC project!

46 Outline 1. Energy Efficient Computing Systems (EECS) 2. Computer Architecture Trends 3. Achieving Energy Efficient Computation 4. The SHMAC Research Project 5. Concluding Remarks

47 Concluding Remarks EECS Motivation Environment: Climate change and efficient use of energy Technology: Power/energy consumption limits performance growth across all computing segments Master and project topics Strong relations to international high volume industry SHMAC project covers the vertical depth of the strategic research area

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