MARKET PERSPECTIVE: SEMICONDUCTOR TREND OF 2.5D/3D IC WITH OPTICAL INTERFACES PHILIPPE ABSIL, IMEC

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1 MARKET PERSPECTIVE: SEMICONDUCTOR TREND OF 2.5D/3D IC WITH OPTICAL INTERFACES PHILIPPE ABSIL, IMEC

2 OUTLINE Market Trends & Technology Needs Silicon Photonics Technology Remaining Key Challenges Conclusion

3 OPTICAL VS. COPPER INTERCONNECTS 1 Pbps 1 Tbps 1 Gbps 1 Mbps 1cm Package/Chip Logic Core-Core, Logic-DRAM [1mm-5cm] Source: Intel COPPER INTERCONNECT Copper I/O Density 100Tbps/mm 10Tbps/mm 1Tbps/mm 100Gbps/mm 10Gbps/mm Board Logic Package-to-Package Logic-DRAM array [5cm-0.5m]? 100G 50G 25G 10G... Nx50/100G 2.5G 1.25G Backplane Board-to-board [0.5m-3m] Source: LightCounting Intra-Datacenter Rack-to-Rack [5m-500m+] T 800G 400G 200G 100G 40G 10G Telecom [10km+] T 800G 400G 200G 100G Optical Source: LightCounting TRANSITION ROADMAP IT System Scaling requires Scalable Optical Interconnects Datacenter [5m-10km+] 100G-400G-1T+ Backplane [0.5-3m] (N x) 50G-100G+ Board [5-50cm] 200Gbps+/mm Package or Chip [1mm-5cm] 10Tbps+/mm 3D Technologies enables local interconnect scaling Link distance 3

4 3D TECHNOLOGIES ENABLES ON-BOARD INTERCONNECT SCALING 3D Application Interposer stacking ( 2.5D ) Example Industry Implementation Xilinx: 3D FPGA Virtex T AMD: Graphics Radeon R9 FURY X Xilinx: Heterogeneous 3D FPGAVirtex-7 H580T Memory stacking Advanced DRAM Micron: Hybrid Memory Cube SK Hynix: High Bandwidth Module Samsung: 128GB 3D DDR4 RDIMM SystemPlus TechInsites

5 OPTICAL VS. COPPER INTERCONNECTS 1 Pbps 1 Tbps 1 Gbps 1 Mbps 1cm Package/Chip Logic Core-Core, Logic-DRAM [1mm-5cm] Source: Intel COPPER INTERCONNECT Copper I/O Density 100Tbps/mm 10Tbps/mm 1Tbps/mm 100Gbps/mm 10Gbps/mm Board Logic Package-to-Package Logic-DRAM array [5cm-0.5m]? 100G 50G 25G 10G... Nx50/100G 2.5G 1.25G Backplane Board-to-board [0.5m-3m] Source: LightCounting Intra-Datacenter Rack-to-Rack [5m-500m+] T 800G 400G 200G 100G 40G 10G Telecom [10km+] T 800G 400G 200G 100G Optical Source: LightCounting TRANSITION ROADMAP IT System Scaling requires Scalable Optical Interconnects Datacenter [5m-10km+] 100G-400G-1T+ Backplane [0.5-3m] (N x) 50G-100G+ Board [5-50cm] 200Gbps+/mm Package or Chip [1mm-5cm] 10Tbps+/mm Link distance Photonic Integration Is Key To Enable Global Interconnect Scaling, from withinrack to across-datacenters 5

6 CLOUD DATA CENTER NETWORK Building-wide Fiber Network Building-wide rack-to-rack connectivity Redundancy 100,000s fiber optic links Up to 500m reach Fiber cost is substantial CAPEX Re-use fiber plant, upgrade optical ports Data center network topology (Facebook) TODAY 40G EMERGING (2016) 100G NEAR FUTURE (2019E) 400G FUTURE (2022E) 1T+

7 WHERE IS THE PHOTONIC? Switch QSFP Transceiver Transceiver Needs Scaling up the bandwidth Scaling down the form factor Scaling down the power consumption

8 PHOTONICS: FROM THE PANEL INTO THE PACKAGE (1) Si Photonics Module on the Board SMF array connector SMF to network (1) Si Photonics Module on the Board SMF PCB to network Current Solution: Stand-alone transceiver on frontpanel PCB Scaling Step 1: On-Board Transceiver (2) Si Photonics Module in the Package Logic die SiPh module SMF to network Scaling Step 2: In-package Optical I/O PCB

9 PHOTONIC INTEGRATION ENABLES BEYOND THE BOARD INTERCONNECT SCALING INTEGRATION OF DIVERSE OPTICAL FUNCTIONS Source: Infinera Source: Jeppix InP Photonic Integration = Complete toolbox of active and passive optical functionality High performance optical devices and circuits 9

10 SILICON PHOTONIC INTEGRATION BENEFITS AND DRAWBACKS Silicon PICs Fabrication in CMOS fabs [200mm/300mm] Large Si/SiO 2 refractive index contrast of ~2 [scalable PIC density] Advanced Si patterning capability [193(i), nanometer scale accuracy] (Si)Ge epitaxy [photodetectors/modulators] Low resistance contacts to Si [high-speed optical devices] Volume scalability [>1M units/year] & Efficiencies of scale [cost] Wafer-scale 3-D packaging and assembly [TSVs, micro-bumps,...] No monolithic integrated optical gain/lasing [need for hybrid solution] Silicon Photonics = Leverage existing CMOS infrastructure for Photonic Integration 10

11 DATA CENTER TRAFFIC GROWTH Zettabyte Data Volumes Cisco Global Cloud Index ( ) Zettabyte/year since 2013 Average CAGR = 32%, some reporting 50% CAGR >75% of this data traffic stays inside the datacenter

12 MARKET FORECAST Evolution of market size for discrete and integrated Photonics transceivers Reference: LightCounting OFC2016 Dinner Seminar Ethernet represents dominant market share, largely driven by Cloud Mega Datacenters Integrated photonics grows faster than discrete photonics, cross-over expected by 2018 Steady growth for Si Photonics, however market share remains relatively modest (~$1B by 2021) Optical Technology that combines performance of InP (single-mode) and cost of GaAs (multimode) with manufacturability and scalability of Si Photonics has tremendous market potential!

13 WHO IS DOING WHAT IN SILICON PHOTONICS? Press Announcement GlobalFoundries presentation at Semicon West 2016, San Francisco Integration of Silicon Photonics Into DRAM Samsung technical paper at OFC 2013, Anaheim Process Press Announcement

14 OUTLINE Market Trends & Technology Needs Silicon Photonics Technology Remaining Key Challenges Conclusion

15 OPTICAL TRANSCEIVER SCALING Faster Channels MULTIPLE AXES PAM-16 (LightWire/Luxtera) 4-bit 2-bit 1-bit 1core More Bits per Symbol Amplitude: PAM-X Phase and Amplitude: DP-QPSK, QAM-X, G 50G 25G 10G 1l 4l 8l 16l 8core 16core Focus for very-short reach interconnects: Faster and More Channels J. Sakaguchi, et al, "19-core fiber transmission of 19x100x172-Gb/s SDM-WDM-PDM-QPSK signals at 305Tb/s," OFC2012, PDP5C.1. More Channels Parallel (Single-Mode) Fiber [PSM] Multi-Core Fiber, Spatial Division Multiplexing [SDM] Wavelength Division Multiplexing [WDM] 15

16 ARCHITECTURE DIVERSITY DRIVES PLATFORM AGILITY CWDM PSM DWDM SDM Edge + Surface Couplers Mach-Zehnder, MicroRing, GeSi Electro-Absorption Modulators Ge (Avalanche) Photo-Detectors WDM Filters

17 KEY TECHNOLOGY FEATURES OF SILICON PHOTONICS Leveraging CMOS Technology Starting substrate: Silicon-On-Insulator (typ. 220nm Si / 2000nm BOX) Multi-level Si patterning with 193nm (immersion) lithography Silicon doping & Ge doping Ge-on-Si RPCVD Epitaxy Metal interconnects + Al bondpad Deep-Si etch for edge coupling III-V on silicon (bonding, epitaxy) for gain material

18 IMEC S SILICON PHOTONICS PLATFORM Fully Integrated 8x50G DWDM Si Photonics Technology 56G Silicon Ring Modulator 8+1-channel DWDM (De-)Multiplexing Filter In-Plane Coupler 56Gb/s eye diagram 56G Ge Electro-Absorption Modulator Surface-Normal Coupler 56Gb/s eye diagram 50G Ge Photodetector 50Gb/s eye diagram 56G Silicon Mach-Zehnder Modulator Co-integration of the various building blocks in a single platform Today available on 200mm wafer size, coming soon on 300mm 95% compatible with CMOS130 in commercial foundries

19 HYBRID CMOS SI-PHOTONICS TRANSCEIVER DEMO Putting it all together 40nm CMOS 4x20Gb/s Transceiver 28nm CMOS 50Gb/s Transmitter

20 WIREBOND CMOS SI-PHOTONICS RING TRANSMITTER DEMO MEASUREMENT SETUP SiPh die with ring modulator array Polarization controller Fiber in Wirebond Wirebond Fiber out EDFA (6dB) Tunable Laser (12dBm) Optical Filter PPG + MUX 56 Gb/s Sampling Oscilloscope 40GHz BW - 67GHz - 50Ω GSG probe 20

21 WIREBOND CMOS SI-PHOTONICS RING TRANSMITTER DEMO EYE DIAGRAMS VS. POWER SUPPLY VDD 36Gb/s NRZ, PRBS07 40Gb/s NRZ, PRBS07 50Gb/s NRZ, PRBS07 Driver supply: VDD=0.9V E bit = 420 fj/bit 36Gb/s NRZ Driver supply: VDD=1.0V E bit = 510 fj/bit 46Gb/s NRZ Driver supply: VDD=1.1V E bit = 610 fj/bit 50Gb/s NRZ 21

22 IMEC S SILICON PHOTONICS OFFERING Build your own Prototype in imec s open platform technology! Accessing imec s 200mm Si Photonics Platform (isipp200) Both MPW and Fully Dedicated Runs Silicon Validated PDK v1.3 is available Supported by various EDA tools >8 Customer tape-outs since 2014, >10 planned in 2016 Interested? Get in touch! MPW Dedicated: Kenneth.Francken@imec.be

23 OUTLINE Market Trends & Technology Needs Silicon Photonics Technology Remaining Key Challenges Conclusion

24 THE MISSING PIECE: THE LASER Option 1: Hybrid Bonding Manufacturability Reliability Option 2: Epitaxy Efficiency not proven Reliability Option 3: Assembly Insertion loss Scalability & Cost

25 MONOLITHIC LASERS ON SILICON Addressing extreme cost and performance targets Epitaxial growth of III-V Lasers on Silicon Array of 10 InP lasers under optical pumping InP Silicon Wang, Nature Photonics, October 2015

26 LOW-COST PACKAGING Challenge 1: Fiber Assembly (sub-) micron alignment Fiber through package Challenge 2: Laser Assembly (sub-) micron alignment Metal pads Emerging custom solutions but still far from standard OSAT operations SAMTEC FireFly solution

27 OUTLINE Market Trends & Technology Needs Silicon Photonics Technology Remaining Key Challenges Conclusion

28 3D & Silicon Photonics Enable Future In-Package Optical I/O s Silicon Photonics Ready For Low Voltage Operation at 50Gb/s and beyond Light Sources & Packaging Remain Challenging Investment Required!

29 THANK YOU!