Verification Futures The next three years. February 2015 Nick Heaton, Distinguished Engineer

Transcription

1 Verification Futures The next three years February 2015 Nick Heaton, Distinguished Engineer

2 Let s rewind to November Cadence Design Systems, Inc. All rights reserved.

3 November 2011 SoC Integration Challenges are the next frontier Cadence Design Systems, Inc. All rights reserved.

4 November 2011 SoC Integration Challenges are the next frontier Ensuring new design IP correct by construction Cadence Design Systems, Inc. All rights reserved.

5 November 2011 SoC Integration Challenges are the next frontier Ensuring new design IP correct by construction Need for automation for common SoC components like Interconnect infrastructure Cadence Design Systems, Inc. All rights reserved.

6 November 2011 SoC Integration Challenges are the next frontier Ensuring new design IP correct by construction Automation for common SoC components like Interconnect infrastructure Reducing barriers to migration across simulation engines Cadence Design Systems, Inc. All rights reserved.

7 November 2011 SoC Integration Challenges are the next frontier Ensuring new design IP correct by construction Automation for common SoC components like Interconnect infrastructure Reducing barriers to migration across simulation engines HW/SW Challenges Simulation performance Debug Cadence Design Systems, Inc. All rights reserved.

8 How have things moved on? Cadence Design Systems, Inc. All rights reserved.

9 Evolution of integrated end-to-end platforms Enabling verification reuse and portability Perspec System Verifier vmanager Incisive Debug Analyzer, SimVision Verification IP System-level Use-Case Verification Plan & Management Debug Analysis Verification IP + Forte & Jasper M&As VSP Incisive Virtual Prototyping Palladium Hybrid CtoS Cynthesizer High-level Synthesis JasperGold + IFV/IEV Formal Verification TLM Design & Verification Metric Driven Verification Incisive Simulation Palladium Emulation & Accelerattion Stratus, Incisive, UVM-ML Protium FPGA Based Prototyping vmanager, Incisive, Palladium, VIP, JasperGold ARM-based SoC Development Palladium Hybrid, AMBA VIP/IPK, IWB, Perspec Low Low Power Power & Mixed Mixed Signal Signal Functional Safety CPF & IEEE1801, Palladium DPA, JasperGold LP Incisive DMS, AMS Designer, Spectre Incisive Fault Simulator (JasperGold, Palladium) + Incisive & VIP leadership + Hybrid & Perspec for software driven verification technology + ARM, MDV, FuSa, MS, LP solutions Sim VIP Catalog VIP for Palladium In-Circuit Acceleration Debug Analyzer Cadence System Development Suite IEEE1801 Palladium XP II, Hybrid Interconnect Validation Forte Jasper Safety ARM Solution Protium Cadence Design Systems, Inc. All rights reserved

10 A New Era in Verification Management Verification Engines User Interface Client #n User Interface Client #1 Incisive vmanager Application Coverage Results Plans LAN User Interface Client #2 Incisive vmanager Verification Database Verification is a team activity Multi-user / multi-project environment Database-driven for massive scaling Instant access to real-time reports Continuous operating modes Automatic data management Synchronous information Cadence Design Systems, Inc. All rights reserved.

11 Formal-assisted design methodology Formal pioneers consider it critical for RTL Designers to be active in verification effort Design and verification knowledge to be shared and maintained cross teams and cross projects Impact Reduce costly and long design loops by enabling backend work flows to work on higher quality RTL design Design intent and validation collateral maintained across design projects Boost the overall TTM and quality of products Cadence Design Systems, Inc. All rights reserved. FMCAD 2012

12 Spectrum of Formal Verification Solutions ROI Quality Cost Risk Schedule Arch Arch Design Design Verify Verify Integrate Post-Si Integrate Post-Si $$ Saving Formal Verification in the Mainstream! 90 s 00 s 10 s 20 s Cadence Design Systems, Inc. All rights reserved.

13 Palladium Hybrid Early SW & System Validation Fast Processor Model TLM2 A15 x 4 A7 x 2 Coherent Fabric SW Integrator Solution Timers UARTs emmc Execute SW at 100MHz With standard or custom processor models Plug and Play Integration with RTL SoC-specific transactors and RTL I/F Reconfigurable Interconnect TLM Memory Smart DDR TLM/RTL Bridge Interrupt Manager Reset Manager CPU Sub-system RTL I/F Validate SoC + OS at 5-10 MHz on PXP High-performance memory coherency Shorten SoC Debug System Messages HW / SW Debuggers AXI4 or ACE-Lite Compute Subsystem A15 x 4 A7 x 2 Coherent Fabric SoC Interconnect Fabric Interrupts UART INTC Timer System Boot Resets Peripheral Fabric Color Key: Customer RTL SW Integrator RTL TLM Back-Door I/F Memory Controller DDR3 Smart DDR MM GPU Customer Design (no RTL changes) CSI DSI Ethernet Display USB2 USB3 SATA Cadence Design Systems, Inc. All rights reserved.

14 Perspec System Verifier Solution 10x productivity for SoC complex test creation Abstraction: UML style use-case diagrams Automation: system use-case test generation Portability: reuse across all execution platforms Measurement: SoC-level HW/SW coverage metrics Cadence Design Systems, Inc. All rights reserved.

15 What will drive verification in the next 3 years? Cadence Design Systems, Inc. All rights reserved.

16 Verification is changing Power, Performance and Thermal Considerations Analysis traffic Verification Power Analysis Implementation Key traffic data generated by verification Use-case and SW-driven TB increase value for analyses Performance Analysis Thermal Analysis Requires physical for accuracy Packaging/ambient modeling Architecture System Performance goals/metrics Modeling/abstraction Package Board Cadence Design Systems, Inc. All rights reserved.

17 Automotive Challenges Mixed-Signal and Safety concerns Advanced Driver Assist Systems Image video processing Sensor fusion Functional safety Infotainment systems HiFi audio processing Voice triggering Active noise cancellation Lidar/Radar Sensors Ethernet Camera V2X In-vehicle Networking ADAS, infotainment, gateways, cameras, etc. will all use Ethernet Key Cadence IP to build and verify Ethernet networks ADAS ECU Infotainment Head Unit Automotive Ethernet ECU Cadence Design Systems, Inc. All rights reserved.

18 Where are we going? Cadence Design Systems, Inc. All rights reserved.

19 SoC Power-Performance-Thermal System Development Suite Engines Palladium Incisive Analysis traffic VCD, SAIF Power Analysis Voltus Verification Power profile Power map Stratus Encounter SoC sim configuration Floorplan Layout Implementation IWB VMgr Performance Analysis Thermal map Sigrity Power DC Thermal Analysis Perspec SVR Architecture System Analysis scoreboard Floorplan Layout Allegro Package Board Cadence Design Systems, Inc. All rights reserved.

20 Requirements TCL Cadence Functional Safety Solution High initial quality 10+ year reliability Predictable failure recovery or fail safe mode Proven technology in connected flow Traceable requirements throughout Integrated safety verification NEW! IP Design & Implementation Signoff & Validation Functional Verification Safety Verification Safety Manual Safety Testing (ASIL) ISO Cadence Design Systems, Inc. All rights reserved.

21 The Eras of Verification Looking at the past and into the future Metric Driven (HW Coverage, SW Coverage, Use-Cases, Mixed-Signal, Functional Safety, Performance, Power, Bug Count, Code Churn etc etc) HVL Driven Verification Era SW-Driven Verification Era 1980 Directed Testing Era (aka Stone Age) Cadence Design Systems, Inc. All rights reserved.

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