EE251: Thursday November 15

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1 EE251: Thursday November 15 Major new topic: MEMORY A KEY topic HW #7 due today; HW #8 due Thursday, Nov. 29 Lab #8 finishes this week; due week of Nov. 26 All labs MUST be completed/handed-in by Dec. 7 Guest Lecture on Nov. 27. Attendance will be taken. Practical #2 is week of Dec. 3 Final Exam on Monday, Dec 10, 2:00 p.m. Lecture #26 1

2 Memory NOT Covered in Text NOT covered in TM4C Data Sheet NOT part of any lab IS covered in three Lecture Notes IS the topic of final Homework IS candidate for Final Exam Lecture #26 2

3 Memory Map A diagram which shows which blocks of memory address space are used Type of memory (RAM, ROM, registers, etc.) For what purpose, if special purpose E.g. Interrupt Vectors, I/O registers Useful for system designer and programmer to track usage of memory in a microprocessor system See example, next page Lecture #26 3

4 TM4C Memory Map 256k Flash ROM 32k RAM I/O ports Internal I/O PPB 0x x0003.FFFF 0x x2000.7FFF 0x x400F.FFFF 0xE xE004.1FFF Lecture #26 4

5 TM4C Memory Address Use Note ability to add external RAM to our processor The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M4F has separate buses that can perform instruction fetches and data accesses simultaneously. Lecture #26 5

6 Types of memory: RAM Dynamic RAM (DRAM)--must be refreshed frequently or it loses its memory Memory element is usually a capacitor Very small RAM cell Very large memory capacity, inexpensive Complex refresh circuitry required Refresh time typically in milliseconds Static RAM (SRAM)--maintains data as long as power is applied. Memory element is a latch (multi-transistor) Much larger RAM cell Physically larger; smaller memory capacity More costly per bit Faster No complex refresh circuitry required Lecture #26 6

7 Types of Memory: ROMs ROM: Read Only Memory Nonvolatile, Read Only in normal use Stores instructions, addresses, and constant values Program storage for final code version Mask Programmed ROMs Permanent. New programs mean new ROM chips Programmable ROMs Burn bits, much like a writable CD write once Erasable: EPROM May be erased when exposed to UV light, through a glass window in the package Byte-erasable EEPROMs Flash EEPROMs--requires rewrite of large blocks of ROM at one time (ours is 2K x 8). NAND Gate technology with floating gates. Lecture #26 7

8 Memory Bus Diagram m Address Bus Processor Memory Control Bus N Data Bus Lecture #26 8

9 Description of Memory Buses A microprocessor system uses address, data and control buses to communicate with external memory and memory-mapped peripherals The address bus determines which memory location to read or write The data bus contains the data being transferred during the memory cycle The control bus specifies whether the memory cycle is a read (into microprocessor) or a write (into memory) cycle, and specifies timing information for the cycle Lecture #26 9

10 32-bit address bus Addressing Memory: ARM Cortex-M4 Memory System Size first address: 2_ = 0x last address: 2_ = 0xFFFFFFFF 2 32 = = 4 1K 1K 1K = 4G addresses where 1K = 2 10 = 1024 (and 1G = = 1,073,741,824) Each address contains one byte of data Total memory addressable: 4G bytes = 4 Gbytes = 32 Gbits BUT suppose a physical memory subsystem to be added has/needs/uses only 12 address lines and 8 data lines This is 2 addresses or addresses Or K addresses or Kbytes This is bits of addressable memory We will discuss how to design this kind of subsystem. Lecture #26 10

11 More on Memory Addressing What if a memory system had 22 address lines? 2 22 = = addresses (Remember 1M=1K 1K=1,048,576) And what if it had 32 data lines? Bytes wide Therefore bytes of addressable memory in this system. Lecture #26 12

12 Memory Subsystem Diagram m Address lines (2 m = M)... A m-1... Memory Subsystem Memory Capacity: 2 m N bits or 2 m N/8 bytes A 0 Contol Signals Read/Write line Chip select line WE* CS* Output enable line OE* D N-1... D 0... N Data lines Lecture #26 13

13 Expanding Memory Off-Chip Can expand physical memory beyond what s included on chip, within processor s 4Gbyte address space. Key Design Requirements for adding memory: Maintain unique addresses for each memory location (data stored only once). The data bus is properly connected to all memory chips. Control lines are routed to appropriate pins on each memory chip. External memory chips are electrically compatible with our processor. We will discuss each of these four areas of requirements, starting with the next slide Lecture #26 14

14 Expanding Memory Off-Chip Can expand physical memory beyond what s included on chip, within processor s 4Gbyte address space. Key Design Requirements for adding memory: Maintain unique addresses for each memory location (data stored only once). The data bus is properly connected to all memory chips. Control lines are routed to appropriate pins on each memory chip. External memory chips are electrically compatible with our processor. Lecture #26 15

15 Expanding Memory: A Small Example Goal: Expand RAM memory by 8 Kbytes at address 0x , using 1K x 8-bit RAM chips equipped with tri-state outputs. Use chips, each addressed at a different K address block Tri-state logic allows only one RAM chip to drive the bus at a time even though several attach to bus. 8K memory requires address lines (2 + = 8K) which can change values. Each 1K chip has 10 address lines (2 10 = 1K). Modern RAM chips include 1G x 8-bit configurations. How many address lines for this chip? Lecture #26 16

16 Tutorial: K vs. Hex Notation K (base 10) 256=¼K 512=½K 1K 2K 4K 8K 16K 32K Hex 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000 Lecture #26 17

17 Addresses of 1K RAM chips in example: Assume ALL addresses below are prefixed by 0x6000 so numbers will fit on slide Chip # Starting Address Ending Address Starting Address Ending Address Address Range Use X for bits that change in this range 0 0x0000 0x % 0x 0x 1 0x 0x 2 0x 0x 3 0x 0x 4 0x 0x 5 0x 0x 6 0x 0x 7 0x 0x Lecture #26 18

18 Addresses of 1K RAM chips in example: Again assume ALL addresses below are prefixed by 0x6000 Chip # Starting Address Ending Address Starting Address Ending Address Address Range Use X for bits that change in this range 0 0x0000 0x03FF XX XXXX XXXX 1 0x0400 0x07FF XX XXXX XXXX 2 0x0800 0x0BFF XX XXXX XXXX 3 0x0C00 0x0FFF XX XXXX XXXX 4 0x1000 0x13FF XX XXXX XXXX 5 0x1400 0x17FF XX XXXX XXXX 6 0x1800 0x1BFF XX XXXX XXXX 7 0x1C00 0x1FFF XX XXXX XXXX Lecture #26 19

19 Another View of Address Ranges Chip # Address Range Another view of Address Range XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX XX XXXX XXXX Constant for this memory subsystem Different for each RAM chip Varying bits address bits to RAM chips But this needs to be prefixed by 0x6000 = Lecture #26 22

20 How do we associate RAM chips with these address ranges? A DECODER with enable inputs is the perfect logic device! (C.f. ECE102 Decoder topic), (See next slide) Since there are 8 chips, a 3:8 decoder works best. The decoder will choose (enable, address) exactly ONE of the 8 chips IF the address is in-range for this block of memory. Lowest (least significant) bits of address go directly to RAM chips Next lowest bits of address are decoded in decoder Remaining + = bits are used to determine if address is in-range for this block of memory TOTAL = bits Is this a coincidence? NO! Lecture #26 23

21 3-to-8 Decoder (e.g. 74HC238 ) Addr[2:0] 3 Select Inputs 3 Enable Inputs Enable G1 G2A* G2B* 3-to-8 Decoder Y 0 *... Y 7 * 8 Outputs Enable inputs Select inputs Outputs G 1 G 2 A* G 2 B* S 2 S 1 S 0 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L Lecture #26 24

22 Next Content Lecture Details of a physical Memory System. More on Adding Memory to the system Expanding the address space even beyond 4 Gbytes! Wait! There are only 32 address bits. Can t get past 4 GB, can you? Yes, you can! Come see how it s done! Memory Behavior and Adding Memory are possible topics on the final exam! BUT Special Lecture on Nov. 27 Susan Benzel, retired as HPE Program Manager Understands Future of Computing Well Also Understands a Variety of Engineering Positions Attendance WILL Be Taken (a Quiz Grade) Lecture #26 25

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