An Area-Efficient BIRA With 1-D Spare Segments

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1 206 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 1, JANUARY 2018 An Area-Efficient BIRA With 1-D Spare Segments Donghyun Kim, Hayoung Lee, and Sungho Kang Abstract The growing capacity and density of embedded memories increases the probability of defects and affects the yield. To improve the yield, built-in redundancy analysis (BIRA) has been developed to replace faulty cells with healthy redundant cells. BIRA requires a high repair rate and a feasible hardware size for implementation. Although many BIRAs have been proposed, most of them still demonstrate a low repair rate or a large required hardware size. The proposed BIRA employs an intuitive algorithm with a small-area analyzer that uses 1-D spare segments in the 2-D spare structure. Because most faults in the memory are single faults, spare segments can be used to efficiently allocate redundancies. In terms of the yield, 1-D spare segments are effective when used with an intuitive algorithm that can be implemented with a small hardware overhead. Experimental results show that the proposed BIRA has a higher repair rate and relatively low hardware overhead than state-of-the-art BIRAs and has the advantages of 1-D spare segments. Index Terms 1-D spare segments, 2-D spare structure, built-in redundancy analysis (BIRA), built-in self-repair (BISR), hardware overhead, normalized repair rate, repair rate. I. INTRODUCTION With advances in technology and device requirements, memory capacity and memory density are growing rapidly, which is increasing the probability of occurrence of memory faults. The yield drops and the quality, such as performance and reliability, deteriorates owing to an increased number of memory faults. A system-onchip (SoC) contains embedded memories; therefore, the yield of the embedded memories influences the yield of the SoC. To improve the yield and quality of embedded memories, built-in self-repair (BISR) has been developed [1]. The built-in redundancy analysis (BIRA) is a module of BISR that is used to analyze the fault address and to generate a solution of redundancy allocation. The three key features, hardware overhead, repair rate, and analysis speed, should be considered when implementing a competitive BIRA. Recently, most of the memories use 2-D spare structure consisting of row and column redundancies [3] [9]. The spare allocation in a 2-D spare structure is complicated by the choice of whether to use row spares or column spares. The problem of how to allocate redundancy is known as an NP-complete problem [2]. Therefore, many BIRA architectures have been proposed to obtain the optimal solution for yield improvement. CRESTA [4] provides an optimal repair rate solution which means achieving a 100% repair rate for memory that can be repaired using several subanalyzers. In other words, it focuses on repair rate; however, the required hardware size is large. The number of subanalyzers and hardware overhead increase drastically as the number of spares increases. LRM and ESP [5] are effective in reducing hardware overhead and provide a repair rate close to an optimal repair rate, but not an optimal Manuscript received May 10, 2017; revised July 26, 2017; accepted September 4, Date of publication September 26, 2017; date of current version December 27, This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MEST) under Grant 2015R1A2A1A (Corresponding author: Sungho Kang.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea ( Color versions of one or more of the figures in this brief are available online at Digital Object Identifier /TVLSI Fig. 1. Example of a memory using 1-D spare segments. repair rate. SFCC [7] and Branch [8] have been proposed to achieve low hardware overhead and an optimal repair rate. Both SFCC and Branch reduce the content-addressable memories (CAM) size by storing the pivot addresses. In the case of SFCC, the size of the analyzer is reduced by using a line-based search tree, whereas in the case of Branch, all nodes of a branch are analyzed to obtain a solution to the spare allocation. In particular, Branch is a state-of-theart BIRA with the lowest hardware overhead among existing BIRAs and an optimal repair rate. Therefore, the competitiveness of BIRA must be compared with Branch. The lower the hardware overhead, the more competitive the chip size. However, if the repair rate is low, it cannot be used because the yield and competitiveness worsen. In other words, hardware overhead and repair rate are a tradeoff, so a new algorithm or structure is required. In this brief, a BIRA with a smaller hardware overhead than other existing BIRAs with an optimal repair rate is proposed. The hardware overhead is reduced by using an intuitive algorithm and a high repair rate is achieved through the advantages of 1-D spare segments. II. RELATED WORKS AND MOTIVATION The following two sections describe the types of faults and repair rate to provide an understanding of repair analysis. Further, the spare structure used in the proposed BIRA is described. A. Classification of Faults Classification of faults is necessary for efficient spare allocation. In terms of the spare allocation, faults can be divided into single faults and sparse line faults by the faulty cell address. A single fault is a fault whose row and column addresses are not equal to those of the other faults. A sparse line fault comprises two or more faults and has the same row or column address. A must-repair line fault is one of the sparse line faults which can only be repaired in one direction, as shown in Fig. 1. For example, a fault with row address 3 and column address 0 is a single fault, whereas two faults with column address 2 are sparse line faults, and three faults with row address 1 are must-repair line faults. B. Repair Rate Repair rate is an important indicator of the performance of the BIRA [5], [7], [8]. The definition of repair rate is as follows: Repair rate = No. of repaired chips No. of total tested chips IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 1, JANUARY Fig. 3. CAM structure for the fault-collection process of the proposed BIRA. only physically located row lines can be repaired. If the repairable area is not limited, then the number of multiplexers for address reconstruction increases by the number of 1-D spare segments. Fig. 2. Example of memories with various spare structures. (a) 2-D spare structure. (b) 2-D spare structure with 1-D spare segments. (c) 1-D column spare structure. (d) 1-D row spare segment structure. The normalized repair rate is defined as the ratio of the number of repaired chips to the number of repairable chips No. of repaired chips Normalized repair rate = No. of repairable chips. The fact that the BIRA algorithm has an optimal repair rate, or a 100% normalized repair rate, indicates that all repairable chips can be repaired using spare cells. CRESTA, ISF, SFCC, and Branch are the representative BIRA algorithms with optimal repair rates. C. Motivation As mentioned, the conventional structure shown in Fig. 2(a) has an NP-complete problem, so the fault-analysis process is complicated and has a high hardware overhead. However, when the spare structure is 1-D, as shown in Fig. 2(c) and (d), then a complicated fault-analysis process is not required but has a lower repair rate than the 2-D spare structure. This is because, in the 1-D spare structure, it is not possible to repair faults that must be repaired to the other direction spare cells. Therefore, in the 2-D spare structure, if the fault-analysis process can be done intuitively, as with a 1-D spare structure, then the required hardware size will be small. In this brief, the fault-analysis process is intuitively performed as a 1-D spare structure using spare segments [10] in the 2-D spare structure. 1-D spare segments are defined as spares that can be individually repaired by dividing one spare into specific units, as shown in Figs. 1 and 2(b). Various spares have been proposed [11], [12], but there is a lot of additional hardware. On the other hand, the spare structure in Fig. 2(b) can be easily changed because it only divides into segments in the conventional 2-D spare structure. Two conditions are used to efficiently apply the 1-D spare segments structure. First, the 1-D spare segments structure is applied along either the row or column direction to simplify the algorithm. The direction of the 1-D spare segments can be selected as the row direction or the column direction, depending on the feature of the memory or the tendency of faulty cells. Second, the repairable area is limited by the physical spare position for optimized placement. In the case of row spares with a 1-D spare segments structure, only physically located column lines can be repaired. In contrast, if column spares with a 1-D spare segments structure are applied, III. PROPOSED IDEA The proposed BIRA algorithm proceeds in the order of fault collection followed by fault-analysis to optimize the efficiency of repair. In the fault-collection phase, faults received from the built-in self-test (BIST) are stored in two CAMs, and allocation is performed for the must-repair line faults and a fault sharing address of spare applied 1-D spare segments. In the fault-analysis phase, allocation of faults stored in the CAM is performed using an intuitive algorithm. A. Fault Collection The BIST tests the memory through various algorithms, and the addresses of the faults occurring during the test are transferred to the CAM in real time. The CAM size should be minimized to reduce the hardware requirement for storing the address of faults. If all fault addresses are stored without specific conditions, the CAM size to store is needed as much as the memory size being tested. Therefore, in the proposed BIRA, the spare pivot address used in many BIRAs, such as ESP, SFCC, and Branch, is applied to reduce the CAM size [5], [7], [8], as shown in Fig. 3. The concept of a spare pivot used in the fault-collection phase of the proposed BIRA was introduced in [5]. The fault-storing CAM of the proposed BIRA comprises a main CAM and a sub CAM. Fig. 3 shows the CAM structure of the proposed BIRA for an M N memory block with Rs spare rows and Cs spare columns. The column (row) address can be represented using the segment address and sequence in the segment when the 1-D spare segments structure is applied to the spare row (column). The row spare for the memory in Fig. 1 comprises four spare segments (D = 4), and a fault with column address 3 can be described with segment address (S) 1 and sequence in the segment (SS) 1. The number of main CAM addresses is equal to the number of spares (i.e., Rs + Cs), which is the same as Branch. The sub CAM is used when the column address of incoming fault is the same as the existing main CAM addresses, and the number of sub CAM addresses is Rs(Cs 1) + Cs(Rs 1). The faults stored in the main CAM have different row and column addresses in comparison with other faults stored in the main CAM. The faults stored in the sub CAM depend on the spare direction applied to the 1-D spare segments structure. As mentioned, the direction of the 1-D spare segments structure can be changed depending on the features of the memory and the spare allocation cost. In this brief, the 1-D spare segments structure is applied to row spares, as shown in Fig. 2(b). When a new fault is transferred from the BIST, its addresses are compared with those of the faults stored in the main CAM. If a

3 208 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 1, JANUARY 2018 Fig. 4. Example of the fault-collection process of the proposed BIRA. column address matches, then the fault is stored in the sub CAM. If a row address matches, then spare allocation for the incoming fault is performed. Further, if the segment address also matches, then the allocation row flag of the main CAM is set to 1. Fig. 4 shows the fault-collection process of the proposed BIRA. Fig. 4(a) shows the fault distribution of memory with two column spares and two row spares. The example memory has the spare segments structure along the row direction. Fig. 4(b) presents the addresses of the 10 faults in their detection order. The fourth and fifth columns of Fig. 4(b) represent the column addresses in the segment and sequence of segment, respectively. Both the main CAM space and the sub CAM space are initialized when the fault-collection process starts. Fig. 4(c) (g) demonstrates the fault-collection process for efficient storage and processing of fault information. The first fault [i.e., cell (1,0,1)] is stored in the main CAM as the first fault detected. The second fault [i.e., cell (0,0,0)] does not share the address with the existing fault stored in the main CAM, so it is stored in the main CAM. The third fault [i.e., cell (0,3,1)] shares the row address of the second main CAM address, so allocation is performed using row spare segments. The fourth incoming fault [i.e., cell (3,2,1)], like the second fault, is stored in the main CAM because it does not share its address with the existing main CAM addresses. The fifth fault [i.e., cell (3,2,0)] has the same row address and segment number as the third main CAM address (the fourth fault), so allocation using row spare segments is performed and the allocation row flag of the third main CAM address is set to 1. The sixth fault [i.e., cell (2,3,0)] is also stored in the main CAM for the same reasons as the second fault and the fourth fault. The seventh and eighth faults [i.e., cells (4,3,0) and (6,0,1)] are stored in the sub CAM because they have the same column addresses (i.e., segment and the sequence in the segment) as the existing faults in the main CAM, as shown in Fig. 4(f). The seventh and eighth faults share their column addresses with the fourth fault and first fault of the main CAM, respectively. The ninth fault [i.e., cell (7,0,0)] is also stored in the sub CAM since it shares the column address of the second main CAM address. The tenth fault [i.e., cell (5,3,0)] shares the column address of the fourth main CAM address (the seventh fault). When two or more faults share the same column address, allocation using column spares is utilized because it is a must-repair line condition, which is the number of faults that exceeds the number of row spares. Also, the allocation column flag is set to 1 and the enable flag of the related sub CAM address is set to 0. The fault-collection process concludes when the last fault is transferred from the BIST, as shown in Fig. 4(g). In the fault-collection process, the address information for the fault-analysis process was stored in the main CAM and the sub CAM, and spare allocation was promptly performed in the direction ofthe1-dsparesegments. B. Fault Analysis The proposed BIRA analyzer uses an intuitive algorithm and 1-D spare segment structure to improve the repair rate and lower the hardware overhead. After the fault-collection process of spare allocation for a shared fault, such as a must-repair line fault, the main CAM, and the sub CAM are used for spare allocation in the following two simple steps. Step 1: Column spare allocation. Step 2: Row spare segment allocation. Both Step 1 and Step 2 start with sub CAM and then move to the main CAM. In Step 1, allocating for the sub CAM first is efficient because the address stored in the sub CAM has the same column address. The allocation column flag of the related main CAM address is set to 1 simultaneously with the column spare allocation. If any spare columns for faults in the sub CAM remain after allocation, then spare column allocation is performed for the main CAM addresses, and the allocation column flag is set to 1. In Step 2, row spare segment allocation is performed first for the unallocated faults of the sub CAM. Next, row spare segment allocation is performed for the address of the main CAM. The enable flag equal to 0 and the allocation row/column flag equal to 1 indicates that the direction of spares to allocate has been determined. Thus, in Fig. 5(a), the first and second main CAM addresses and second and third sub CAM addresses require spare allocation. When the fault-analysis process reaches the stage in Fig. 5(a), only the second sub CAM address is allocated to the column spare in Step 1 because the number of remaining spare columns is one. Also, the enable flag of the second sub CAM and the allocation column flag of the related main CAM address are set to 0 and 1, respectively. In Step 2, the third sub CAM address and the second main CAM address are allocated to row spare segments and the enable flag and the allocation row flag are set to 0 and 1, respectively, as shown in Fig. 5(c). After the faultanalysis process is completed, two column spares are used, and the used row spares are segments 0, 2, and 3 of spare row 1 and segment 0

4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 1, JANUARY TABLE I HARDWARE OVERHEAD IN TERMS OF THE FAULT ANALYZER BETWEEN BRANCH AND THE PROPOSED BIRA Fig. 5. Example of the fault-analysis process for the proposed BIRA. (a) After the fault-collection process. (b) Column allocation. (c) Row allocation. Fig. 6. Repair rate of Branch and the proposed BIRA (M = 1024, N = 1024). (a) Two spare rows and two spare columns. (b) Three spare rows and three spare columns. (c) Four spare rows and four spare columns. (d) Five spare rows and five spare columns. (e) Two spare rows and four spare columns. (f) Four spare rows and two spare columns. of spare row 2. As described above, the fault-analysis process of the proposed BIRA comprises an intuitive algorithm; therefore, it can be implemented with low hardware overhead. IV. EXPERIMENTAL RESULTS In the previous section, repair rate and hardware overhead of the three key features are important for the competitiveness of the BIRA. This is because hardware overhead is related to chip size and repair rate is related to yield. However, the analysis speed can vary with other factors such as the clock speed. A simulator made in C language is used for randomly generated faults to estimate the repair rate and Verilog HDL is used to verify the hardware overhead for the proposed BIRA. Fig. 6 shows a comparison of repair rate obtained by the proposed BIRA for various spare conditions in comparison with that of Branch a competitive BIRA with the lowest hardware overhead among other existing BIRAs and an optimal repair rate. Fig. 7. Relation between repair rate and hardware overhead. The experiment is performed times using 1 Mb of memory. Fig. 6(a) (d) shows the repair rate for the same ratio of row spares and column spares. Note, however, that Fig. 6(e) and (f) are different. The experimental results show that the repair rate of the proposed BIRA is higher than that of Branch and that the repair rate of the proposed BIRA tends to increase as the number of segments increases, regardless of the abovementioned ratio of spares. Although many segments are useful in terms of repair rate, hardware overhead should also be considered. Table I shows the hardware overhead of Branch and the proposed BIRA in terms of the fault analyzer. The CAM size used by the fault-collection process does not differ much between proposed BIRA and Branch. Therefore, the hardware overhead of the fault analyzer demonstrates the competitiveness of the hardware overhead of the proposed BIRA. As shown in Table I, the hardware overhead of the fault analyzer is reduced by 60% at 2/2 spares (two spare rows and two spare columns) and by 85% at 3/3 spares (three spare rows and three spare columns) compared with the hardware overhead of Branch. In addition, the hardware overhead growth of the proposed BIRA is not high depending on the number of segments. That is, the proposed BIRA has a competitive hardware overhead compared with that of Branch. In the proposed BIRA, the number of segments is related to both repair rate and hardware overhead. In the spare structure with many segments, the repair rate is high but the hardware overhead is also high. In other words, hardware overhead and repair rate are a tradeoff. Fig. 7 shows the relation between repair rate and hardware overhead when the number of faults is 10 for both Branch and the proposed BIRA. In Fig. 7, the x-axis represents the repair rate, the y-axis represents the hardware overhead, and the points represent the data points of Branch and the proposed BIRA. The relation between repair rate and hardware overhead is explored by comparing Branch and the proposed BIRA at 2/2 spares and 3/3 spares. In the case of the proposed BIRA, in comparison with Branch, the repair rate is higher and hardware overhead is lower at both 2/2 spares

5 210 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 1, JANUARY 2018 and 3/3 spares. In the case of 3/3 spares, the point of the proposed BIRA is closer to the lower-right-hand corner than the point of Branch. In other words, the proposed BIRA is more competitive BIRA. In Fig. 7, the repair rate of the proposed BIRA is higher than that of Branch and the hardware overhead is lower, irrespective of the number of segments. In the case of 3/3 spares, Fig. 7 shows that considering the hardware overhead and the repair rate, the mosteffective number of segments is four, because repair rate improvement is greater than the corresponding increase in hardware overhead. The results for the proposed BIRA with eight and sixteen segments only slightly exceed those with four segments but demonstrate significantly higher growth in hardware overhead. The proposed BIRA has a higher repair rate and a lower hardware overhead compared to other existing BIRAs with optimal repair rates (100% normalized repair rate). V. CONCLUSION The proposed BIRA using 1-D spare segments structure has a higher repair rate than the optimal repair rate obtained using the conventional spare structure, and the hardware overhead of the proposed BIRA s fault analyzer is significantly reduced in comparison with Branch, which is a state-of-the-art BIRA with the lowest hardware overhead and an optimal repair rate. Thus, the proposed BIRA, in terms of repair rate and hardware overhead, is a competitive solution for the embedded memory that affects the size of a SoC. REFERENCES [1] Y.-Y. Hasio, C.-H. Chen, and C.-W. Wu, Built-in self-repair schemes for flash memories, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, no. 8, pp , Aug [2] S.-Y. Kuo and W. K. Fuchs, Efficient spare allocation for reconfigurable arrays, IEEE Des. Test Comput., vol. 4, no. 1, pp , Feb [3] M. Tarr, D. Boudreau, and R. Murphy, Defect analysis system speeds test and repair of redundant memories, Electronics, vol. 57, no. 1, pp , Jan [4] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, A built-in self-repair analyzer (CRESTA) for embedded DRAMs, in Proc. Int. Test Conf., Oct. 2000, pp [5] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, Built-in redundancy analysis for memory yield improvement, IEEE Trans. Rel., vol. 52, no. 4, pp , Dec [6] P. Ohler, S. Hellebrand, and H.-J. Wunderlich, An integrated built-in test and repair approach for memories with 2D redundancy, in Proc. Eur. Test Symp. (ETS), May 2007, pp [7] W. Jeong, I. Kang, K. Jin, and S. Kang, A fast built-in redundancy analysis for memories with optimal repair rate using a line-based search tree, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 12, pp , Dec [8] W. Jeong, J. Lee, T. Han, K. Lee, and S. Kang, An advanced BIRA for memories with an optimal repair rate and fast analysis speed by using a branch analyzer, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, no. 12, pp , Dec [9] W. Kang, H. Cho, J. Lee, and S. Kang, A BIRA for memories with an optimal repair rate using spare memories for area reduction, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 11, pp , Nov [10] D.-H. Kim and L. S. Milor, ECC-ASPIRIN: An ECC-assisted postpackage repair scheme for aging errors in DRAMs, in Proc. IEEE VLSI Test Symp. (VTS), Apr. 2016, pp [11] J. Kim, W. Lee, K. Cho, and S. Kang, Hardware-efficient built-in redundancy analysis for memory with various spares, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 3, pp , Mar [12] H.-H. Liu et al., A built-off self-repair scheme for channel-based 3D memories, IEEE Trans. Comput., vol. 66, no. 8, pp , Aug

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