Hardware Design and Simulation for Verification
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1 Hardware Design and Simulation for Verification by N. Bombieri, F. Fummi, and G. Pravadelli Universit`a di Verona, Italy (in M. Bernardo and A. Cimatti Eds., Formal Methods for Hardware Verification, Lecture Notes in Computer Science 3965, 2006, Springer) This paper is intended to provide a general view on simulation-based modeling and verification strategies for developing embedded systems. In particular, it describes state-of-the art co-simulation approaches and verification strategies based on fault simulation and assertion checking.
2 Embedded system design (1) In a classical design modeling flow, system level is refined by applying the transactional level modeling (TLM) style. A TLM-based design flow starts from an abstract system description and evolves toward more detailed implementations till it gets to RTL.
3 Embedded system design (2) Verification activity involves three main phases: The design implemented at the higher abstraction level is validated considering the system functionality. Once the design is optimized following architecture exploration and performance analysis, it is validated taking into account the temporal behavior. Whenever a step of the refinement flow implies a change in the system design, a further verification check is required in order to preserve the golden model functionality ascertained at the preceding step.
4 Embedded system design flow (1)
5 Embedded system design flow (2)
6 TLM levels use and features
7 Key Concepts in TLM 1. To implement a system at higher level means to implement the system in a more abstract way, that is to leave implementation details in order (mainly) to speed-up simulation for functional verification purposes. 2. To implement a system at lower level means to add implementation details to the system in order to simulate it in a more accurate way (for performance analysis purpose).
8 Typical TLM-based SoC design flow (1) System modeling (TL3). Informal specification and system constraints are analyzed to provide a system level model of the design. HW/SW partitioning and architecture mapping (TL2, TL1). The system level description is then mapped onto an architecture to obtain a transactional level model. This requires to decide which tasks will be implemented by SW and which ones by HW.
9 Typical TLM-based SoC design flow (2) In HW-SW Partitioning, the designers must select: programmable device where the SW will run; memory model; HW/SW communication architecture and bus topology; HW technology (ASIC, FPGA, etc.) where HW tasks will be mapped. SW coding. After partitioning, SW and HW parts follow a different design flow. In particular, SW tasks are implemented by using a programming language SW compilation. After the coding, the SW is compiled to object code.
10 Typical TLM-based SoC design flow (3) Interface definition. Splitting the design tasks in HW components and pieces of SW introduces the need for an interface between the two parts that, often, is not specified in the initial requirements. HDL modeling and HW partitioning. The HW model generated at the transactional level must be refined and optimized by executing different synthesis steps to obtain a gate-level description.
11 Typical TLM-based SoC design flow (4) Behavioral synthesis and IP reuse. The functional/behavioral model of each HW component is further refined into a Register Transfer Level (RTL) model by means of behavioral synthesis. Logic Synthesis. Finally, logic synthesis is used to translate the RTL model to a gate-level model.
12 Design Simulation Dynamic verification faces the correctness of a design by means of simulation based techniques. In dynamic verification the model functionality is essentially verified by generating a high number of input stimuli (test set) that are simulated to observe the behavior of the design under verification (DUV) at primary outputs. The test set generated at a specific abstraction level can be re-used (and possibly incremented) at the lower levels after each synthesis step up to manufacturing test.
13 Design Simulation Traditional simulation-based approaches can be adopted to verify the whole embedded system before HW/SW partitioning, as well as, HW and SW components separately after HW/SW partitioning. However, the most challenging task is to perform co-verification between HW and SW components. The integration and the synchronization of HW and SW modules requires a permanent control of consistency and correctness that can be efficiently achieved only by exploiting a co-simulation environment.
14 Co-simulation environments (1) Homogeneous Environments. Homogeneous environments use a single engine for the simulation of both HW and SW components
15 Co-simulation environments (2) Heterogeneous environments ensure a more accurate tuning between HW and SW components.
16 Co-simulation environments (3) Most of the heterogeneous frameworks essentially address the same problem: how to efficiently link an event-driven hardware simulator and a cycle-based Instruction Set Simulator (ISS). An ISS provides an accurate simulation of a programmable device allowing to verify SW before hardware is available.
17 Co-simulation environments (4) Semi-Homogeneous Environments. The advent of design flows based on SystemC allowed the definition of efficient semi-homogeneous approaches. In these semi-homogeneous approaches, the bus is not modeled at signal level. Rather, the bus is usually modeled with a small number of simple functions which provide information on the time required by the communication, without the need to evaluate each signal.
18 Co-simulation environments Semi-homogeneous approaches are homogeneous from the language point of view, since both HW and SW are described using C++ constructs. However, these semi-homogeneous approaches are heterogeneous from the simulation point of view, since HW and SW can be executed using different simulators: the SystemC simulation kernel for the HW components and an ISS for the SW programs.
19 Semi-homogeneous environment based on SystemC and ISS
20 Semi-homogeneous environment based on SystemC and ISS Interprocess communication (IPC). IPC is a software mechanism to allow different processes to communicate, even on different computers. It is used to realize the communication between the ISS, where SW runs in its binary form, and the SystemC simulator, that models HW. Bus wrapper. A wrapper is a SW layer which allows an existing piece of software to interact with an environment that is different from its originally intended one. The bus wrapper allows the use of a high level model of the bus within an environment where the SW model is cycle-accurate and the HW is modeled at a signal-accurate level of abstraction.
21 Simulation for Verification Simulation techniques for embedded systems verification are classified in two main categories: Simulation by testbenches. Assertion-based verification.
22 Simulation by testbenches Simulation techniques based on testbenches essentially validate the model functionality by dynamically generating a high number on input stimuli (test set) that are simulated to observe the behavior of the design under verification (DUV) at primary outputs. What we need to perform such a dynamic verification is: a simulatable model of the design, a simulator, a testbench to apply stimuli to the primary input of the design, and a method to establish the correctness of the design with respect to the results of the simulation.
23 Simulation by testbenches Generally, the stimuli generator and the simulation engine are integrated in a single SW application, called automatic test pattern generator (ATPG). Two kinds of dynamic verification: Logic Simulation and Fault Simulation.
24 Logic Simulation Logic simulation. In logic simulation, the quality of the set of stimuli is measured by using code coverage. This is a class of metrics that has been used in software engineering for quite some time to analyze whether test suites cover the required functionality. The most popular metrics adopted in logic simulation are: statement coverage, condition coverage and path coverage.
25 Fault Simulation Fault simulation consists of simulating a design in presence of logical faults, which emulate the effect of physical faults on the behavior of a system description. Comparing the fault simulation results with those of the fault-free simulation of the same design, simulated by using the same test set, we can determine the fault coverage as the ratio between the number of faults detected by the test set and the number of simulated faults.
26 Assertion Based Verification Functional verification based on assertions represents a valuable alternative to fault simulation. Assertion-based verification (ABV) joins formal verification and simulation based verification to provide a more powerful and easy way to verify complex digital systems.
27 Fault simulation and ABV Fault simulation and ABV are generally faster than formal verification techniques. This motivates the recent trend of proposing design and verification methodologies based on TLM, simulation and ABV. Reuse of IP-cores, testbenches and properties in a mixed TL-RTL design and verification flow
28 Mixed TL-RTL design and verification flow
29 Role of Transactor in TBV
30 Role of Transactor in TBV Transactor is exploited to reuse TL testbenches and assertions on the RTL design. The testbench carries out one transaction at time, composed by two TL function calls (write() and read()). First, data are provided to the RTL design by means of write(addr, data). The transactor converts the write() call to the RTL protocol-dependent sequence of signals required to drive control and data inputs of the design under verification.
31 Role of Transactor in TBV Moreover, the write status is reported to the testbench to notify about successes or errors. Then, the testbench asks for the DUV result by calling read(addr, &res). The transactor waits until the DUV result is ready by monitoring the output control ports, and, finally, after it gets the output data, testbench carries on with the next transaction.
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