Shared Memory Multiprocessors. Symmetric Shared Memory Architecture (SMP) Cache Coherence. Cache Coherence Mechanism. Interconnection Network

Transcription

1 Shared Memory Multis Processor Processor Processor i Processor n Symmetric Shared Memory Architecture (SMP) cache cache cache cache Interconnection Network Main Memory I/O System Cache Coherence Cache Coherence Mechanism Time Event A reads X Cache Contents for CPU A Cache Contents for CPU B Memory contents for location X Snooping protocol write invalidate write update Directory based protocol A stores in X Processor p: WRITE X READ X Processor p: WRITE X Processor q: READ X Processor p: WRITE X () Processor q: WRITE X () Time Event A reads X A stores in X Bus Activity invalidation for X CPU A CPU B location X

2 Cache Coherence Mechanism Basic Implementation Techniques Write update protocol requires higher bandwidth Time Event A reads X A stores in X Bus Activity write broadcast for X cache hit for X CPU A CPU B location X Bus is used for the invalidation Processors snoop the Bus serialization forces the writes to be serialized Cache tag matching is used for snooping A finite state machine to keep track of the state of the cache line invalid,, In multilevel cache, snooping activity happens at the highest level Cache Coherence Actions Request Source State of block or invalid invalid Request Source State of block Function and explanation or invalid invalid Read data in cache Place read miss on address conflict miss; place read miss on address conflict miss;, then place read miss on write data in cache place write miss on place write miss on address conflict miss; place write miss on address conflict miss;, then place write miss on No action; allow memory to service read miss Attempt to share data; place cache block on and change state to Attempt to write block; invalidate the block Attempt to write a block that is elsewhere; write back the cache block and make its state invalid

3 An Example Protocol An Example Protocol Invalid Invalid place write miss on Exclusive Exclusive read/write read/write hit CPU read place read miss on place read miss on read read only only place write miss on miss write back cache block place write miss on place read miss on write miss for this block Invalid Invalid abort memory access Exclusive Exclusive read/write read/write write miss for this block read miss for this block abort memory access read read only only Cache state transition based on requests from CPU Cache state transition based on requests from the write back cache block write miss for block An Example Protocol Invalid Invalid place write miss on Exclusive Exclusive read/write read/write hit write miss for this block CPU read place read miss on place read miss on miss place write miss on read miss for block write back cache block place write miss on read read only only place read miss on Cache Performance of SMP Uni cache miss Cache miss caused by sharing and invalidation true sharing, false sharing Cache state transition induced by the local and the

4 Performance Measurement of the Commercial Workload OLTP DSS AltaVista L cache: KB direct mapped on-chip cache, block size bytes write through L using write buffer L 9 KB on-chip, three-way set associative bytes block size L off chip direct mapped MB cache Bytes block size The execution time break down Performance of OLTP Vs Cache Size

5 Performance of OLTP Vs Cache Size Memory access time Vs Processor count Misses Vs Block size Scientific Workload Data Miss Rate Vs Processor count capacity miss rate coherence miss rate Barnes LU 9 7 FFT Ocean

6 Data Miss Rate vs Cache Size capacity miss rate coherence miss rate Bus Traffic vs Block Size 9 7. FFT Barnes 7 Barnes LU FFT Ocean.. LU Ocean