Shared Memory Architectures. Shared Memory Multiprocessors. Caches and Cache Coherence. Cache Memories. Cache Memories Write Operation

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1 hared Architectures hared Multiprocessors ngo ander hared Multiprocessor are often used pecial Class: ymmetric Multiprocessors (MP) o ymmetric access to all of main from any processor A shared programming model has a direct representation in hardware s o ncrease performance o Demand cache coherence and consistency protocols ngo ander - 2B1447 OC Architecture 1 ngo ander - 2B1447 OC Architecture 2 s and Coherence Memories s play key role in all cases o Reduce average data access time o Reduce bandwidth demands placed on shared interconnect But private processor caches create a problem o Copies of a variable can be present in multiple caches o A write by one processor may not become visible to others They ll keep accessing stale value in their caches o coherence problem o Need to take actions to ensure visibility ngo ander - 2B1447 OC Architecture 3 Processor Main A cache is used to reduce the access time to misses can occur since the cache is much smaller than the The decision which parts of the reside in the cache is taken by a replacementalgorithm There are different protocols for a write operation: Write-Back and Write-Through ngo ander - 2B1447 OC Architecture 4 Memories Operation Memories Write Operation Processor Main Processor Main f the location is in the cache (cache hit), the data is read from the cache. f the location is not in the cache (cache miss), the data is read from and the cache is updated with this location (or block containing this location). ngo ander - 2B1447 OC Architecture 5 Write-Through Protocol o A write operation updates the cache location and the main simultaneneously Write-Back Protocol o A write operation updates only the cache location and marks it as updated with an associated flag bit o The main is updated later, when the block containing the marked address is removed from the cache. ngo ander - 2B1447 OC Architecture 6 1

2 hared Architecture -shared hared P 1 P m witch everal processors are connected via a switch with a shared Has been used for a very small number of processors s difficult to use for a large number of processors, since the shared cache must deliver an extremely large bandwidth P 1 P m The interconnect is a shared bus between the processors local caches and the Has been used up to 20 to 30 processors caling is limited due to the bandwidth limitations of the shared bus ngo ander - 2B1447 OC Architecture 7 ngo ander - 2B1447 OC Architecture 8 Dancehall Architecture Distributed P 1 P m nterconnection Network calable Point-to- Point Network placed between caches and modules that together form the main Due to the size of the interconnection network, the can be very far from the processors P 1 P m nterconnection Network No symmetric approach. The local is much closer than the rest of the global. tructure works very well with scaling mportant in the design to use the local efficiently. ngo ander - 2B1447 OC Architecture 9 ngo ander - 2B1447 OC Architecture 10 s Coherence Problem s Coherence Problem ingle Processor running 3 processes ingle Processor running 3 processes 1. P1 reads location u (value 5) from main 2. P3 reads location u from main 3. P3 writes u, changing the value to 7 4. P1 reads value u again 5. P2 reads location u from main 1. P1 reads location u (value 5) from main o and are updated () ngo ander - 2B1447 OC Architecture 11 ngo ander - 2B1447 OC Architecture 12 2

3 s Coherence Problem s Coherence Problem ingle Processor running 3 processes Write Back ingle Processor running 3 processes 2. P3 reads location u from main o and have still the value 3. P3 writes u, changing the value to 7 o is updated () and u is marked. is not changed! ngo ander - 2B1447 OC Architecture 13 ngo ander - 2B1447 OC Architecture 14 s Coherence Problem s Coherence Problem ingle Processor running 3 processes ingle Processor running 3 processes 4. P1 reads value u again o ince cache is common to all processes, there is no problem though the main is not updated! All processes have the same view of the cache! 5. P2 reads location u from main o ince cache is common to all processes, there is no problem though the main is not updated! All processes have the same view of the cache! ngo ander - 2B1447 OC Architecture 15 ngo ander - 2B1447 OC Architecture 16 Coherence Problem f only a uniprocessor is involved there is no cache coherence problem! However, if a DMA is involved that has direct access, the cache may not represent the contents of the and the cache coherence problem can occur! Coherence Problem 1. P1 reads location u (value 5) from main 2. P3 reads location u from main 3. P3 writes u, changing the value to 7 4. P1 reads value u again 5. P2 reads location u from main ngo ander - 2B1447 OC Architecture 17 ngo ander - 2B1447 OC Architecture 18 3

4 Coherence Problem (Write-Through ) Coherence Problem (Write-Through ) 1. P1 reads location u (value 5) from main o P1 s cache is updated () 2. P3 reads location u from main o P3 s cache is updated () ngo ander - 2B1447 OC Architecture 19 ngo ander - 2B1447 OC Architecture 20 Coherence Problem (Write-Through ) Coherence Problem (Write-Through ) Write Through 3. P3 writes u, changing the value to 7 o P3 s cache and main updates () 4. P1 reads value u again o P1 reads the value from the cache (), which is not the correct value! ngo ander - 2B1447 OC Architecture 21 ngo ander - 2B1447 OC Architecture 22 Coherence Problem (Write-Through ) Coherence Problem (Write-Back ) 5. P2 reads location u from main o P2 reads the value from the main () 1. P1 reads location u (value 5) from main o P1 s cache is updated () ngo ander - 2B1447 OC Architecture 23 ngo ander - 2B1447 OC Architecture 24 4

5 Coherence Problem (Write-Back ) Coherence Problem (Write-Back ) Write Back 2. P3 reads location u from main o P3 s cache is updated () 3. P3 writes u, changing the value to 7 o P3 s cache is updated () and location u is marked o Main is NOT updated! ngo ander - 2B1447 OC Architecture 25 ngo ander - 2B1447 OC Architecture 26 Coherence Problem (Write-Back ) Coherence Problem (Write-Back ) 4. P1 reads value u again o P1 reads the value from the cache (), which is not the correct value! 5. P2 reads location u from main o P2 reads the value from the cache (), which is not the correct value! ngo ander - 2B1447 OC Architecture 27 ngo ander - 2B1447 OC Architecture 28 Coherence Problems with the ntuition ince communication between processors is done by means of shared cache coherence must be guaranteed. The hardware should support cache coherence! Recall: alue returned by read should be last value written But last is not well-defined on a parallel architecture n parallel case, program order defined within a process, but need to make sense of orders across processes Must define a meaningful semantics ngo ander - 2B1447 OC Architecture 29 ngo ander - 2B1447 OC Architecture 30 5

6 ome Basic Definitions ome Basic Definitions Extend from definitions in uniprocessors to those in multiprocessors operation: a single read (load), write (store) or read-modifywrite access to a location o Assumed to execute atomically w.r.t each other ssue: a operation issues when it leaves processor s internal environment and is presented to system (cache, buffer ) Perform: operation appears to have taken place, as far as processor can tell from other operations it issues o A write performs w.r.t. the processor when a subsequent read by the processor returns the value of that write or a later write o A read perform w.r.t the processor when subsequent writes issued by the processor cannot affect the value returned by the read n multiprocessors, stay same but replace the by a processor o Also, complete: perform with respect to all processors o till need to make sense of order in operations from different processes ngo ander - 2B1447 OC Architecture 31 ngo ander - 2B1447 OC Architecture 32 harpening the ntuition harpening the ntuition magine a single shared and no caches o Every read and write to a location accesses the same physical location o Operation completes when it does so imposes a serial or total order on operations to the location o Operations to the location from a given processor are in program order o The order of operations to the location from different processors is some interleaving that preserves the individual program orders Last now means most recent in a hypothetical serial order that maintains these properties For the serial order to be consistent, all processors must see writes to the location in the same order (if they bother to look, i.e. to read) Note that the total order is never really constructed in real systems o Don t even want, or any hardware, to see all operations But program should behave as if some serial order is enforced o Order in which things appear to happen, not actually happen ngo ander - 2B1447 OC Architecture 33 ngo ander - 2B1447 OC Architecture 34 Formal Definition of Coherence Results of a program: values returned by its read operations A system is coherent if the results of any execution of a program are such that for each location, it is possible to construct a hypothetical serial order of all operations to the location that is consistent with the results of the execution and in which: 1. operations issued by any particular process occur in the order issued by that process, and 2. the value returned by a read is the value written by the last write to that location in the serial order ngo ander - 2B1447 OC Architecture 35 Formal Definition of Coherence Two necessary features: o Write propagation: value written must become visible to others o Write serialization: writes to location seen in same order by all if see w1 after w2, you should not see w2 before w1 no need for analogous read serialization since reads not visible to others ngo ander - 2B1447 OC Architecture 36 6

7 Coherence Using a Coherence Using a Built on top of two fundamentals of uniprocessor systems o transactions o tate transition diagram in cache Uniprocessor bus transaction: o Three phases: arbitration, command/address, data transfer o All devices observe addresses, one is responsible Uniprocessor cache states: o Effectively, every block is a finite state machine o Write-through, write no-allocate has two states: valid, invalid o Writeback caches have one more state: modified ( dirty ) Multiprocessors extend both these somewhat to implement coherence ngo ander - 2B1447 OC Architecture 37 ngo ander - 2B1447 OC Architecture 38 nooping-based Coherence Basic dea Transactions on bus are visible to all processors Processors or their representatives can snoop (monitor) bus and take action on relevant events (e.g. change state) nooping-based Coherence mplementing a Protocol controller now receives inputs from both sides: o Requests from processor, bus requests/responses from snooper n either case, takes zero or more actions o Updates state, responds with data, generates new bus transactions Protocol is distributed algorithm: cooperating state machines o et of states, state transition diagram, actions Granularity of coherence is typically cache block o Like that of allocation in cache and transfer to/from cache ngo ander - 2B1447 OC Architecture 39 ngo ander - 2B1447 OC Architecture 40 Coherence with Write- Through s tate Transition Diagram Write-Through P 1 nooping Key extensions to uniprocessor: snooping, invalidating/updating caches o no new states or bus transactions in this case o invalidation- versus update-based protocols Write propagation: even in invalidation case, later reads will see new value o invalidation causes miss on later access, and up-to-date via write-through P n - Transition ngo ander - 2B1447 OC Architecture 41 PrWr/Wr PrRd/Rd PrRd/- Wr/- Processor-initiated transactions -snooper-initiated transactions PrWr/Wr Protocol is executed for each cachecontroller connected to a processor Controller receives inputs from processor and bus ngo ander - 2B1447 OC Architecture 42 7

8 tate Transition Diagram Write-Through Two states per block in each cache, as in uniprocessor Hardware state bits associated with only blocks that are in the cache o other blocks can be seen as being in invalid (not-present) state in that cache Write will invalidate all other caches (no local change of state) o can have multiple simultaneous readers of block,but write invalidates them Ordering All Writes appear on the bus misses: appear on bus, and will see last write in bus order hits: do not appear on bus o But value read was placed in cache by either most recent write by this processor, or most recent read miss by this processor o Both these transactions appear on the bus o o reads hits also see values as being produced in consistent bus order ngo ander - 2B1447 OC Architecture 43 ngo ander - 2B1447 OC Architecture 44 Problem with Write-Through Example of Orders High bandwidth requirements o Every write from every processor goes to shared bus and o Write-through especially unpopular for ymmetric Multi-Processors Write-back caches absorb most writes as cache hits o Write hits don t go on bus o But now how do we ensure write propagation and serialization? o Need more sophisticated protocols: large design space /*Assume initial values of A and B are0*/ (1a) A = 1; (2a) print B; (1b) B = 2; (2b) print A; What s the intuition? Whatever it is, we need an ordering model for clear semantics o across different locations as well o so programmers can reason about what results are possible This is the consistency model ngo ander - 2B1447 OC Architecture 45 ngo ander - 2B1447 OC Architecture 46 Consistency Model Consistency Model pecifies constraints on the order in which operations (from any process) can appear to execute with respect to one another o What orders are preserved? o Given a load, constrains the possible values returned by it Without it, can t tell much about an hared based program s execution mplications for both programmer and system designer o Programmer uses to reason about correctness and possible results o ystem designer can use to constrain how much accesses can be reordered by compiler or hardware Contract between programmer and system ngo ander - 2B1447 OC Architecture 47 ngo ander - 2B1447 OC Architecture 48 8

9 equential Consistency A multiprocessor is sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program. [Lamport, 1979] equential Consistency Processors issuing references as per program order P n The switch is randomly set after each reference (as if there were no caches, and a single ) Total order achieved by interleaving accesses from different processes Maintains program order, and operations, from all processes, appear to [issue, execute, complete] atomically w.r.t. others Programmer s intuition is maintained ngo ander - 2B1447 OC Architecture 49 ngo ander - 2B1447 OC Architecture 50 C Example mplementing C /*Assume initial values of A and B are0*/ (1a) A = 1; (2a) print B; (1b) B = 2; (2b) print A; What matters is order in which appears to execute, not executes o possible outcomes for (A,B): (0,0), (1,0), (1,2); impossible under C: (0,2) we know 1a->1b and 2a->2b by program order A = 0 implies 2b->1a, which implies 2a->1b B = 2 implies 1b->2a, which leads to a contradiction o BUT, actual execution 1b->1a->2b->2a is C, despite not program order appears just like 1a->1b->2a->2b as visible from results o actual execution 1b->2a->2b-> 1a is not C Two kinds of requirements o Program order operations issued by a process must appear to become visible (to others and itself) in program order o Atomicity in the overall total order, one operation should appear to complete with respect to all processes before the next one is issued needed to guarantee that total order is consistent across processes tricky part is making writes atomic ngo ander - 2B1447 OC Architecture 51 ngo ander - 2B1447 OC Architecture 52 Write Atomicity Write Atomicity Write Atomicity: Position in total order at which a write appears to perform should be the same for all processes o Nothing a process does after it has seen the new value produced by a write W should be visible to other processes until they too have seen W o n effect, extends write serialization to writes from multiple processes A=1; while (A==0); B=1; while (B==0); print A; Transitivity implies A should print as 1 under C Problem if P 2 leaves loop, writes B, and sees new B but old A (from its cache, say) ngo ander - 2B1447 OC Architecture 53 ngo ander - 2B1447 OC Architecture 54 9

10 ufficient Conditions for C ufficient Conditions for C ufficient, not necessary, conditions o Every process issues operations in program order o After a write operation is issued, the issuing process waits for the write to complete before issuing its next operation o After a read operation is issued, the issuing process waits for the read to complete, and for the write whose value is being returned by the read to complete, before issuing its next operation (provides write atomicity) Clearly, compilers should not reorder for C, but they do! o Loop transformations, register allocation (eliminates!) Even if issued in order, hardware may violate for better performance o Write buffers, out of order execution Reason: uniprocessors care only about dependences to same location o Makes the sufficient conditions very restrictive for performance ngo ander - 2B1447 OC Architecture 55 ngo ander - 2B1447 OC Architecture 56 tate Transition Diagram Write-Through PrWr/Wr PrRd/Rd PrRd/- Wr/- Processor-initiated transactions -snooper-initiated transactions PrWr/Wr Two-state write through protocol provides sequential consistency! Write Back caches require more complex protocols Design pace for nooping Protocols No need to change processor, main, cache o Extend cache controller and exploit bus (provides serialization) Focus on protocols for write-back caches Dirty state now also indicates exclusive ownership o Exclusive: only cache with a valid copy (main may be too) o Owner: responsible for supplying block upon a request for it Design space o nvalidation versus Update-based protocols o et of states ngo ander - 2B1447 OC Architecture 57 ngo ander - 2B1447 OC Architecture 58 nvalidation-based Protocols nvalidation-based Protocols Exclusive means can modify without notifying anyone else o i.e. without bus transaction o Must first get block in exclusive state before writing into it o Even if already in valid state, need transaction, so called a write miss tore to non-dirty data generates a readexclusive bus transaction o o Tells others about impending write, obtains exclusive ownership makes the write visible, i.e. write is performed may be actually observed (by a read miss) only later write hit made visible (performed) when block updated in writer s cache Only one RdX can succeed at a time for a block: serialized by bus and -exclusive bus transactions drive coherence actions o Writeback transactions also, but not caused by operation and quite incidental to coherence protocol note: replaced block that is not in modified state can be dropped ngo ander - 2B1447 OC Architecture 59 ngo ander - 2B1447 OC Architecture 60 10

11 Basic M Writeback nvalidation Protocol tates o nvalid () o hared (): one or more o Dirty or Modified (M): one only Processor Events: o PrRd (read) o PrWr (write) Transactions o Rd: asks for copy with no intent to modify o RdX: asks for copy with intent to modify o WB: updates Actions o Update state, perform bus transaction, flush value onto bus ngo ander - 2B1447 OC Architecture 61 tate Transition Diagram PrWr/RdX PrRd/Rd PrWr/RdX PrRd/ M PrRd/ Rd/ PrWr/ Rd/Flush RdX/Flush RdX/ Write to shared block: o Already have latest data; can use upgrade (Upgr) instead of RdX Replacement changes state of two blocks: outgoing and incoming ngo ander - 2B1447 OC Architecture 62 ME (4-state) nvalidation Protocol Problem with M protocol o ing and modifying data is 2 bus xactions, even if noone sharing e.g. even in sequential program Rd (->) followed by RdX or Upgr (->M) ME (4-state) nvalidation Protocol Add exclusive state: write locally without transaction, but not modified o Main is up to date, so cache not necessarily owner o tates invalid exclusive or exclusive-clean (only this cache has copy, but not modified) shared (two or more caches may have copies) modified (dirty) o -> E on PrRd if noone else has copy needs shared signal on bus: wired-or line asserted in response to Rd ngo ander - 2B1447 OC Architecture 63 ngo ander - 2B1447 OC Architecture 64 ME tate Transition PrRd PrWr/ Diagram PrWr/RdX PrWr/ PrWr/RdX PrRd/ Rd () M E PrRd/ PrRd/ Rd() Rd/Flush PrRd/ Rd/Flush Rd/ Flush RdX/Flush RdX/Flush RdX/Flush Rd() means shared line asserted on Rd transaction Flush : if cache-to-cache sharing (see next), only one cache flushes data ngo ander - 2B1447 OC Architecture 65 Update-based Protocols A write operation updates values in other caches o New, update bus transaction Advantages o Other processors don t miss on next access: reduced latency n invalidation protocols, they would miss and cause more transactions o ingle bus transaction to update several caches can save bandwidth Also, only the word written is transferred, not whole block Disadvantages o Multiple writes by same processor cause multiple update transactions n invalidation, first write gets exclusive ownership, others local Detailed tradeoffs more complex ngo ander - 2B1447 OC Architecture 66 11

12 nvalidate versus Update Basic question of program behavior o s a block written by one processor read by others before it is rewritten? nvalidation: o readers will take a miss o multiple writes without additional traffic and clears out copies that won t be used again Update: o readers will not miss if they had a copy previously single bus transaction to update all copies o multiple useless updates, even to dead copies Need to look at program behavior and hardware complexity Back to the Example: Coherence Problem 1. P1 reads location u (value 5) from main 2. P3 reads location u from main 3. P3 writes u, changing the value to 7 4. P1 reads value u again 5. P2 reads location u from main ngo ander - 2B1447 OC Architecture 67 ngo ander - 2B1447 OC Architecture 68 Back to the Example: Coherence Problem Two tate Write-Through Protocol Describe what happens, if a 1. Two tate Write-Through Protocol 2. Basic M Writeback Protocol 3. ME Protocol is used? Processor Action P1 reads u P3 reads u tate in P1 tate in P2 tate in P3 Action Rd Rd Data supplied by P3 writes u Wr P1 reads u Rd P2 reads u Rd ngo ander - 2B1447 OC Architecture 69 ngo ander - 2B1447 OC Architecture 70 Basic M Writeback Protocol ME Protocol Processor Action tate in P1 tate in P2 tate in P3 Action Data supplied by Processor Action tate in P1 tate in P2 tate in P3 Action Data supplied by P1 reads u Rd P1 reads u E ( not asserted) Rd( ) P3 reads u Rd P3 reads u ( asserted) Rd() P1 P3 writes u M RdX P3 writes u M RdX P1 reads u (Flush to ) Rd P3 P1 reads u ( asserted) (Flush to ) Rd() P3 P2 reads u Rd P2 reads u Rd() Either P1 or P3 ngo ander - 2B1447 OC Architecture 71 ngo ander - 2B1447 OC Architecture 72 12

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