Fall 2012 EE 6633: Architecture of Parallel Computers Lecture 4: Shared Address Multiprocessors Acknowledgement: Dave Patterson, UC Berkeley
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1 Fall 2012 EE 6633: Architecture of Parallel Computers Lecture 4: Shared Address Multiprocessors Acknowledgement: Dave Patterson, UC Berkeley Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio Website: Outline Review Memory Hierarchy Coherence Write Consistency Snooping Building Blocks Snooping protocols and examples Coherence traffic and Performance on MP Directory-based protocols and examples Conclusion 2 1
2 3 Performanc Processor-Memory Performance Gap Moore s Law µproc 55%/year (2X/1.5yr) Processor-Memory Performance Gap (grows 50%/year) DRAM 7%/year (2X/10yrs) Year Characteristics of the Memory Hierarchy Increasing distance from the processor in access time Processor 4-8 bytes (word) L1$ 8-32 bytes (block) L2$ 1 to 4 blocks Main Memory Inclusive what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM Secondary Memory 1,024+ bytes (disk sector = page) (Relative) size of the memory at each level 4 2
3 The Memory Hierarchy: Why Does it Work? Temporal Locality (Locality in Time): Keep most recently accessed data items closer to the processor Spatial Locality (Locality in Space): Move blocks consisting of contiguous words to the upper levels To Processor From Processor Upper Level Memory Blk X Lower Level Memory Blk Y 5 The Memory Hierarchy: Terminology Hit: data is in some block in the upper level (Blk X) Hit Rate: the fraction of memory accesses found in the upper level Hit Time: Time to access the upper level which consists of RAM access time + Time to determine hit/miss To Processor From Processor Upper Level Memory Lower Level Memory Miss: data is not in the upper level so needs to be retrieve from a block in the lower level (Blk Y) Miss Rate = 1 - (Hit Rate) Miss Penalty: Time to replace a block in the upper level + Time to deliver the block the processor Blk X Blk Y Average Memory Access Time (AMAT) = Hit Time + Miss Rate x Miss Penalty 6 3
4 4 Questions for the Memory Hierarchy Q1: Where can a block be placed in the upper level? (Block placement) Q2: How is a block found if it is in the upper level? (Block identification) Q3: Which block should be replaced on a miss? (Block replacement) Q4: What happens on a write? (Write strategy) Q1: Where can a block be placed in the upper level? Block 12 placed in 8 block cache: Cache Fully associative, direct mapped, 2-way set associative S.A. Mapping = Block Number Modulo Number Sets Full Mapped Direct Mapped (12 mod 8) = 4 2-Way Assoc (12 mod 4) = Memory
5 Q1&Q2: Where can a block be placed/found? # of sets Blocks per set Direct mapped # of blocks in cache 1 Set associative (# of blocks in cache)/ associativity Associativity (typically 2 to 16) Fully associative 1 # of blocks in cache Location method # of comparisons Direct mapped Index 1 Set associative Index the set; compare set s tags Degree of associativity Fully associative Compare all blocks tags # of blocks Q3: Which block should be replaced on a miss? Easy for direct mapped only one choice Set associative or fully associative Random LRU (Least Recently Used) For a 2-way set associative cache, random replacement has a miss rate about 1.1 times higher than LRU. LRU is too costly to implement for high levels of associativity (> 4-way) since tracking the usage information is costly 5
6 Q4: What happens on a write? Write-through The information is written to both the block in the cache and to the block in the next lower level of the memory hierarchy Write-through is always combined with a write buffer so write waits to lower level memory can be eliminated (as long as the write buffer doesn t fill) Write-back The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. Need a dirty bit to keep track of whether the block is clean or dirty Pros and cons of each? Write-through: read misses don t result in writes (so are simpler and cheaper) Write-back: repeated writes require only one write to lower level Improving Cache Performance 0. Reduce the hit time in the cache smaller cache direct mapped cache smaller blocks for writes no write allocate no hit on cache, just write to write buffer write allocate to avoid two cycles (first check for hit, then write) pipeline writes via a delayed write buffer to cache 1. Reduce the miss rate bigger cache more flexible placement (increase associativity) larger blocks (16 to 64 bytes typical) victim cache small buffer holding most recently discarded blocks 6
7 Improving Cache Performance 2. Reduce the miss penalty smaller blocks use a write buffer to hold dirty blocks being replaced so don t have to wait for the write to complete before reading check write buffer (and/or victim cache) on read miss may get lucky for large blocks fetch critical word first use multiple cache levels L2 cache not tied to CPU clock rate faster backing store/improved memory bandwidth wider buses memory interleaving, page mode DRAMs Symmetric Shared-Memory Architectures From multiple boards on a shared bus to multiple processors inside a single chip Caches both Private data are used by a single processor Shared data are used by multiple processors Caching shared data reduces latency to shared data, memory bandwidth for shared data, and interconnect bandwidth cache coherence problem 14 7
8 Natural Extensions of Memory System P 1 Switch P n (Interleaved) First-level $ P 1 P n (Interleaved) Main memory $ Inter connection network $ Shared Cache Mem Mem Centralized Memory Dance Hall, UMA P 1 P n Mem $ Mem $ Inter connection network Distributed Memory (NUMA) 15 Example Cache Coherence Problem P 1 P 2 P 3 u =? u =? 3 4 $ $ 5 $ u :5 u :5 u = 7 1 u :5 2 I/O devices Memory Processors see different values for u after event 3 With write back caches, value written back to memory depends on happenstance of which cache flushes or writes back value when Processes accessing main memory may see very stale value Unacceptable for programming, and its frequent! 16 8
9 Example P 1 P 2 /*Assume initial value of A and flag is 0*/ A = 1; while (flag == 0); /*spin idly*/ flag = 1; print A; Intuition not guaranteed by coherence expect memory to respect order between accesses to different locations issued by a given process to preserve orders among accesses to same location by different processes Coherence is not enough! pertains only to single location P 1 P n Conceptual Picture Mem 17 Intuitive Memory Model Memory Disk L2 L1 P 100:67 100:35 100:34 Reading an address should return the last value written to that address Easy in uniprocessors, except for I/O Too vague and simplistic; 2 issues 1. Coherence defines values returned by a read 2. Consistency determines when a written value will be returned by a read Coherence defines behavior to same location, Consistency defines behavior to other locations 18 9
10 Defining Coherent Memory System 1. Preserve Program Order: A read by processor P to location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P 2. Coherent view of memory: Read by a processor to location X that follows a write by another processor to X returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses 3. Write serialization: 2 writes to same location by any 2 processors are seen in the same order by all processors If not, a processor could keep value 1 since saw as last write For example, if the values 1 and then 2 are written to a location, processors can never read the value of the location as 2 and then later read it as 1 19 For now assume Write Consistency 1. A write does not complete (and allow the next write to occur) until all processors have seen the effect of that write 2. The processor does not change the order of any write with respect to any other memory access if a processor writes location A followed by location B, any processor that sees the new value of B must also see the new value of A These restrictions allow the processor to reorder reads, but forces the processor to finish writes in program order 20 10
11 Basic Schemes for Enforcing Coherence Program on multiple processors will normally have copies of the same data in several caches Unlike I/O, where its rare Rather than trying to avoid sharing in SW, SMPs use a HW protocol to maintain coherent caches Migration and Replication key to performance of shared data Migration - data can be moved to a local cache and used there in a transparent fashion Reduces both latency to access shared data that is allocated remotely and bandwidth demand on the shared memory Replication for reading shared data simultaneously, since caches make a copy of data in local cache Reduces both latency of access and contention for read shared data 21 2 Classes of Cache Coherence Protocols 1. Directory based Sharing status of a block of physical memory is kept in just one location, the directory 2. Snooping Every cache with a copy of data also has a copy of sharing status of block, but no centralized state is kept All caches are accessible via some broadcast medium (a bus or switch) All cache controllers monitor or snoop on the medium to determine whether or not they have a copy of a block that is requested on a bus or switch access 22 11
12 Snoopy Cache-Coherence Protocols State Address Data P 1 $ Bus snoop P n $ Mem I/O devices Cache-memory transaction Cache Controller snoops all transactions on the shared medium (bus or switch) relevant transaction if for a block it contains take action to ensure coherence invalidate, update, or supply value depends on state of the block and the protocol Either get exclusive access before write via write invalidate or update all copies on write 23 Example: Write-thru Invalidate P 1 P 2 P 3 u =? u =? 3 4 $ $ 5 $ u :5 u :5 u = 7 1 u :5 Memory u = 7 2 I/O devices Must invalidate before step 3 Write update uses more broadcast medium BW all recent MPUs use write invalidate 24 12
13 Architectural Building Blocks Cache block state transition diagram FSM specifying how disposition of block changes invalid, valid, exclusive Broadcast Medium Transactions (e.g., bus) Fundamental system design abstraction Logically single set of wires connect several devices Protocol: arbitration, command/addr, data Every device observes every transaction Broadcast medium enforces serialization of read or write accesses Write serialization 1 st processor to get medium invalidates others copies Implies cannot complete write until it obtains bus All coherence schemes require serializing accesses to same cache block Also need to find up-to-date copy of cache block 25 Locate up-to-date copy of data Write-through: get up-to-date copy from memory Write through simpler if enough memory BW Write-back harder Most recent copy can be in a cache Can use same snooping mechanism 1. Snoop every address placed on the bus 2. If a processor has dirty copy of requested cache block, it provides it in response to a read request and aborts the memory access Complexity from retrieving cache block from cache, which can take longer than retrieving it from memory Write-back needs lower memory bandwidth Support larger numbers of faster processors Most multiprocessors use write-back 9/17/2012 CS252 s06 snooping cache MP 26 13
14 Cache Resources for WB Snooping Normal cache tags can be used for snooping Valid bit per block makes invalidation easy Read misses easy since rely on snooping Writes Need to know if know whether any other copies of the block are cached No other copies No need to place write on bus for WB Other copies Need to place invalidate on bus 27 Cache Resources for WB Snooping To track whether a cache block is shared, add extra state bit associated with each cache block, like valid bit and dirty bit Write to Shared block Need to place invalidate on bus and mark cache block as private (if an option) No further invalidations will be sent for that block This processor called owner of cache block Owner then changes state from shared to unshared (or exclusive) 28 14
15 Cache behavior in response to bus Every bus transaction must check the cache-address tags could potentially interfere with processor cache accesses A way to reduce interference is to duplicate tags One set for caches access, one set for bus accesses Another way to reduce interference is to use L2 tags Since L2 less heavily used than L1 Every entry in L1 cache must be present in the L2 cache, called the inclusion property If Snoop gets a hit in L2 cache, then it must arbitrate for the L1 cache to update the state and possibly retrieve the data, which usually requires a stall of the processor 29 Example Protocol Snooping coherence protocol is usually implemented by incorporating a finite-state controller in each node Logically, think of a separate controller associated with each cache block That is, snooping operations or cache requests for different blocks can proceed independently In implementations, a single controller allows multiple operations to distinct blocks to proceed in interleaved fashion that is, one operation may be initiated before another is completed, even through only one cache access or one bus access is allowed at time 30 15
16 Write-through Invalidate Protocol 2 states per block in each cache as in uniprocessor state of a block is a p-vector of states Hardware state bits associated with blocks that are in the cache PrRd / BusRd other blocks can be seen as being in invalid (not-present) state in that cache Writes invalidate all other cache copies can have multiple simultaneous readers of block,but write invalidates them PrRd: Processor Read PrWr: Processor Write BusRd: Bus Read BusWr: Bus Write State Tag Data P 1 Mem V I PrRd/ -- PrWr / BusWr BusWr / - PrWr / BusWr State Tag Data P n $ $ Bus I/O devices 31 Is 2-state Protocol Coherent? Processor only observes state of memory system by issuing memory operations Assume bus transactions and memory operations are atomic and a one-level cache all phases of one bus transaction complete before next one starts processor waits for memory operation to complete before issuing next with one-level cache, assume invalidations applied during bus transaction All writes go to bus + atomicity Writes serialized by order in which they appear on bus (bus order) => invalidations applied to caches in bus order How to insert reads in this order? Important since processors see writes through reads, so determines whether write serialization is satisfied But read hits may happen independently and do not appear on bus or enter directly in bus order Let s understand other ordering issues 32 16
17 Ordering P 0 : R R R W R R P 1 : R R R R R W P 2 : R R R R R R Writes establish a partial order Doesn t constrain ordering of reads, though shared-medium (bus) will order read misses too any order among reads between writes is fine, as long as in program order 33 Setup for Memory Consistency Coherence => Writes to a location become visible to all in the same order But when does a write become visible? How do we establish orders between a write and a read by different processors? use event synchronization typically use more than one location! 34 17
18 Requirements for Memory Consistency (1/3) /*Assume initial value of A and flag is 0*/ P1 P2 A = 1; While( Flag == 0 ); /* spin idly */ Flag = 1; Print A; /*Assume initial value of A and B are 0*/ P1 P2 35 A = 1; print B; B = 2; print A; Clearly, we need something more than coherence to give a shared address space a clear semantics, i.e. an ordering model that programmers can use to reason about possible results and hence the correctness of their programmers Requirements for Memory Consistency (2/3) Determines the total order such that: It gives the same result Operations by any particular process occur in the order they were issued The value returned by each read operation is the value written by the last write operation to that location in the total order Coherence Protocol defines only properties for accesses to a single location Program need in addition, guaranteed properties for accesses to multiple locations 36 18
19 Requirements for Memory Consistency (3/3) A memory consistency model for a shared address space specifies constraints on the order in which memory operations must appear to be performed (i.e. to become visible to the processors) with respect to one another. It includes operations to the same location or to different locations. Therefore, it subsumes coherence. 37 Sequential Consistency (1/3) Definition (Lamport 1979): A multiprocessor is sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor occur in this sequence in the order specified by its program Two constraints: program order and atomicity of memory operations
20 Sequential Consistency (2/3) Program Order - Memory operations of a process must appear to become visible - to itself & others - in program order Write Atomicity - Maintain a single sequential order among all operations to all memory locations P0 P1 Pn 39 Memory Sequential Consistency (3/3) /*Assume initial value of A and B are 0*/ P1 P2 A = 1; print B; B = 2; print A; Possible Outcomes (A,B): (0,0), (1,0), (1,2) (A, B) = (0, 2) NOT ALLOWED under SC SC does not ensure mutual exclusion, synchronization primitives are required 40 20
21 Example Write Back Snoopy Protocol Invalidation protocol, write-back cache Snoops every address on bus If it has a dirty copy of requested block, provides that block in response to the read request and aborts the memory access Each memory block is in one state: Clean in all caches and up-to-date in memory (Shared) OR Dirty in exactly one cache (Exclusive) OR Not in any caches Each cache block is in one state (track these): Shared : block can be read OR Exclusive : cache has only copy, its writeable, and dirty OR Invalid : block contains no data (in uniprocessor cache too) Read misses: cause all caches to snoop bus Writes to clean blocks are treated as misses 41 Write-Back State Machine - CPU State machine for CPU requests for each cache block Non-resident blocks invalid CPU Write Place Write Miss on bus Invalid CPU Read Place read miss on bus CPU Read hit Shared (read/only) Cache Block State CPU read hit CPU write hit Exclusive (read/write) CPU Write Place Write Miss on Bus CPU Write Miss (?) Write back cache block Place write miss on bus 42 21
22 Write-Back State Machine- Bus request State machine for bus requests for each cache block Invalid Write miss for this block Shared (read/only) Write miss for this block Write Back Block; (abort memory access) Exclusive (read/write) Read miss for this block Write Back Block; (abort memory access) 43 State machine for CPU requests for each cache block Block-replacement CPU Write Place Write Miss on bus Invalid CPU Read Place read miss on bus CPU read miss Write back block, Place read miss on bus CPU Read hit Shared (read/only) CPU Read miss Place read miss on bus Cache Block State CPU read hit CPU write hit Exclusive (read/write) CPU Write Place Write Miss on Bus CPU Write Miss Write back cache block Place write miss on bus 44 22
23 State machine for CPU requests for each cache block and for bus requests for each cache block Cache Block State Write-back State Machine-III Write miss for this block Write Back Block; (abort memory access) CPU read hit CPU write hit Write miss for this block Invalid CPU Read Place read miss CPU Write on bus Place Write Miss on bus Exclusive (read/write) CPU read miss Write back block, Place read miss on bus CPU Write CPU Read hit Shared (read/only) CPU Read miss Place read miss on bus Place Write Miss on Bus Read miss for this block Write Back Block; (abort memory access) CPU Write Miss Write back cache block Place write miss on bus 45 Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 P1: P1: Read A1 A1 P2: Read A1 P2: Write 20 to A1 P2: Write Write 40 to A2 Assumes A1 and A2 map to same cache block, initial cache state is invalid 46 23
24 Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read A1 A1 P2: Read A1 P2: Write 20 to A1 P2: Write Write 40 to A2 Assumes A1 and A2 map to same cache block 47 Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read A1 A1 Excl. A1 10 P2: Read A1 P2: Write 20 to A1 P2: Write Write 40 to A2 Assumes A1 and A2 map to same cache block 48 24
25 Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read A1 A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 WrBk P1 A1 10 A1 10 Shar. A1 10 RdDa P2 A1 10 A1 10 P2: Write 20 to A1 P2: Write Write 40 to A2 Assumes A1 and A2 map to same cache block 49 Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read A1 A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 WrBk P1 A1 10 A1 10 Shar. A1 10 RdDa P2 A1 10 A1 10 P2: Write 20 to A1 Inv. Excl. A1 20 WrMs P2 A1 A1 10 P2: Write Write 40 to A2 Assumes A1 and A2 map to same cache block 50 25
26 Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read A1 A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 WrBk P1 A1 10 A1 10 Shar. A1 10 RdDa P2 A1 10 A1 10 P2: Write 20 to A1 Inv. Excl. A1 20 WrMs P2 A1 A1 10 P2: Write Write 40 to A2 WrMs P2 A2 A1 10 Excl. A2 40 WrBk P2 A1 20 A1 20 Assumes A1 and A2 map to same cache block, but A1!= A2 51 MESI Write-back Invalidation Protocol States - Invalid (I) - Shared (S): one or more - Exclusive (E): one only - Dirty or Modified (M): one only Processor Events: - PrRd (read) - PrWr (write) Bus Transactions - BusRd: asks for copy with no intent to modify - BusRdX: asks for copy with intent to modify - BusWB: updates memory Actions - Update state, perform bus transaction, flush value onto bus 52 26
27 4-State MESI Protocol Invalid (I) PrRd PrWr/ Exclusive (E) M BusRd/Flush BusRdX/Flush Shared (S) PrWr/BusRdX PrWr/ Modified (M) PrWr/BusRdX E PrRd/ BusRd/ Flush BusRdX/Flush S PrRd/ BusRd (S) PrRd/ BusRd/Flush BusRdX/Flush PrRd/ BusRd(S) I 53 4-State Dragon Update-based Protocol 4 states Exclusive-Clean or (E): I and memory have it Shared-Clean (Sc): I, others and memory have it, but I am not the owner Shared-Modified (Sm): I, others and memory have it, and I am the owner Modified or Dirty (M): I and nobody else No invalid state If in cache, should be valid New processor events: PrRdMiss, PrWrMiss Introduced to specify actions when block not in cache New Bus Transaction: BusUpd Broadcasts single word written on bus to update caches 27
28 Dragon Update-based Protocol Performance of Symmetric Shared-Memory Multiprocessors Cache performance is combination of 1. Uniprocessor cache miss traffic 2. Traffic caused by communication Results in invalidations and subsequent cache misses 4 th C: coherence miss Joins Compulsory, Capacity, Conflict 56 28
29 Coherency Misses 1. True sharing misses arise from the communication of data through the cache coherence mechanism Invalidates due to 1 st write to shared block Reads by another CPU of modified block in different cache Miss would still occur if block size were 1 word 2. False sharing misses when a block is invalidated because some word in the block, other than the one being read, is written into Invalidation does not cause a new value to be communicated, but only causes an extra cache miss Block is shared, but no word in block is actually shared miss would not occur if block size were 1 word 57 Miss Rate Trade-Off Lots of coherence misses: updates help Lots of capacity misses: updates hurts (keeps useless data in cache) 29
30 Reporting Snoop Results: How? Collective response from caches must appear on bus Example: in MESI protocol, need to know - Is block dirty; i.e. should memory respond or not? - Is block shared; i.e. transition to E or S state on read miss? Three wired-or signals - Shared: asserted if any cache has a copy - Dirty: asserted if some cache has a dirty copy - needn t know which, since it will do what s necessary Snoop-valid: asserted when OK to check other two signals actually inhibit until OK to check Illinois MESI requires priority scheme for cache-to-cache transfers Which cache should supply data when in shared state? Commercial implementations allow memory to provide data Reporting Snoop Results: When? As soon as possible, memory needs to know what to do. If none of the caches has a dirty copy, memory has to fetch the data. Three options: Fixed number of clocks from address appearing on bus Dual tags required to reduce contention with processor Still must be conservative. Processor blocks access to tag memory on E -> M. Variable delay Memory assumes cache will supply data till all say sorry Less conservative, more flexible, more complex Memory can fetch data and hold just in case (SGI Challenge) Immediately: Bit-per-block in memory Main memory maintain a bit per block that indicates whether this block is modified in one of the caches. Extra hardware complexity in commodity main memory system 30
31 Multi-level Cache Hierarchies How to snoop with multi-level caches? - independent bus snooping at every level (additional hardware: snooper, pins, duplication of tags) - maintain cache inclusion Requirements for Inclusion - data in higher-level cache is subset of data in lower-level cache - modified in higher-level => marked modified in lower-level Need to snoop lowest-level cache - If L2 says not present (modified), then not so in L1 too - If BusRd seen to block that is modified in L1, L2 itself knows this Inclusion is not always automatically preserved 61 Violations in Inclusion The two caches (L1, L2) may choose to replace different block Differences in reference history - set-associative first-level cache with LRU replacement Split higher-level caches - instruction, data blocks go in different caches at L1, but may collide in L2 Differences in block size But a common case works automatically - L1 direct-mapped, fewer sets than in L2, and block size same 62 31
32 Enhancements required to Cache Protocol Explicitly maintaining inclusion property Propagate bus transactions from L2 to L1 Propagate flush and invalidations Propagate modified state from L1 to L2 on writes L2 cache must be updated before flush due to bus transaction Write-through L1, or modified-but-stale bit per block in L2 cache Dual cache tags less important: each cache is filter for other 63 Further Enhancements Split bus transaction into request and response sub-transactions Separate arbitration for each phase Other transactions may intervene Improves bandwidth dramatically Response is matched to request Buffering between bus and cache controllers Use multiple buses (address and data separately) To separate the address and data portions of the transaction 64 32
33 Bytes Per Clock Bandwidth at 83.3-MHz clock (MBps) 9/17/2012 Split Transaction Buses: Example Split-transaction Buses Separate the address and data portions of the transaction Address Bus Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Arbitration Address Request (a) Arbitration Address Request (b) Arbitration Address Request Snoop Line Snoop Response (a) Snoop Response (b) Data Bus Data Transfer (a) Data Transfer (b) Multiple Buses Every bus snoops different portions of the memory. As the equation shows one can increase the snoop bandwidth as a cost: 65 Snoop Rate = Bus Clock Number of Buses Clocks/Snoop Problems in scaling SMPs: Starfire Sun StarFire: Uses 4 address buses. For 13 or lower system boards, the maximum data capacity is limited by the crossbar. Beyond 13, it is limited by the snoop bandwidth , Memory Bandwidth Snooping capacity Data-crossbar capacity with random addresses 16, ,667 = Snoop Bandwidth 64 Data-crossbar limited Snoop Limited 5, System Boards Courtesy of Alan Charlesworth, STARFIRE: Extending the SMP Envelope, IEEE Micro, Volume 18, Issue 1,Jan-Feb 1998 Page(s) :
34 Bandwidth Scaling: Sun Interconnects 67 Other Enhancement Older machines (Starfire, SGI Powerpath-2) Sun Fireplane Architecture (tree-based MEOSI protocol) Filtering Techniques (at source and destination, QPI Interconnect) Speculative Techniques (adaptive snooping) Token Coherence Papers all posted and discussed in class 34
35 A Cache Coherent System Must: Provide set of states, state transition diagram, and actions Manage coherence protocol (0) Determine when to invoke coherence protocol (a) Find info about state of block in other caches to determine action whether need to communicate with other cached copies (b) Locate the other copies (c) Communicate with those copies (invalidate/update) (0) is done the same way on all systems state of the line is maintained in the cache protocol is invoked if an access fault occurs on the line Different approaches distinguished by (a) to (c) 69 Bus-based Coherence All of (a), (b), (c) done through broadcast on bus faulting processor sends out a search others respond to the search probe and take necessary action Could do it in scalable network too broadcast to all processors, and let them respond Conceptually simple, but broadcast doesn t scale with p on bus, bus bandwidth doesn t scale on scalable network, every fault leads to at least p network transactions Scalable coherence: can have same cache states and state transition diagram different mechanisms to manage protocol 70 35
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