Making the Most of your MATLAB Models to Improve Verification

Transcription

1 Making the Most of your MATLAB Models to Improve Verification Verification Futures 2016 Graham Reith Industry Manager: Communications, Electronics & Semiconductors 2015 The MathWorks, Inc. 1

2 Agenda Motivation: Role of MATLAB Models in Semiconductor Design Desire to shift-left verification Faster verification testbench development, directly linked to design reference Technical Topics: Building better models in MATLAB and Simulink Fixed-point, architectural Improving verification at the design stage Model coverage, test case generation Re-using models in verification environments Deployment to SystemVerilog/UVM with DPI-C export Co-simulation and FPGA-in-the-Loop Next Steps 2

3 Shifting-Left Where Errors are Introduced and Detected 60% 60% 55% 50% 40% 30% 20% 10% 0% 8% 21% Specification Design Implement Test Increased Modelling & Simulation 15% Shift-left Verification 12% 22% 7% Traditional Verification Introduced Detected Clive Maxfield and Kuhoo Goyal EDA: Where Electronics Begins 3

4 Model-Based Design RESEARCH REQUIREMENTS ALGORITHM DESIGN Environment Models Digital Models Analog Models RF Models Timing and Control Logic Algorithms ALGORITHM IMPLEMENTATION C/C++ HDL RF & Analog MCU DSP FPGA ASIC Transistor ALGORITHM TEST & VERIFICATION INTEGRATION 4

5 Model-Based Design RESEARCH WHAT am I making? Digital Models ALGORITHM IMPLEMENTATION C/C++ ALGORITHM DESIGN HOW am I making it? Environment Models Timing and Control Logic MAKE IT! Analog Models Algorithms HDL MCU DSP FPGA ASIC Am I making the right thing? REQUIREMENTS RF Models Is it going to work? Have I made it right? RF & Analog Transistor ALGORITHM TEST & VERIFICATION INTEGRATION 5

6 Model-Based Design Modelling Algorithms Ideal, Floating Point Detailed design: Fixed-Point Architectural System context Implementation: C and RTL generation RESEARCH Digital Models ALGORITHM IMPLEMENTATION C/C++ ALGORITHM DESIGN Environment Models Analog Models Timing and Control Logic Algorithms HDL MCU DSP FPGA ASIC INTEGRATION REQUIREMENTS RF Models RF & Analog Transistor ALGORITHM TEST & VERIFICATION Validation of Requirements Verification against Requirements Verification against Detailed Design 6

7 Why Model-Based Design: Achieving the Shift-Left Reduce overall development time Reduced FPGA prototype development schedule Shorter design iteration cycle by 80% Improved product quality Increase detailed modelling Decrease downstream development time 7

8 Survey of Existing Customers: Model-Based Design Benefits REQUIREMENTS DEFECT REDUCTION 70% 30% DESIGN DEFECT REDUCTION 91% 9% CODING DEFECT REDUCTION 93% 7% Medium - Very High Low - Very Low 8

9 Survey of Existing Customers: Split by Process Maturity Initial Optimizing REQUIREMENTS DEFECT REDUCTION 40% 60% REQUIREMENTS DEFECT REDUCTION 75% 25% DESIGN DEFECT REDUCTION 55% 45% DESIGN DEFECT REDUCTION 92% 8% CODING DEFECT REDUCTION 57% 43% CODING DEFECT REDUCTION 100% 0% Medium - Very High Low - Very Low Medium - Very High Low - Very Low 9

10 How to use MATLAB as a Golden Reference Different model fidelities: Floating point Bit accurate, no latency Bit accurate, with latency Bit accurate, latency and controls Tools to improve quality of test framework Export to C/C++, DPI-C or SystemC Co-simulation with HDL, FPGA, UVM, etc. Bus I/F Algorithm Test Framework MATLAB Floating-point Algorithm model Configurable Simulink Floating/Fixed-point Floating-point Algorithm model Reference Model Simulink Fixed-point Algorithm model Simulink Fixed-point HW Architecture model Bus I/F Ideal, Floating point Bit & Cycle Accurate, Architectural 10

11 Algorithm Verification at the Model Level Data Source Component Model Environment Model Analysis Component Model Algorithmic System-level Testbench Simulink Verification & Validation Coverage results for tests that have been simulated Interfaces to Requirements Management systems Simulink Design Verifier Generation of tests to deliver coverage Identification of unreachable code Formal proof methods against objectives Example 11

12 Example Summary 12

13 Example Summary - Coverage 13

14 Example Summary Test Case Generation 14

15 Verification Environment Creation System and algorithm verified in MATLAB or Simulink Algorithmic models Full system environment Realistic stimulus Algorithmic system-level environment Data Source Algorithm Analysis Specification written, passed to verification Specification Verification interprets spec to recreate: Scoreboard Checker model Models external to DUT Stimulus Driver Design Under Test (DUT) Monitor Why recreate when we can reuse? SystemVerilog environment 15

16 HDL Verifier Automatically generate SystemVerilog DPI-C models Reuse MATLAB/Simulink models in verification Available immediately Already verified Easy to update Algorithmic system-level environment MATLAB or Simulink Data Source Algorithm Analysis Everything is automated Generates code and SystemVerilog interface Generates and runs makefile to build shared library DPI DPI DPI Anywhere C code can be generated Digital and analog Broad block and language support C C C SystemVerilog environment Cadence, Mentor, Synopsys 16

17 Demo Overview fft_sequence_wave Waveform? fft_sequencer fft_st_driver SystemVerilog UVM environment AXI S fft_scoreboard Checker? FFT DUT Verilog AXI S Coverage fft_st_monitor Checker: Calculate floating point FFT Calculate difference vs. DUT normalized rms error = rms(error) rms(result) Compare vs. theoretical upper bound Waveform: What would it take to write these in SystemVerilog? 17

18 Demo Summary 18

19 Demo Summary Generated Files 19

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21 Demo Results fft_sequence_wave DPI_gen_wave fft_sequencer SystemVerilog UVM environment fft_scoreboard DPI_fft_checker Checker: 5 lines of MATLAB Generated with a single command Easily adjusted fft_st_driver AXI S FFT DUT AXI S Coverage fft_st_monitor Verilog Waveform: 10-line MATLAB function Generated with a single command Easily adjusted or replicated How much work does this save? 21

22 HDL Verifier DPI-C Component Generation Reuse MATLAB and Simulink models for verification Algorithmic system-level environment Models available earlier Data Source Algorithm Analysis Accurately capture algorithm behavior Establish connection to original source Scoreboard Easy to update DPI-C DPI-C Applicable to broad class of models Driver Design Under Test (DUT) Monitor SystemVerilog environment 22

23 Algorithm Reusing MATLAB as a Verification Environment Co-simulation for Verification of HDL Source Code Data Source Component Model Environment Model Co-simulation with 3 rd -party HDL simulator Reuse of existing testbench in MATLAB/Simulink Analysis == Co-Sim Algorithmic System-level Testbench Component Model HDL code execution in 3 rd -party HDL simulator Flexible HDL sources Handwritten or generated code RTL HDL (VHDL, Verilog) cosimwizard (HDL Verifier), HDL Workflow Advisor (HDL Coder) HDL Verifier Automated generation of co-simulation infrastructure Automatic handshaking Combined analysis and debugging in both simulators 3 rd -party HDL Simulator 23

24 Algorithm Reusing MATLAB as a Verification Environment FPGA-in-the-Loop Verification of HDL Source Code Data Source Component Model Environment Model FIL simulation with FPGA development board Reuse of existing testbench in MATLAB/Simulink Analysis == FIL Algorithmic System-level Testbench Component Model filwizard (HDL Verifier), HDL Workflow Advisor (HDL Coder) HDL Verifier HDL code execution on FPGA Flexible HDL sources Handwritten or generated code Automated generation of co-simulation infrastructure Encapsulation of algorithm within GBit Ethernet MAC, or via JTAG Automatic handshaking 24

25 Summary Motivation: Role of MATLAB Models in Semiconductor Design Desire to shift-left verification Faster verification testbench development, directly linked to design reference Technical Topics: Building better models in MATLAB and Simulink Fixed-point, architectural Improving verification at the design stage Model coverage, test case generation Re-using models in verification environments Deployment to SystemVerilog/UVM with DPI-C export Co-simulation and FPGA-in-the-Loop Next Steps 25

26 Next Steps Verification Focus: Establish whether you can re-use existing MATLAB models in your verification testbench Save effort Close the loop on the development process Overall Design Flow Focus: Consider how you can achieve a shift-left in verification How can modelling fidelity be improved ahead of implementation Improved Models Improved Testbenches For more information, references, and discussion on this topic Visit Contact Graham.Reith@mathworks.co.uk 26