SEQUENTIAL STATEMENTS

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1 SEQUENTIAL STATEMENTS

2 Sequential Statements Allow to describe the behavior of a circuit as a sequence of related events Can be used to model, simulate and synthesize: Combinational logic circuits Sequential logic circuits They are used inside of: Processes Functions Procedures The order or sequence of sequential statements is very important 2

3 process A process is a concurrent statement, but it is the primary mode of introducing sequential statements A process, with all the sequential statements, is a simple concurrent statement. That is, a process is executed in just one delta time From the traditional programming view, it is an infinite loop Multiple processes can be executed in parallel 3

4 Anatomy of a process A process has two states: execution and wait execution Until a condition is satisfied wait Once the process has been executed, it will wait for the next satisfied condition 4

5 process - Syntax process sensitivity_list declarations; sequential_statements; end process; process declarations; sequential_statements; wait on sensitivity_list; end process; 5

6 process Syntax [process_label:] process [(sensitivity_list)] [is] [process_data_object_declarations] variable_assignment_statement signal_assignment_statement wait_statement if_statement case_statement loop_statement null_statement exit_statement next_statement assertion_statement report_statement procedure_call_statement return_statement end process [process_label]; Sequential statements 6

7 sensitivity_list process List of all the signals that are able to triger the process Similation tools monitor events on these signals Any event on any signal in the sensitivity list will cause to execute the process at least once declarations Declarative part. Types, functions, procedures and variables can be declared in this part Each declaration is local to the process sequential_statements All the sequential statements that will be executed each time that the process is activated 7

8 Signal Behavior - process While a process is running ALL the SIGNALS in the system remain unchanged -> Signals are affectively CONSTANTS during process execution, EVEN after a signal assignment, will NOT take a new value SIGNALS are updated at the end of a process 8

9 Variable Behavior - process While a process is running ALL the Variables in the system are updates IMMEDIATELY by a variable assignment statement 9

10 Clocked process Clocked processes lead to all the signals assigned inside the process resulting in a flip-flop Variables can also give rise a flip-flop in a clocked process. If a variable is read before it is assigned a value, it will result in a flip-flop for the variable (bad practice) If a signal is not assigned a value in a clocked process, the signal will retain the old value (flip-flop with a mux) A clocked process can result in combinational logic as well as flip-flops. All logic caused by a signal assignment in a clocked process will end up on the left of the flipflop (before the flip-flop s input) 10

11 Clocked process entity ff_example is port( d : in std_logic; clk : in std_logic; q : out std_logic); end entity; architecture rtl of ff_example is ff_d: process (clk) if (rising_edge(clk)) then q <= d; end if; end process ff_d; end rtl; 11

12 Clocked process entity ff_example is port( d, clk, rst: in std_logic; q: out std_logic); end entity; architecture rtl of ff_example is ff_d_srst: process (clk) if (rising_edge(clk)) then if (rst= 1 ) then q <= 0 ; else q <= d; end if; end if; end process ff_d_srst; end rtl; 12

13 Clocked process entity ff_example is port( d, clk, rst: in std_logic; q: out std_logic); end entity; architecture rtl of ff_example is ff_d_arst: process (clk, rst) if (rst= 1 ) then q <= 0 ; else if (rising_edge (clk)) then q <= d; end if; end process ff_d_arst; end rtl; 13

14 Clocked process architecture rtl of example is signal q: std_logic; FD1_B1: process (clk, rst) if (rst='1') then q <= '0'; elsif (clk'event and clk='1') then if (en='1') then q <= ;-- some boolean expression(b1) end if; end if; end process; q1 <= q and some boolean expression(b2) end rtl; 14

15 Clocked process - Counter library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter_ud is generic(cnt_w: natural:= 4) port ( -- clock & reset inputs clk : in std_logic; rst : in std_logic; -- control input signals up_dw : in std_logic; -- ouptuts count : out std_logic_vector(cnt_w-1 downto 0)); end counter_ud; 15

16 Clocked process - Counter architecture rtl of counter_ud is -- signal declarations signal count_i: unsigned(cnt_w-1 downto 0); count_proc: process(clk, rst) if(rst='0') then count_i <= (others => '0'); elsif(rising_edge(clk)) then if(up_dw = '1') then -- up count_i <= count_i + 1; else -- down count_i <= count_i - 1; end if; end if; end process count_proc; count <= std_logic_vector(count_i); end architecture rtl; 16

17 Combinational process In a combinational process all the input signals must be contained in the sensitivity list If a signal is omitted from the sensitivity list, the VHDL simulation and the synthesized hardware will behave differently All the output signals from the process must be assigned a value each time the process is executed. If this condition is not satisfied, the signal will retain its value (latch!) 17

18 Combinational process a_process: process (a_in, b_in) c_out <= not(a_in and b_in); d_out <= not b_in; end process a_process; b_process: process (c_in, d_in) e_out <= not(d_in and c_in); f_out <= not c_in; end process a_process; 18

19 Combinational process entity exampe3 is port ( a, b, c: in bit; z, y: out bit); end example3; architecture beh of example3 is process (a, b, c) if c='1' then z <= a; else y <= b; end if; end process; end beh; 19

20 Combinational vs Clocked process.... architecture rtl of com_ex is ex_c: process (a,b) z <= a and b; end process ex_c; end rtl;.... architecture rtl of reg_ex is ex_r: process (clk) if (rising_edge(clk)) then z <= a and b; end if; end process ex_r; end rtl; 20

21 Combinational vs Clocked process Sinthesis??? 21

22 Signal - process Signals are the interface between VHDL s concurrent domain and the sequential domain within a process Signals are a mean of communication between processes -> VHDL can be seen as a network of processes intercommunicating via signals 22

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