SIS Logic Synthesis System
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1 SIS Logic Synthesis System Luigi Di Guglielmo Davide Bresolin Tiziano Villa University of Verona Dep. Computer Science Italy
2 Introduc>on Logic Synthesis performs the transla>on from a high level descrip>on (e.g., VHDL) to a RTL descrip>on and op>mizes the lager It may be driven by different cost func>ons Area Delay, clock speed etc. It leads to implementa>ons mee>ng the desired objec>ves 2
3 SIS Logic Synthesis System (I) SIS is an interac>ve tool for synthesis and op>miza>on of sequen>al circuits developed by the CAD group of U.C. Berkeley in the 1990s It produces an op>mized net- list preserving the sequen>al input/output behavior It incorporates a set of logic op>miza>on algorithms users can choose among a variety of techniques at each stage of the synthesis process 3
4 SIS Logic Synthesis System (II) Different algorithms for various stages of sequen>al synthesis: State minimiza>on State assignment Node simplifica>on Kernel and cube extrac>on Technology mapping Re>ming 4
5 How to use SIS Design specifica>on Rewrite in different formats / Read sta>s>cs read Technology independent op>miza>on Technology mapping Gate- level op>miza>on Formats: 1. pla 2. blif 3. kiss 4. eqn 1. FSM op>miza>on 2. FSM to logic and reverse 3. Combina>onal op>miza>on 4. Sequen>al (gate- level) op>miza>on Target library 1. Re>ming 5
6 Design Specifica>on A sequen>al circuit can be input to SIS in several ways allowing SIS to be used at various stages of the design process The most common entry points are Net- list of gates Truth table in PLA (espresso) format Set of equa>ons Finite- state machine in state- transi>on- table form 6
7 Logic Implementa>on (Net- list) The net- list descrip>on is given in extended BLIF (Berkeley Logic Interchange Format) It consists of interconnected single- output combina>onal gates and latches Gates are simple elements that perform logical opera>ons Latches store the state 7
8 The SIS Synthesis and Op>miza>on System Read the specifica>ons $> sis UC Berkeley, SIS (compiled :35:42) sis> sis> help returns a list of all the commands provided by SIS sis> read_pla <file_name> Loads a pla descrip>on sis> read_blif <file_name> Loads a net- list descrip>on sis> read_eqn <file_name> Loads an equa>on- based descrip>on sis> read_kiss <file_name> Loads a kiss- style STG descrip>on 8
9 The SIS Synthesis and Op>miza>on System Write the specifica>ons sis> write_pla [file_name] Writes a PLA descrip>on sis> write_blif [file_name] Writes a net- list descrip>on sis> write_eqn [file_name] Writes an equa>on- based descrip>on sis> write_kiss [file_name] Writes a kiss- style STG descrip>on 9
10 Example 1: the full- adder # full-adder circuit.i 3.o 2.ilb x y z.ob C S end Create a.pla file with the descrip>on Open the file in SIS Try the following commands: print print_stats print_io 06/11/13 Software for Embedded Systems 10
11 The SIS Synthesis and Op>miza>on System Node simplifica>on (II) In SIS, the user may invoke the ESPRESSO program to perform node simplifica>on sis> full_simplify the input is a net- list (blif or PLA format) returns a minimized net- list (blif format) SIS decomposes mul>ple output func>ons into single output func>ons and represents them separately 11
12 The SIS Synthesis and Op>miza>on System Node Restructuring A logical network can be modified by Crea>ng new nodes Dele>ng nodes Crea>ng new connec>ons Dele>ng connec>ons A par>cular case of node restructuring is node crea>on by extrac>ng a factor from one or more nodes 12
13 The SIS Synthesis and Op>miza>on System Kernel (I) The extrac>on of new nodes that are factors of exis>ng nodes is a form of division that may be performed in the Boolean or algebraic domain Algebraic techniques: sum- of- products are treated as standard polynomials look for expressions that are observed many >mes in the nodes of the network and extract such common expressions The extracted expression is implemented only once and the output of that node replaces the expression in any other node Current algebraic techniques used in SIS are based on cube- free divisors called kernels 13
14 The SIS Synthesis and Op>miza>on System Kernel (II) An expression f is cube- free if no cubes divides the expression evenly ab + c is cube free ab+ac or abc are not cube free The primary divisors of an expression are obtained by dividing the expression by cubes The kernels of an expression are the cube- free primary divisors of the expression 14
15 The SIS Synthesis and Op>miza>on System Kernel (III) adf+aef+bdf+bef+cdf+cef+g = (a+b+c)(d+e)f+g Kernel Cokernel a+b+c df, ef d+e af, bf, cf (a+b+c)(d+e) f (a+b+c)(d+e)f+g 1 15
16 The SIS Synthesis and Op>miza>on System Kernel (IV) In SIS, the user may invoke the command fast_extract, i.e., fx, to perform kerneling sis> fx the input is a net- list extracts common expressions among the nodes and rewrites the nodes of the network in terms of common expressions 16
17 The SIS Synthesis and Op>miza>on System Technology mapping (I) A tree- covering algorithm is used to map arbitrary complex logic gates into cells available in a technology library Technology mapping consists of two phases: Decomposing the logic to be mapped into a network of 2- input NAND gates and inverters Covering the network by pagerns that represent the possible cells in the library During the covering stage the area or the delay of the circuit is used as an op>miza>on criterion 17
18 The SIS Synthesis and Op>miza>on System Technology mapping (II) In SIS, the user may invoke the command rlib and map to select a library for the technology mapping and perform the mapping, respec>vely sis> rlib <library_name> sis> map the input is a net- list (blif format) map complex logic gates into cells of the chosen technology library (genlib format) 18
19 Mapping the full adder Load the minimal.genlib library Map the full- adder to the library Try the following commands: print print_gate print_map_stats 06/11/13 Software for Embedded Systems 19
20 Example 2: the >cket machine Print a >cket aner 1.50 euros are deposited Single slot for 1 euro and 50 cents coins No change E C Coin counter P 06/11/13 Software for Embedded Systems 20
21 State Transi>on Graph (STG) (I) A state transi>on table for a finite- state machine is specified using the KISS format It is used in state assignment and state minimiza>on programs STG States are symbolic The transi>on table indicates the next symbolic state and output bit- vector given a current state and an input bit- vector Don t care condi>ons are indicated by a missing transi>on or by a - in an output bit A present- state/input combina>on has no explicit next- state/output, or For a present- state/input combina>on a - output stands for either 0 or 1 21
22 State Transi>on Graph (STG) (II).start_kiss.i 2.o 1.r q0 00 q0 q q0 q q0 q q1 q q1 q q1 q q2 q q2 q q2 q q3 q q3 q q3 q0 1.end_kiss.end 00/0 q3 10/0 10/1 01/1 00/0 q1 10/0 00/0 q0 01/1 01/0 q2 00/0 10/1 01/1 22
23 The SIS Synthesis and Op>miza>on System State minimiza>on (I) State minimiza>on works on STGs Degrees of freedom (i.e., unspecified transi>ons or explicit output don t cares) can be exploited to produce a machine with fewer states State minimiza>on looks for equivalent states in order to minimize the total number of states Two states are equivalent if they produce the same output sequences given the same input sequences 23
24 The SIS Synthesis and Op>miza>on System State minimiza>on (II) In SIS, the user may invoke the STAMINA program to perform state minimiza>on STAMINA is a state minimizer for incompletely specified machine sis> state_minimize stamina the input is a STG (kiss format) the original STG is replaced by the one computed by STAMINA with (possibly) fewer states 24
25 Minimize the Ticket counter FSM Create a.kiss2 file with the descrip>on of the FSM Open the file in SIS Minimize the FSM Compare the minimized machine with the original one use write_kiss to print the minimized FSM 06/11/13 Software for Embedded Systems 25
26 The SIS Synthesis and Op>miza>on System State assignment (I) State assignment provides the mapping from a STG to a net- list State assignment requires a state transi>on table and computes binary codes for each symbolic state Binary codes are used to create a logic level implementa>on subs>tu>ng the binary codes for the symbolic states, it creates a latch for each bit of the binary code 26
27 The SIS Synthesis and Op>miza>on System State assignment (II) In SIS, the user may invoke either JEDI or NOVA programs to perform state assignments sis> state_assign nova or sis> state_assign jedi the input is a STG (kiss format) returns a state assignment of the STG and a corresponding logic implementa>on (net- list) (blif format) 27
28 State- assign the Ticket counter FSM Do the state assignment of the minimized FSM Use print, print_stats, and print_latch to obtain informa>on Simulate the FSM Use simulate input1 input2 to give inputs print_state gives the current state of the FSM Compare the results of jedi and nova 06/11/13 Software for Embedded Systems 28
29 Mapping the >cket counter Load the lib2.genlib and the lib2_latch.genlib libraries Use rlib a to load the second library! Map the >cket counter FSM Try the following commands: print_stats print_gate print_map_stats 06/11/13 Software for Embedded Systems 29
30 The SIS Synthesis and Op>miza>on System Re>ming (I) Re>ming is an algorithm that moves registers across logic gates to minimize Cycle >me, or Number of registers, or Number of registers subject to a cycle- >me constraint It operates on synchronous edge- triggered designs The sequen>al I/O behavior of the circuit is maintained 30
31 The SIS Synthesis and Op>miza>on System Re>ming (II) In SIS, the user may invoke the command resme to perform the re>ming of the circuit sis> resme the input is a net- list (blif format) Add more latches, or re- posi>on the latches, to reduce the clock period Generally used to reduce the cycle >me of the circuit by adding latches 31
32 Re>ming the >cket counter Use the command resme to op>mize the circuit Try the following commands: print_stats print_gate print_map_stats Simulate the new circuit 06/11/13 Software for Embedded Systems 32
33 Synthesis and op>miza>ons SIS provides scripts for performing logic network op>miza>ons The standard script The standard script.rugged The standard script.delay Such scripts derive from the experience of SIS developers 33
34 References U.C. Berkeley More SIS infos are available at hgp://embedded.eecs.berkeley.edu/pubs/ downloads/sis/index.htm Documenta>on Examples 34
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