Model Based Design: develpment of Electronic Systems

Transcription

1 Model Based Desig: develpmet of Electroic Systems Stuttgart 16 Jue 2004 Ageda Model Based Desig: purposes ad process Model Based Desig: vehicle developmet process Tools Fuctioal Requiremets: Structure Lik to simulatio models M.A.R.S.: a method to model ad simulate Test Patter: developmet ad utilizatio Rapid Prototypig: purposes ad process Rapid Prototypig: V.C.S. Project 2 Software Egieerig

2 Model Based Desig: purposes ad process (1) To validate Fuctioal Requiremets of the followig Electrical ad Electroic Systems: Body Electroics Ifotaimet Driver Assistace Itegratio of PowerTrai strategies Itegratio of Chassis strategies To aalyze the logics ad strategies behavior i typical ad worst case coditios To aalyze ad / or desig the diagostic ad recovery strategies To develop ew algorithms. To verify the itegratio of differet fuctios To supply executable models to ot-techical Fiat Auto departmets (i.e. Marketig), i order to evaluate the behavior of the fuctioality. 3 Software Egieerig Model Based Desig: purposes ad process (2) Textual Specificatio MS Word MS Excel Simulatio Model Simulik Matlab Test Patter: Developmet Ad Utilizatio DOORS Stateflow Textual Specificatio Validated Executable Model 4 Software Egieerig

3 Model Based Desig: Developmet Process EE Platform defiitio Ptp1 Ptp2 Ptp3 S.O.P. Developmet Process Time Project Defiitio (Cocept) Project Developmet Modelig & Simulatio (1) Defiitio ad Aalysis of Strategies ad Algorithms (2) Developmet of ew fuctioality (3) Aalysis of fuctioality of previous projects (1) Fuctioal Itegratio (2) Aalysis of the relatioship betwee the fuctios (1) Problem aalysis (2) Chage Request aalysis (3) Fedback to Fuctioal Requiremets (4) Test Patter Developmet ad Utilizatio MAIN GOAL: TO VALIDATE THE FUNCTIONAL REQUIREMENT BEFORE USING THEM IN THE PROJECT DEVELOPMENT 5 Software Egieerig Tools Database DOORS Simulatio Models: MATLAB SIMULINK STATEFLOW Graphic Iterfaces: ALTIA DESIGN ALTIA DEEPSCREEN Chage Maagemet: ECPS (SYNERGY) Automatic Software Geeratio: REAL TIME WORKSHOP R.T.W. Embedded Rapid Prototypig: dspace xpctarget 6 Software Egieerig

4 Fuctioal Requiremets Orgaizatio Fuctio AREA Comfort & Coveiece Exteral Sigalig Ad Lightig. Ifotaimet. Fuctio GROUP Electric Su Roof Power Mirrors Power Widows Hor Exteral Lights. Rear Fog Light Mai Lights Tur Lights Fuctio.. 7 Software Egieerig Fuctioal Requiremets: A example 8 Software Egieerig

5 Fuctioal Requiremet: Lik to Simulatio Models Fuctio AREA Fuctio GROUP Fuctio 9 Software Egieerig M.A.R.S.: Modelig Automotive Requiremets Specificatio Mai Purposes: To defie the validatig process flow To defie a commo approach to model, simulate ad validate the fuctioal requiremets. To defie the set of tools used i the validatig process To defie which type of iformatio is possible to exchage with the Supplier Mai Topics: Structure of the simulatio model Basic blocks Stylig rules Lik to Fuctioal Requiremets Fuctioal itegratio Fuctioal partitioig 10 Software Egieerig

6 Test Patter: Develpmet & Utilizatio The mai purposes are: To verify ad validate the logics / strategies modeled, at system (VFA) ad sub-system (VFG) level. To verify the logics / strategies modeled from user poit view To discover all workig coditios of the logics / strategies. To defies the relatioship betwee the logics / strategies with the eviromet (fault ijectio). To automate the applicatio of the Test Patters ad the aalysis of the results. 11 Software Egieerig Test Patter: Process Flow Fuctioal Requiremet Aalysis Aalysis Iput Simulatio Model Simulik Matlab Stateflow The automatic activities are: Test Patter Applicatio Output Compariso Report Geeratio (from output compariso) Test Patter Calculated Output Predicted Output Output Compariso (Post-processig Routie) Not OK Problem Aalysis OK Model Validated 12 Software Egieerig

7 Rapid Prototypig Goals To verify / validate the fuctioal logics / strategies modelled ad simulated i a real eviromet (bech or vehicle). To verify the fuctioal partitioig ad itegratio To validate the etworks o vehicle. To evaluate fuctioal logics preset oly i a real eviromet ad ot simulated o computer (i.e. deboucig, etwork maagemet, output maagemet, recovery logics, etc.) Not to geerate software for productio 13 Software Egieerig Rapid Prototypig: Process Textual Specificatio Test Patter Simulatio Model Developmet Ad Matlab Utilizatio Rapid Prototypig Eviromet ECU1 ECU2 ECU3 MS Word MS Excel Simulik CAN DOORS Stateflow Fuctioal Requiremets Completely Validated Textual Specificatio Validated Executable Model + Validatio o real prototype 14 Software Egieerig

8 Virtual Compoet Simulator (VCS) I Out dspace NBC B-CAN - dspace autobox - CAN TX / RX - Fuctioal Logics NPG dspace NPP Nxx - No Fuctioal Logics - I/O maagemet I Out I Out Nxx - Fuctioal Logics - I/O maagemet NVB I Out NBC: Body Computer Module NPG: Driver Door Module NPP: Passeger Door Module NVB: Truk Module 15 Software Egieerig Thak You! Fiat Auto P&PE ACEE E&SI - Software Egieerig Corso Settembrii, TORINO edoardo.sivera@fiat.com