FUSION PROCESSORS AND HPC
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1 FUSION PROCESSORS AND HPC Chuck Moore AMD Corporate Fellow & Technology Group CTO June 14, 2011
2 Fusion Processors and HPC Today: Multi-socket x86 CMPs + optional dgpu + high BW memory Fusion APUs (SPFP) + optional dgpu (DPFP) + high BW memory Highest performance/watt in the industry Soon: Full ECC on all external memory and large internal arrays FSA and OpenCL programming model CPUs and GPU SIMDs Ongoing increased performance and memory BW Performance Agility Gentle Slope: Start w/ Applications on x86 -- Move sections to GPU as needed Dynamic power sloshing Power allocation automatically moves to most active execution unit types Future: Fusion APUs with very high performance SPFP & DPFP 2
3 Single-thread Performance Throughput Performance Targeted Application Performance Three Eras of Processor Performance Single-Core Era Enabled by: Moore s Law Voltage Scaling MicroArchitecture Constrained by: Power Complexity Multi-Core Era Enabled by: Moore s Law Desire for Throughput 20 years of SMP arch Constrained by: Power Parallel SW availability Scalability Heterogeneous Systems Era Enabled by: Moore s Law Abundant data parallelism Power efficient GPUs Currently constrained by: Programming models Communication overheads o we are here? o we are here o we are here Time Time (# of Processors) Time (Data-parallel exploitation) 3
4 The Fusion System Architecture (FSA) 4
5 Challenge: Nested Data Parallelism Fine-grain data parallel Code Nested data parallel Code Coarse-grain data parallel Code Loop 1M times for 1M pieces of data i=0 i++ load x(i) fmul store cmp i ( ) bc i=0 i++ load x(i) fmul store cmp i (16) bc Loop 16 times for 16 pieces of data Maps very well to integrated SIMD dataflow (SSE/AVX) Lots of conditional data parallelism Benefits from closer coupling (CPU & GPU) 2D array representing very large dataset Maps very well to discrete GPU type data parallel engines i,j=0 i++ j++ load x(i,j) fmul store cmp j (100000) bc cmp i (100000) bc 5
6 Commercial HPC Opportunities of the Future Healthcare A clear national crisis and priority for next decade Analytic imaging and diagnosis (in each Doctors office!) Personalized medicine Cost effectiveness through massive commodity computing Education Another national crisis and priority for next decade New methods and tools will rely heavily on visualization, advanced modeling, interactive simulations, etc Understanding how to leverage computing technology likely to become a basic skill for success Accelerating the process of innovation Leverage computing for scientific/technical advancements Big Data and Stream Analytics for new business opportunities Green IT Drive system-level power/thermal/resource management tech 6
7 AMD and Exascale-class Computing DARPA Study (2008) identified four major challenges Energy and Power (20MW) Memory and Storage Concurrency and Locality Resiliency Available At: /TR pdf Compute Node 20pJ/FLOP 50 GFLOP/W 10 TFLOP/200W 1EFLOP/20MW Today, ~200pJ/FLOP (DPFP) 10X efficiency improvement required 100 PB/s local memory BW (1 TB/s/node * 100K nodes) Programming Model Hybrid: FSA on Heterogeneous Node + MPI Follow-op Optimized messaging (PGAS-type memory model) System Design Low latency, high BW node interconnect 7
8 PROGRAMMING AT SCALE (100K NODES) Different hardware technologies present different characteristics in the full system design NUMA Latency, BW, coherency support Networking Tiers Variable communication, synch, data movement costs Reliability Some of these can be flattened out with brute force increased cost Not always practical or desirable to do so The balance of these differences are presented to SW Glass half empty: Programmability, performance or both suffer Glass half full: Fast time-to-functionality; then, gradual optimization opportunity as needed Abstractions that present these realities in simple ways are needed: Locality Optimized Communications: PGAS extended addressing RAS support and non-disruptive check pointing Resource and systems scale (system hypervisor) 8
9 COMMONALITIES BETWEEN MEGA-DATACENTERS AND SUPERCOMPUTERS? Attribute Mega-Datacenter Supercomputer Commonality? Scale 10K 100K nodes 10K 100K nodes Maybe Workload diversity Top optimization priorities Moderate, but almost all integer processing 1. TCO (CapEx and OpEx) 2. Throughput/W/$$ Moderate, but almost all floating point processing 1. Sustained FLOPs 2. TCO Node-level power 10 s of Watts 100 s of Watts No Yes -- TCO No -- Power Density Memory BW & Cap High Very High Yes Interconnect BW Working towards 100GbE Working towards 1 Tbps Maybe Interconnect Topology Programming model Power Provisioning Cooling Dealing w/ Failures 9 Embrace Tiers w/ natural parallelism boundaries Exploit natural parallelism to build fast response time Map/Reduce, Hadoop Close proximity to cheap power Sophisticated heat flow engineering Fail-in-place; self recovering algorithms Desire as Flat as possible MPI, OpenMP, OpenCL. DirectCompute Close proximity to electric power generation facilities Sophisticated heat flow engineering Working towards extensive checkpointing No -- Costs Maybe Yes Yes Maybe
10 Questions? 10
11 DISCLAIMER & ATTRIBUTION The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. There is no obligation to update or otherwise correct or revise this information. However, we reserve the right to revise this information and to make changes from time to time to the content hereof without obligation to notify any person of such revisions or changes. NO REPRESENTATIONS OR WARRANTIES ARE MADE WITH RESPECT TO THE CONTENTS HEREOF AND NO RESPONSIBILITY IS ASSUMED FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. ALL IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE ARE EXPRESSLY DISCLAIMED. IN NO EVENT WILL ANY LIABILITY TO ANY PERSON BE INCURRED FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. AMD, the AMD arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. All other names used in this presentation are for informational purposes only and may be trademarks of their respective owners Advanced Micro Devices, Inc. 11
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