How to explicitly defines MoCCs within a model

Transcription

1 How to explicitly defines MoCCs within a model AOSTE sophia I3S/UNS/INRIA Synchron

2 the RT-Simex project (or a mean to check an implementation against its specification ) AOSTE sophia I3S/UNS/INRIA Frederic Thomas, Étienne Juliot Obeo Jean-Philippe Babau UBO and more... Synchron

3 Logical work: How to explicitly defines MoCCs within a model AOSTE sophia I3S/UNS/INRIA Synchron

4 Logical Time... focuses on causal relations between events Is independent of the abstraction level Is multi-clock (polychronous) Provides a partial order between events After 23 starts of the computer, a disk check is done The computation duration is 156 processor ticks 4

5 Logical Time... focuses on causal relations between events Is independent of the abstraction level Is multi-clock (polychronous) Provides a partial order between events After 23 starts of the computer, a disk check is done The computation duration is 156 processor ticks In modern laptop, tick is logical since the processor speed depend on the battery level 5

6 Logical Time... focuses on causal relations between events Is independent of the abstraction level Is multi-clock (polychronous) Provides a partial order between events LOGICAL TIME Friedemann Mattern Darmstadt University of Technology 6

7 Physical Time... Can be seen as a special case of logical time After 5 secondes, it stops... After 5 events of the second clock, it stops 7

8 Modeling: an example Structure Behavior Platform-Based Software Design Flow for Heterogeneous MPSoC K. POPOVICI, X. GUERIN, F. ROUSSEAU, P. S. PAOLUCCI, A. JERRAYA ACM Transactions on Embedded Computing Systems, Vol. 7, No. 4, Article 39, Publication date : July

9 Modeling: an example Structure Elaboration phase (SystemC) Behavior Simulation Platform-Based Software Design Flow for Heterogeneous MPSoC K. POPOVICI, X. GUERIN, F. ROUSSEAU, P. S. PAOLUCCI, A. JERRAYA ACM Transactions on Embedded Computing Systems, Vol. 7, No. 4, Article 39, Publication date : July

10 Traditional modelling approach Structure Black-box + Interfaces (Ports, Data Types) Behavioral abstraction Messages + possibly period and performance requirements,... What we find missing: Detailed definition of timing and synchronization properties Communication protocol requirements This missing information is often deported elsewhere 10 10

11 Time & Semantics physical time Extra functional Single time (total order) Timing constraints to be satisfied at execution Simulation semantics possibly different from synthesis UML, SystemC HDLs 11 11

12 Time & Semantics Logical functional time physical time Functional: sequence of reaction steps Multiple times (local / global) Synchronization primitives constraints between local activation times Synthesis / Compilation Extra functional Single time (total order) Timing constraints to be satisfied at execution Simulation semantics possibly different from synthesis Process networks (SDF), synchronous reactive formalisms, statecharts UML, SystemC HDLs 12 12

13 Time as semantics physical time Logical functional time Extra functional Functional: sequence of reaction steps Multiple times (local / global) Synchronization primitives constraints between local activation times Synthesis / Compilation Single time (total order) Timing constraints to be satisfied at execution Our choice Simulation semantics possibly different from synthesis UML, SystemC Process networks (SDF), synchronous reactive formalisms, statecharts HDLs 13 13

14 Logical Time (in MARTE TIME MODEL) The main concept is the Clock. It is a way to specify a, possibly infinite, ordered set of instants It can be logical or chronometric, discrete or dense Its type is a ClockType itsresolution = 1 = TAI = discrete tick 14 14

15 MARTE TIME MODEL 1..* itsresolution = 1 = TAI Simplified view of the MARTE Time meta-model 15 15

16 An extension * AnyElement itsresolution = 1 = TAI Simplified view of the MARTE Time meta-model 16 16

17 MARTE TIME MODEL Sketchy example of its use User model Producer c1 Consumer 17 17

18 Logical time in models Sketchy example of its use User model Producer c1 sendevent Consumer receiveevent 18 18

19 Logical time in models Sketchy example of its use User model Producer c1 sendevent on c1.sendevent: LogicalClock Consumer receiveevent on c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete The ordered set of sendevent is bijective with the ordered set of instants of c1.sendevent 19 19

20 CCSL Clock Constraint Specification Language Firstly introduced in the MARTE TIME profile Declarative model-based language integrated with Eclipse Formal semantics (both denotational and operational) Tooled (TimeSquare) Explicitly represents / specifies relations between clocks 20 20

21 CCSL (Clock Constraint Specification Language) Relations: dependencies between clocks Coincidence Exclusion Precedence Alternance = # < ~ Expressions: a mean to create new clocks from others Delay Filtering Union Intersection Periodicity delayedfor X on aclock aclock filteredby abinaryword aclock union anotherclock aclock inter anotherclock periodicon aclock period X offset Y 21 21

22 CCSL (Clock Constraint Specification Language) Relations: dependencies between clocks Coincidence = Exclusion # Precedence < Alternance ~ Expressions: a mean to create new clocks from others Delay delayedfor X on aclock Filtering aclock filteredby abinaryword Union aclock union anotherclock Intersection aclock inter anotherclock Periodicity periodicon aclock period X offset Y Libraries: user-defined relations and expressions for a specific domain 22 22

23 CCSL Sketchy example of its use User model Producer c1 sendevent on c1.sendevent: LogicalClock Consumer receiveevent on c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete The ordered set of sendevent is bijective with the ordered set of instants of c1.sendevent 23 23

24 CCSL Sketchy example of its use User model Producer Consumer c1 sendevent receiveevent on on c1.sendevent: LogicalClock c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete left right R1 : Coincides 24 24

25 CCSL Sketchy example of its use User model Producer Consumer c1 sendevent receiveevent on on c1.sendevent: LogicalClock c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete left right R1 : Precedes 25 25

26 CCSL Sketchy example of its use User model Producer Consumer c1 sendevent receiveevent on on c1.sendevent: LogicalClock c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete left right R1 : Precedes bound:

27 CCSL Sketchy example of its use User model Producer c1 sendevent Consumer receiveevent on on c1.sendevent: LogicalClock c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete R1 : Precedes R1 : delay bound: 3 d: 3 R1 : period R1 : sample p:

28 CCSL Sketchy example of its use User model Producer c1 sendevent Consumer receiveevent on on c1.sendevent: LogicalClock c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete R1 : Precedes R1 : delay bound: 3 d: 3 com1 : MyComSemantics R1 : period p: 3 p: 5 d: 2 b: 3 R1 : sample 28 28

29 CCSL Sketchy example of its use User model Producer c1 sendevent Consumer receiveevent on on c1.sendevent: LogicalClock c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete R1 : Precedes R1 : delay bound: 3 d: 3 com1 : MyComSemantics R1 : period p: 3 p: 5 d: 2 b: 3 R1 : sample 29 29

30 CCSL Sketchy example of its use User model Producer c1 sendevent Consumer receiveevent on on c1.sendevent: LogicalClock c1.receiveevent: LogicalClock MARTE model LogicalClock : ClockType IsLogical : True Nature : discrete R1 : Precedes R1 : delay bound: 3 d: 3 com1 : MyComSemantics p: 5 d: 2 R1 : sample Means to define formally timed Models of b: 3 p: 3 Computations and Communications (MoCCs) R1 : period 30 30

31 Why CCSL? Means to define formally timed Models of Computations and Communications (MoCCs) Notation to describe semantic relations between timed behaviors (illustrated below) Specification of sophisticated synchronizations Polychronous system modeling Akin to Tagged Systems (Lee & Sangiovanni-Vincentelli) 31

32 Synchronous DataFlow Nodes are called actors SDF Meta-model Arcs have a delay Input/Output have a weight (Number of data samples consumed/produced) 32

33 Synchronous DataFlow SDF Metamodel SDF Model 33

34 Synchronous DataFlow SDF firing rules: Actor enabling = each incoming arc carries at least weight tokens Actor execution = atomic consumption/production of tokens by an enabled actor i.e., consume weight tokens on each incoming arcs and produce weight tokens on each outgoing arc Delay is an initial token load on an arc. How can CCSL express this semantics? 34

35 SDF Example Evolutions of the model Static schedule: A A BA A B CC 35

36 How to model SDF graphs in UML? Where is the semantics? Is that compatible with the UML semantics? CCSL makes the semantics explicit within the model 36

37 SDF semantics with CCSL (1/2) SDF CCSL Actor A Clock A; Token T Input i Output o Clock write, read; 37

38 SDF semantics with CCSL (2/2) SDF CCSL 38

39 Example 39

40 Simulate and animate the UML/MARTE model in TimeSquare (

41 Simulate and animate the UML/MARTE model in TimeSquare (

42 AOSTE s Tools TimeSquare Software environment dedicated to the Specification of CCSL constraints Resolution of CCSL constraints Simulation and generation of trace model Animation of UML models Exploration of augmented timing diagrams K-Passa Computation of static schedules for specific MoCCs Marked Graphs, Synchronous DataFlow, Latency-Insensitive Designs, Kperiodical Routed Graphs Analysis (deadlock freeness, safety) Optimization (latency, throughput, interconnect buffer size) Code generation (stand-alone simulator, co-simulation) 42

43 Tool download 43

44 work: the project AOSTE sophia I3S/UNS/INRIA Frédéric Thomas, Étienne Juliot Obeo Jean-Philippe Babau UBO and more... FSE

45 Retro-ingénierie de Traces d'analyse de SIMulation et d'exécution de systèmes temps-réel 45

46 Context : help the designer Designer Code Real time Multi-task execution Analysis of the execution 46 46

47 Context: execution traces Designer JumpShot, Vampir, Linux Tool Eclipse Project Code Real time Multi-task execution Exection analysis and reports Temporal execution traces OTF, VCD 47 47

48 observations Designer Model Code Real time Multi-task execution SDL, AADL... Execution analysis and report Temporal execution traces 48 48

49 RT-Simex objectives Designer Models UML MARTE Eclipse Execution analysis and report AT THE MODEL LEVEL Code Real time Multi-task execution Temporal execution traces 49 49

50 Processus RT-Simex 50 50

51 Processus RT-Simex 51 51

52 Processus RT-Simex CCSL specification 52 52

53 CCSL (Clock Constraint Specification Language) Relations: dependencies between clocks Coincidence = Exclusion # Precedence < Alternance ~ Expressions: a mean to create new clocks from others Delay delayedfor X on aclock Filtering aclock filteredby abinaryword Union aclock union anotherclock Intersection aclock inter anotherclock Periodicity periodicon aclock period X offset Y Libraries: user-defined relations and expressions for a specific domain 53 53

54 Graphical formal annotation over a UML model for RT-Simex

55 Processus RT-Simex CCSL specification 55 55

56 Processus RT-Simex Clock instant must be monitored at runtime CCSL specification 56 56

57 Processus RT-Simex CCSL specification For a specific platform, this is a total order

58 Processus RT-Simex CCSL specification For a specific platform, this is a total order... For two communicating platforms, the traces are multi-clocks and must be Synchronized... The result is a partial order 58 58

59 Processus RT-Simex CCSL specification If simulated, it replays the execution... CCSL specification 59 59

60 Processus RT-Simex CCSL specification If simulated it replays the execution... So you can have a timing diagram, animate the model and so on... CCSL specification 60 60

61 A specification and the actual execution 61 61

62 Processus RT-Simex CCSL specification CCSL specification 62 62

63 Processus RT-Simex CCSL assertions CCSL specification 63 63

64 Processus RT-Simex CCSL assertions CCSL You can simulation both together to see if a violation occurs specification 64 64

65 Processus RT-Simex You can simulation both together to see if a violation occurs CCSL Violation of Clk3b issubclockof clk3 assertions CCSL specification 65 65

66 Conclusion Two uses of CCSL: A formal language to specify MoCC explicitly within a model, MOCC library construction, No hidden rules or implementation Directly linked to the model A formal language to specify real-time properties AND to check the correctness of a specific implementation Possibility to specify construct for a specifict domain, Possibility to change the rolle of a CCSL model, from specification, to assertion

67 Some future ongoing works Heterogenenous systems Clocks and CCSL are a way to explicitly glue various MoCC Use of CCSL for Power Domain Add of user defined simulation policy EDF, RMA and all you can imagine (use of back-end) Optimization of the TimeSquare solver Optimize BDD depending on clock domains Instant refinement

68 Some future ongoing works Heterogenenous systems Clocks and CCSL are a way to explicitly glue various MoCC Use of CCSL for Power Domain Add of user defined simulation policy EDF, RMA and all you can imagine (use of back-end) Optimization of the TimeSquare solver Optimize BDD depending on clock domains Instant refinement

69 Some future ongoing works Heterogenenous systems Clocks and CCSL are a way to explicitly glue various MoCC Use of CCSL for Power Domain Add of user defined simulation policy EDF, RMA and all you can imagine (use of back-end) Optimization of the TimeSquare solver Optimize BDD depending on clock domains Instant refinement

70 Thank you! 70