Memory Arrays (4H) Gate Level Design. Young Won Lim 3/15/16

Transcription

1 Arrays (4H) Gate Level Design Young Won Lim 3/15/16

2 Copyright (c) 2011, 2016 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice. Young Won Lim 3/15/16

3 Access Operations WR n-bit Data k-bit Address RD n-bit Data k-bit Address 3 Young Won Lim 3/15/16

4 A Example 2-bit address 4-bit data WR 4-bit Data bit address 01 2-bit address bit data 0111 WR Address: 01 Data: Young Won Lim 3/15/16

5 A Read Example 2-bit address 4-bit data RD 4-bit Data 2-bit address 10 RD Address: 10 Data: 5 Young Won Lim 3/15/16

6 A and A Map k-bit Address n-bit data k-bit Address Read Input n-bit Data Unit 2 k words n-bit per word Output n-bit Data 2 4 words Young Won Lim 3/15/16

7 Address Bits and Data Bits 4-bit Data Bus 4-bit Address Bus 4-bit data 4-bit Address location Address 00 Address 01 Address 02 Address 03 Address 04 Address 05 Address 06 Address 07 Address 08 Address 09 Address 10 Address 11 Address 12 Address 13 Address 14 Address Data 00 Data 01 Data 02 Data 03 Data 04 Data 05 Data 06 Data 07 Data 08 Data 09 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 7 Young Won Lim 3/15/16

8 Increasing Locations 5-bit Address Address 00 Address 01 Address 02 Address 03 Address 04 Address 05 Address 06 Address 07 Address 08 Address 09 Address 10 Address 11 Address 12 Address 13 Address 14 Address 15 5-bit Address Address 16 Address 17 Address 18 Address 19 Address 20 Address 21 Address 22 Address 23 Address 24 Address 25 Address 26 Address 27 Address 28 Address 29 Address 30 Address 31 8 Young Won Lim 3/15/16

9 Increasing Width 8-bit data Address 00 Address 01 Address 02 Address 03 Address 04 Address 05 Address 06 Address 07 Address 08 Address 09 Address 10 Address 11 Address 12 Address 13 Address 14 Address _ patterns 1111_ Young Won Lim 3/15/16

10 The Inputs and Outputs of a Input n-bit Data k-bit Address Read Unit 2 k words n-bit per word n-bit Data k-bit Address Output n-bit Data 10 Young Won Lim 3/15/16

11 Block Diagram of a Unit Input n-bit word k-bit address n-bit word k-bit address Read Unit 2 k words n-bit per word Output n-bit word words 11

12 Control Lines Input n-bit word k-bit address Read Unit 2 k words n-bit per word Enable Read Output n-bit word 12

13 Address & Data Buses k-bit n-bit k-bit address Mem_En Input n-bit word Unit 2 k words n-bit per word Address Bus Data Bus words RD/WR WR Output n-bit word n-bit Data Bus k-bit Address Bus 13

14 RD & WR Operations Input n-bit word k-bit address n-bit Data Bus WR Mem_En RD/WR Unit 2 k words n-bit per word k-bit Address Bus RD Output n-bit word n-bit Data Bus k-bit Address Bus 14

15 Cycle k-bit address Input n-bit word WR Mem_En RD/WR Unit 2 k words n-bit per word n-bit Data Bus k-bit Address Bus Usually, clock is seldom used. (shown for a reference) Clock k-bit Output n-bit word n-bit 2 4 words Address Enable Data Initiating WR op Valid Address Latch Data Valid Data 15

16 Read Cycle Input n-bit word k-bit address Mem_En RD/WR Unit 2 k words n-bit per word n-bit Data Bus k-bit Address Bus RD Usually, clock is seldom used. (shown for a reference) Clock k-bit Output n-bit word n-bit 2 4 words Address Enable Data Initiating RD op Valid Address Valid Data 16

17 Example 2-bit addr4-bit word WR n-bit Data Bus k-bit Address Bus Usually, clock is seldom used. (shown for a reference) Clock 2-bit addr4-bit word ` Address Enable Data Initiating WR op Latch Data 17

18 Read Example 2-bit addr4-bit word n-bit Data Bus k-bit Address Bus RD Usually, clock is seldom used. (shown for a reference)? 10 Clock Address 10 Enable Initiating RD op Data 18

19 Selecting a Word ed 4-bit word 2-bit address 4-bit word words 19

20 Selecting a Word S R = 1 READ op = 0 WRITE op 20

21 A Map bit address Bit 3 Bit 2 Bit 1 Bit bit data

22 4x4 2-bit address 4-bit word S R = 1 READ op = 0 WRITE op 2-bit address 00 4-bit word

23 Diagram for a 4x4 2-bit addr 4-bit word I3 I2 I1 I0 word0 A1 A0 word1 2 x 4 decoder word2 word3 O3 O2 O1 O0 23

24 Cycle Example for a 4x4 WR Address: 01 Data: 0111 Data: bit address 4-bit word I3 I2 I1 I0 4-bit Data Bus 2-bit address Bus A0 A1 word0 word1 Clock Address 01 Address: 01 2 x 4 decoder word2 Enable Initiating WR op Latch Data word3 Data 0111 O3 O2 O1 O0 Data & Address Buses Output (RD) Data Bus Data: 0111 Input (WR) 24

25 Bi-directional Data Bus n-bit Data Bus k-bit Address Bus 25

26 From to WR n-bit Data Bus k-bit Address Bus RD 26

27 From to RD n-bit Data Bus k-bit Address Bus 27

28 2 to 4 Decoder 2 x 4 decoder : 4 AND gates 4 x 16 decoder : 16 AND gates x 1024 decoder : 1024 AND gates

29 Coincidence Decoder 10 k-bit address n-bit word 2 4 words x x x n-bit word 29

30 8x256 Decoder Register Time Sharing Address Bus 16 Input n-bit word k-bit address CAS Register Read Unit 2 k words n-bit per word RAS 8x256 Decoder 8 x 256 Output n-bit word 8-bit RD n-bit Data Bus k-bit Address Bus 8 x 256 Raw Address Col Address 30

31 References [1] Essential C, Nick Parlante [2] Efficient C Programming, Mark A. Weiss [3] C A Reference Manual, Samuel P. Harbison & Guy L. Steele Jr. [4] C Language Express, I. K. Chun [5] [6] [7] [8] [9] Young Won Lim 3/15/16