Combined Radix-10 and Radix-16 Division Unit

Size: px
Start display at page:

Download "Combined Radix-10 and Radix-16 Division Unit"

Transcription

1 Combined adix- and adix-6 Diviion Unit Tomá ang and Alberto Nannarelli Dept. of Eletrial Engineering and Computer Siene, Univerity of California, Irvine, USA Dept. of Informati & Math. Modelling, Tehnial Univerity of Denmark, Kongen yngby, Denmark Abtrat In thi work we extend a previouly propoed digitreurrene radix- diviion unit to be able to perform alo radix- 6 diviion. The extenion i implified by the fat that in the radix- implementation the uotient digit i deompoed into two part and that thi deompoition i alo appropriate for the radix-6 ae. Moreover, to redue the lateny in the radix- the mot-ignifiant portion of the datapath, inluding the eletion funtion, ha been implemented in radix-2, o that the modifiation of that part to inlude radix-6 onit mainly in ombining the two module to obtain the eletion ontant. The ret of the modifiation relate to the generation of multiple, to the arry-ave adder, to the arry-propagate adder, and to the on-the-fly onverion and rounding. The implementation reult how that the delay of an iteration i imilar to that of the radix- ae and that the area i about thirty perent larger. I. INTODUCTION Hardware implementation of deimal arithmeti unit have reently gained importane beaue they provide higher auray in finanial appliation []. Moreover, to redue the reuired area, it i onvenient to perform in the ame unit the operation for both deimal and binary repreentation. Combined unit of thi type have been propoed for addition [2] and multipliation [3]. In thi work we propoe a ombined unit for the diviion operation. Previouly we deribed a radix- diviion unit uing the digit-reurrene approah []. Moreover, thi approah ha been ued extenively for radix-2 repreentation [5]. Speifially, ine the radix- unit produe one digit of the uotient per iteration and the radix- digit i repreented in by four bit, it eem appropriate to ombine it with a radix-6 unit. Thi ombination i implified by the fat that in the radix- ae we have deompoed the uotient digit into two part, whih i alo the preferred method for implementing radix-6 diviion [5]. II. DIVISION AGOITHM The expreion for the digit-reurrene iteration for the radix- ae are [] v[j] = w[j ] j (5d) w[j] = v[j] j d with j {,, } and j { 2,,,, 2} for a redundany fator ρ =7/9. Similarly, for the radix-6 ae v[j] = 6w[j ] j (d) w[j] = v[j] j d with j { 2,,,, 2} and j { 2,,,, 2} for a redundany fator ρ 6 =/6. Therefore, the two reurrene an be ombined into v[j] = [j ] j (kd) () w[j] = v[j] j d (2) with uotient digit eletion funtion = SE H (, d) (3) = SE ( v, d) () and uotient digit j = kj + j. The with between the two radie i performed by etting a bit uh that when = r =6and k = (radix-6) when = r =and k =5 (radix-) To enure onvergene, the reurrene i initialized a w[] = x/r 2. III. DIVIDE ACHITECTUE The heme implementing the diviion reurrene of () and (2) i hown in Fig.. The divider i ompleted by a unit to onvert the uotient-digit j from the igned-digit to the, or to the binary unigned, repreentation, and to perform the rounding. A mentioned above, the radix eletion i done with a ignal uh that for radix-6 = and for radix- =. Therefore, in the reurrene, we have to proe data both in (for radix-) and in binary (for radix-6). Thi reuire ome modifiation in the arry-ave adder (CSA) a explained in Setion III-D. In [], to peed up the radix- diviion, we implement the mot-ignifiant lie (MS-lie) of the reurrene in radix-2 (two omplement). The onverion, one digit per iteration, from a digit to a -bit binary digit i traightfoard. When ombining with radix-6, we need to apply only minor modifiation in the MS-lie, a explained in Setion III-C. One radix-6 digit i imply tranferred from the dual-radix reurrene part every iteration. In the following, we indiate with lower ae letter (e.g. d) digit-vetor in the dual radix part of the reurrene and with upper ae letter (e.g. D) bit-vetor in the MS-lie. When neeary to peify the radix, radix- digit-vetor are indiated with the ubript (e.g. d ). We now diu the implementation of the relevant blok in Fig. and the onvert-and-round unit /8/$ IEEE 967

2 d^ 3* d preomp. + 2D + kd+ D 6* + 5d + 2d 8d d 5d d 5d 8d x Mux 2: - d - d r-6 r- r-6 r- -2 8d N/A -2 2d 2d - d 5d - d d d 5d d d 2 8d N/A 2 2d 2d m k m H m 2 m m H2 Table + kd radix 2 ^ +3* 2d 2d d d d radix /6 CSA 2d 2d v radix /6 CSA v TABE I OPEATION OF MUT/MUX. SE & H 3 w w 3 Poition of regiter 2 Fig.. Bai implementation of radix-/radix-6 reurrene. A. Preomputation of the multiple Thi blok ompute the multiple of d neeary for both the reurrene and the eletion funtion. In the radix- ae the multiple five time the divior (5d ) and two time the divior (2d ), and their negative, are preomputed. For the radix-6 the multiple reuired are eight, four, and two time the divior (8d, d, and2d); thee are traightfoard to ompute (by hifting) and a eletor i ued to elet among the multiple depending on the radix. The detail of the multiple eletion for the dual radix reurrene i hown in Table I. In the radix-2 MS-lie for the radix-6 diviion, we imply ue a trunated repreentation of 8d, d, and2d. For radix- diviion, the multiple 5d, 2d and their negative are onverted into two omplement. B. Quotient-digit eletion In the uotient digit eletion funtion deribed by (3) and (), the etimate and v are obtained by uing a limited number of digit of the arry-ave repreentation. Although in priniple thi number ould be different, we ue the ame number to implify the heme. The eletion of the uotient-digit i done by preloading eletion ontant and omparion [6]. With repet to the radix- implementation of [], in thi dual radix divider we need to ombine the radix- eletion funtion with the radix- 6 one. We explored two alternative: ) eparate module to generate the ontant for eah radix; 2) a ombined module for both. The ombination of the radie an be done if the ontant m k atify the ondition on the bound of the eletion interval (ee [5] and [] for the detailed derivation). Thee bound are hown in Fig. 2, for the poitive uadrant. The Fig. 2. PD plot for (top) and (bottom) (poitive uadrant). dotted line in the figure, repreent the bound for radix- 6, and the olid line the bound for radix-. The eletion ontant are then hoen by k m k <Uk+ 6 k = {,,, 2} where k i the bound obtained for radix- (olid line in Fig. 2) and Uk+ 6 i the bound for radix-6 (dotted line in Fig. 2). Moreover, we hooe ontant whih are ymmetri with repet to the ign: m 2 = m and m = m. For radix-6 (whih eletion funtion i deompoed into two radix- eletion funtion), 3 bit of the divior d are uffiient to elet the ontant m k d =.b 2 b 3 b

3 M, M 2 SE (u= 2) initialization X () Mux 2: 2 2 SE (u= ) W 2 2 SE W 2 kd H (u=) D v (3) 8D kd kd 8D SE (u=) ritial path +/ KD 2D D D 2D +/ 8D SE (u=2) SE d^ m k M M H2 H Table M M M M H2 H 2 8W 8W 2W 2W 8W 8W Mux 2: CSA :2 mult by /6... d preomp.... (3) w () w () egiter 8d kd kd 8d 2d d d 2d x/r 2 Mux 2: radix r CSA v (3) radix r CSA 6* (3) v 6 v 6* 6 w w mux Poition of regiter adix 2 adix r Fig. 3. Implementation of the dual-radix reurrene. Therefore, to unify the interval on d for both radie, we map the 8 onfiguration. b 2 b 3 b into the loet 3 frational digit repreentation of d. The reulting interval on d and the ontant for both and are reported in Table II. Their bound are plotted in Fig. 2. The value in Table II repreent frational number, that ha to be implemented a integer in the radix-2 eletion funtion. Thi onverion fration to integer i done by M k = m k r 2 and therefore, we get two different enoding for radix- and radix-6. Moreover, with repet to the radix- only implementation, the digit-et of i extended from three to five value for radix-6. For thi reaon, the eletion by omparion i modified by omputing peulatively the five poible outome of ˆv[j]. C. adix-2 mot-ignifiant lie With repet of the implementation of [], the radix-2 MSlie i modified a follow. A piture of the implementation of the reurrene i hown in Fig. 3. ) To produe a 5-value uotient-digit, the eletion funtion for i ompoed of four ign-detetor and the enoder of the uotient digit i lightly hanged. 2) A a oneuene of ), the multiplexer produing (kd) i hanged into a 5: mux and two extra flipflop are reuired to tore. 3) The peulative eletion funtion for i in thi dual radix unit ompoed of five blok omputing peulatively = SE ( rw (kd), ˆd), = { 2,,,, 2} Coneuently, a mux 5:, ontrolled by,mutbe ued to elet among the poible value of. ) The multipliation rw[j] i performed by a CSA :2 and a multiplexer: radix input to CSA :2 6 8W +8W +8W +8W 8W +8W +2W +2W D. Dual-radix arry-ave adder The arry-ave adder (CSA) in the reurrene an be operated by eleting the radix with. A heme of the dualradix CSA i hown in Fig. for one digit, we indiate with x (i) the digit of weight r i. E. Converion and ounding The on-the-fly onverion and rounding implemented in [] an be eaily be adapted to the radix-6 ae, with the exeption of the normalization that in the binary ae reuire hift of one bit, while in radix- the hift i one digit ( bit). Moreover, the adder neeary to ompute the ign of the final reminder, and to determine if it i zero, i implemented in dual-radix. IV. IMPEMENTATION AND COMPAISONS In thi etion we preent the reult of the evaluation of the dual radix diviion unit and a omparion with the deimal divider of [] and a double-preiion radix-6 digit-reurrene diviion unit. 969

4 [d i, d i+ ) m H2 m H m H m H m 2 m m m., , , , , , , , , , , , , , , , , , , , , TABE II CONSTANTS m k FO BOTH ADIX- AND ADIX-6 SEECTION. Unit yle time n. yle lateny peed-up area ratio [n] [n] [μm 2 ] adix-6 (tandard) adix- [] Dual-radix (thi work). 6/2 6.6/2.8.96/ TABE III SUMMA OF ESUTS FO THE SNTHESIZED UNIT. Fig.. ign ign a (i) + +2 out CPA (i+) b (i) out (i) CPA i. ign (i) Sheme of radix-/radix-6 CSA (one digit). We performed a ynthei of the unit of Fig. 3 (plu onvertand-round unit) uing the STM 9 nm CMOS tandard ell library [7] and Synopy Deign Compiler. From the ynthei we etimated the ritial path (inluding etimation at netlit level of wire load) and the area. The ritial path i highlighted in Fig. 3 (dotted line). The reult are ompared with thoe of [] for the radix- diviion and with thoe of [8] for radix-6. The data in Table III how that the delay of the ritial path for the dual radix unit i pratially the ame ine the differene i about one INVFO. The additional area with repet to the implementation of [] orrepond mainly to the following module: multiplexer to elet the multiple of the divior in the preomputation blok; module to ompute the eletion ontant; the extra module in the eletion funtion; the multiplexer for the CSA in the dual radix reurrene (Fig. ). However, by omparing the area of the ombined divider with eparate unit for eah radix, we have about 2% le area. V. CONCUSIONS We onlude that the ombination of both radie in a ingle unit i feaible. The yle time i imilar to that of the radix- (and radix-6) implementation and the additional area an be jutified by onidering that the unit an perform both radix- and radix-6 diviion. The eletion funtion might be implified omewhat by modifying the implementation for radix- of [] uing a et for = { 2,,,, 2}, ine that i alo reuired for radix-6. 97

5 EFEENCES [] M. F. Cowlihaw, Deimal floating-point: algorim for omputer, in Pro. of 6th Sympoium on Computer Arithmeti, June 23, pp.. [2] A. Vazuez and E. Antelo, Conditional peulative deimal addition, Pro. 7th Conferene on eal Number and Computer (NC 7), pp. 7 57, June 26. [3] A. Vazuez, E. Antelo, and P. Montuhi, A new family of highperformane parallel deimal multiplier, to appear in Pro. of 8th Sympoium on Computer Arithmeti, June 27. [] T. ang and A. Nannarelli, A adix- Digit-eurrene Diviion Unit: Algorithm and Arhiteture, IEEE Tranation on Computer, vol. 56, no. 6, pp , June 27. [5] M. Eregova and T. ang, Diviion and Suare oot: Digit-eurrene Algorithm and Implementation. Kluwer Aademi Publiher, 99. [6] N. Burge and C. Hind, Deign Iue in adix- ST Suare oot and Divide Unit, Pro. 35th Ailomar Conferene on Signal, Sytem and Computer, pp , 2. [7] STMiroeletroni. 9nm CMOS9 Deign Platform. [Online]. Available: [8] E. Antelo, T. ang, P. Montuhi, and A. Nannarelli, Digit-reurrene divider with redued logial depth, IEEE Tranation on Computer, vol. 5, pp , July

About this Topic. Topic 4. Arithmetic Circuits. Different adder architectures. Basic Ripple Carry Adder

About this Topic. Topic 4. Arithmetic Circuits. Different adder architectures. Basic Ripple Carry Adder About thi Topi Topi 4 Arithmeti Ciruit Peter Cheung Department of Eletrial & Eletroni Engineering Imperial College London URL: www.ee.imperial.a.uk/pheung/ E-mail: p.heung@imperial.a.uk Comparion of adder

More information

Topics. FPGA Design EECE 277. Number Representation and Adders. Class Exercise. Laboratory Assignment #2

Topics. FPGA Design EECE 277. Number Representation and Adders. Class Exercise. Laboratory Assignment #2 FPGA Deign EECE 277 Number Repreentation and Adder Dr. William H. Robinon Februar 2, 25 Topi There are kind of people in the world, thoe that undertand binar and thoe that don't. Unknown Adminitrative

More information

Incorporating Speculative Execution into Scheduling of Control-flow Intensive Behavioral Descriptions

Incorporating Speculative Execution into Scheduling of Control-flow Intensive Behavioral Descriptions Inorporating Speulative Exeution into Sheduling of Control-flow Intenive Behavioral Deription Ganeh Lakhminarayana, Anand Raghunathan, and Niraj K. Jha Dept. of Eletrial Engineering C&C Reearh Laboratorie

More information

VLSI Design 9. Datapath Design

VLSI Design 9. Datapath Design VLSI Deign 9. Datapath Deign 9. Datapath Deign Lat module: Adder circuit Simple adder Fat addition Thi module omparator Shifter Multi-input Adder Multiplier omparator detector: A = 1 detector: A = 11 111

More information

ISSN (Online), Volume 1, Special Issue 2(ICITET 15), March 2015 International Journal of Innovative Trends and Emerging Technologies

ISSN (Online), Volume 1, Special Issue 2(ICITET 15), March 2015 International Journal of Innovative Trends and Emerging Technologies International Journal of Innovative Trend and Emerging Tehnologie ROBUST SCAN TECHNIQUE FOR SECURED AES AGAINST DIFFERENTIAL CRYPTANALYSIS BASED SIDE CHANNEL ATTACK A.TAMILARASAN 1, MR.A.ANBARASAN 2 1

More information

Pipelined Multipliers for Reconfigurable Hardware

Pipelined Multipliers for Reconfigurable Hardware Pipelined Multipliers for Reonfigurable Hardware Mithell J. Myjak and José G. Delgado-Frias Shool of Eletrial Engineering and Computer Siene, Washington State University Pullman, WA 99164-2752 USA {mmyjak,

More information

Description of Traffic in ATM Networks by the First Erlang Formula

Description of Traffic in ATM Networks by the First Erlang Formula 5th International Conferene on Information Tehnology and Appliation (ICITA 8) Deription of Traffi in ATM Network by the Firt Erlang Formula Erik Chromý, Matej Kavaký and Ivan Baroňák Abtrat In the paper

More information

Parametric Micro-level Performance Models for Parallel Computing

Parametric Micro-level Performance Models for Parallel Computing Computer Siene Tehnial Report Computer Siene 12-5-1994 Parametri Miro-level Performane Model for Parallel Computing Youngtae Kim Iowa State Univerity Mark Fienup Iowa State Univerity Jeffrey S. Clary Iowa

More information

COURSEWORK 1 FOR INF2B: FINDING THE DISTANCE OF CLOSEST PAIRS OF POINTS ISSUED: 9FEBRUARY 2017

COURSEWORK 1 FOR INF2B: FINDING THE DISTANCE OF CLOSEST PAIRS OF POINTS ISSUED: 9FEBRUARY 2017 COURSEWORK 1 FOR INF2B: FINDING THE DISTANCE OF CLOSEST PAIRS OF POINTS ISSUED: 9FEBRUARY 2017 Submiion Deadline: The ourework onit of two part (of a different nature) relating to one problem. A hown below

More information

Laboratory Exercise 6

Laboratory Exercise 6 Laboratory Exercie 6 Adder, Subtractor, and Multiplier The purpoe of thi exercie i to examine arithmetic circuit that add, ubtract, and multiply number. Each type of circuit will be implemented in two

More information

Automatic design of robust PID controllers based on QFT specifications

Automatic design of robust PID controllers based on QFT specifications IFAC Conferene on Advane in PID Control PID'1 Breia (Italy), Marh 8-3, 1 Automati deign of robut PID ontroller baed on QFT peifiation R. Comaòliva*, T. Eobet* J. Quevedo* * Advaned Control Sytem (SAC),

More information

Inverse Kinematics 1 1/29/2018

Inverse Kinematics 1 1/29/2018 Invere Kinemati 1 Invere Kinemati 2 given the poe of the end effetor, find the joint variable that produe the end effetor poe for a -joint robot, given find 1 o R T 3 2 1,,,,, q q q q q q RPP + Spherial

More information

1. Introduction. Abstract

1. Introduction. Abstract Automati Ontology Derivation Uing Clutering for Image Claifiation 1 Latifur Khan and Lei Wang Department of Computer Siene Univerity of Texa at Dalla, TX 75083-0688 Email: [lkhan, leiwang]@utdalla.edu

More information

Relayer Selection Strategies in Cellular Networks with Peer-to-Peer Relaying

Relayer Selection Strategies in Cellular Networks with Peer-to-Peer Relaying Relayer Seletion Strategie in Cellular Network with Peer-to-Peer Relaying V. Sreng, H. Yanikomeroglu, and D. D. Faloner Broadband Communiation and Wirele Sytem (BCWS) Centre Dept. of Sytem and Computer

More information

Datum Transformations of NAV420 Reference Frames

Datum Transformations of NAV420 Reference Frames NA4CA Appliation Note Datum ranformation of NA4 Referene Frame Giri Baleri, Sr. Appliation Engineer Crobow ehnology, In. http://www.xbow.om hi appliation note explain how to onvert variou referene frame

More information

KINEMATIC ANALYSIS OF VARIOUS ROBOT CONFIGURATIONS

KINEMATIC ANALYSIS OF VARIOUS ROBOT CONFIGURATIONS International Reearh Journal of Engineering and Tehnology (IRJET) e-in: 39-6 Volume: 4 Iue: May -7 www.irjet.net p-in: 39-7 KINEMATI ANALYI OF VARIOU ROBOT ONFIGURATION Game R. U., Davkhare A. A., Pakhale..

More information

Macrohomogenous Li-Ion-Battery Modeling - Strengths and Limitations

Macrohomogenous Li-Ion-Battery Modeling - Strengths and Limitations Marohomogenou Li-Ion-Battery Modeling - Strength and Limitation Marku Lindner Chritian Wieer Adam Opel AG Sope Purpoe of the reearh: undertand and quantify impat of implifiation in marohomogeneou model

More information

Pruning Game Tree by Rollouts

Pruning Game Tree by Rollouts Pruning Game Tree by Rollout Bojun Huang Mirooft Reearh bojhuang@mirooft.om Abtrat In thi paper we how that the α-β algorithm and it ueor MT-SSS*, a two lai minimax earh algorithm, an be implemented a

More information

Kinematic design of a double wishbone type front suspension mechanism using multi-objective optimization

Kinematic design of a double wishbone type front suspension mechanism using multi-objective optimization 5 th utralaian Congre on pplied Mehani, CM 2007 10-12 Deember 2007, Bribane, utralia Kinemati deign of a double wihbone tpe front upenion mehanim uing multi-objetive optimiation J. S. wang 1, S. R. Kim

More information

Computer Arithmetic Homework Solutions. 1 An adder for graphics. 2 Partitioned adder. 3 HDL implementation of a partitioned adder

Computer Arithmetic Homework Solutions. 1 An adder for graphics. 2 Partitioned adder. 3 HDL implementation of a partitioned adder Computer Arithmetic Homework 3 2016 2017 Solution 1 An adder for graphic In a normal ripple carry addition of two poitive number, the carry i the ignal for a reult exceeding the maximum. We ue thi ignal

More information

Folding. Hardware Mapped vs. Time multiplexed. Folding by N (N=folding factor) Node A. Unfolding by J A 1 A J-1. Time multiplexed/microcoded

Folding. Hardware Mapped vs. Time multiplexed. Folding by N (N=folding factor) Node A. Unfolding by J A 1 A J-1. Time multiplexed/microcoded Folding is verse of Unfolding Node A A Folding by N (N=folding fator) Folding A Unfolding by J A A J- Hardware Mapped vs. Time multiplexed l Hardware Mapped vs. Time multiplexed/mirooded FI : y x(n) h

More information

Calculations for multiple mixers are based on a formalism that uses sideband information and LO frequencies: ( ) sb

Calculations for multiple mixers are based on a formalism that uses sideband information and LO frequencies: ( ) sb Setting frequeny parameter in the WASP databae A. Harri 24 Aug 2003 Calulation for multiple mixer are baed on a formalim that ue ideband information and LO frequenie: b b := ign f ig f LO f IF := f ig

More information

Distributed Packet Processing Architecture with Reconfigurable Hardware Accelerators for 100Gbps Forwarding Performance on Virtualized Edge Router

Distributed Packet Processing Architecture with Reconfigurable Hardware Accelerators for 100Gbps Forwarding Performance on Virtualized Edge Router Ditributed Packet Proceing Architecture with Reconfigurable Hardware Accelerator for 100Gbp Forwarding Performance on Virtualized Edge Router Satohi Nihiyama, Hitohi Kaneko, and Ichiro Kudo Abtract To

More information

Fall 2010 EE457 Instructor: Gandhi Puvvada Date: 10/1/2010, Friday in SGM123 Name:

Fall 2010 EE457 Instructor: Gandhi Puvvada Date: 10/1/2010, Friday in SGM123 Name: Fall 2010 EE457 Intructor: Gandhi Puvvada Quiz (~ 10%) Date: 10/1/2010, Friday in SGM123 Name: Calculator and Cadence Verilog guide are allowed; Cloed-book, Cloed-note, Time: 12:00-2:15PM Total point:

More information

Shortest Paths in Directed Graphs

Shortest Paths in Directed Graphs Shortet Path in Direted Graph Jonathan Turner January, 0 Thi note i adapted from Data Struture and Network Algorithm y Tarjan. Let G = (V, E) e a direted graph and let length e a real-valued funtion on

More information

Design of High Speed Mac Unit

Design of High Speed Mac Unit Design of High Speed Ma Unit 1 Harish Babu N, 2 Rajeev Pankaj N 1 PG Student, 2 Assistant professor Shools of Eletronis Engineering, VIT University, Vellore -632014, TamilNadu, India. 1 harishharsha72@gmail.om,

More information

OSI Model. SS7 Protocol Model. Application TCAP. Presentation Session Transport. ISDN-UP Null SCCP. Network. MTP Level 3 MTP Level 2 MTP Level 1

OSI Model. SS7 Protocol Model. Application TCAP. Presentation Session Transport. ISDN-UP Null SCCP. Network. MTP Level 3 MTP Level 2 MTP Level 1 Direte Event Simulation of CCS7 DAP Benjamin, AE Krzeinki and S Staven Department of Computer Siene Univerity of Stellenboh 7600 Stellenboh, South Afria fbenj,aek,taveng@.un.a.za ABSTRACT: Complex imulation

More information

Universität Augsburg. Institut für Informatik. Approximating Optimal Visual Sensor Placement. E. Hörster, R. Lienhart.

Universität Augsburg. Institut für Informatik. Approximating Optimal Visual Sensor Placement. E. Hörster, R. Lienhart. Univerität Augburg à ÊÇÅÍÆ ËÀǼ Approximating Optimal Viual Senor Placement E. Hörter, R. Lienhart Report 2006-01 Januar 2006 Intitut für Informatik D-86135 Augburg Copyright c E. Hörter, R. Lienhart Intitut

More information

Floating Point CORDIC Based Power Operation

Floating Point CORDIC Based Power Operation Floating Point CORDIC Baed Power Operation Kazumi Malhan, Padmaja AVL Electrical and Computer Engineering Department School of Engineering and Computer Science Oakland Univerity, Rocheter, MI e-mail: kmalhan@oakland.edu,

More information

KS3 Maths Assessment Objectives

KS3 Maths Assessment Objectives KS3 Math Aement Objective Tranition Stage 9 Ratio & Proportion Probabilit y & Statitic Appreciate the infinite nature of the et of integer, real and rational number Can interpret fraction and percentage

More information

How to Select Measurement Points in Access Point Localization

How to Select Measurement Points in Access Point Localization Proceeding of the International MultiConference of Engineer and Computer Scientit 205 Vol II, IMECS 205, March 8-20, 205, Hong Kong How to Select Meaurement Point in Acce Point Localization Xiaoling Yang,

More information

Fall 2010 EE457 Instructor: Gandhi Puvvada Date: 10/1/2010, Friday in SGM123 Name:

Fall 2010 EE457 Instructor: Gandhi Puvvada Date: 10/1/2010, Friday in SGM123 Name: Fall 2010 EE457 Intructor: Gandhi Puvvada Quiz (~ 10%) Date: 10/1/2010, Friday in SGM123 Name: Calculator and Cadence Verilog guide are allowed; Cloed-book, Cloed-note, Time: 12:00-2:15PM Total point:

More information

Laboratory Exercise 6

Laboratory Exercise 6 Laboratory Exercie 6 Adder, Subtractor, and Multiplier The purpoe of thi exercie i to examine arithmetic circuit that add, ubtract, and multiply number. Each circuit will be decribed in Verilog and implemented

More information

Visual Targeted Advertisement System Based on User Profiling and Content Consumption for Mobile Broadcasting Television

Visual Targeted Advertisement System Based on User Profiling and Content Consumption for Mobile Broadcasting Television Viual Targeted Advertiement Sytem Baed on Uer Profiling and ontent onumption for Mobile Broadating Televiion Silvia Uribe Federio Alvarez Joé Manuel Menéndez Guillermo inero Abtrat ontent peronaliation

More information

Laboratory Exercise 6

Laboratory Exercise 6 Laboratory Exercie 6 Adder, Subtractor, and Multiplier The purpoe of thi exercie i to examine arithmetic circuit that add, ubtract, and multiply number. Each circuit will be decribed in VHL and implemented

More information

A Novel Method for Removing Image Staircase Artifacts

A Novel Method for Removing Image Staircase Artifacts Vol.139 (SIP 016, pp.56-63 http://dx.doi.org/10.1457/atl.016.139.54 A Novel Method for Removing Image Stairae Artifat Zhong Chen 1,, Zhiwei Hou 1, Yuegang Xing, Xiaobing Chen 1 1 Jiangu Key Laboratory

More information

Reduced-Complexity Column-Layered Decoding and. Implementation for LDPC Codes

Reduced-Complexity Column-Layered Decoding and. Implementation for LDPC Codes Redued-Complexity Column-Layered Deoding and Implementation for LDPC Codes Zhiqiang Cui 1, Zhongfeng Wang 2, Senior Member, IEEE, and Xinmiao Zhang 3 1 Qualomm In., San Diego, CA 92121, USA 2 Broadom Corp.,

More information

An Evolutionary Multiple Heuristic with Genetic Local Search for Solving TSP

An Evolutionary Multiple Heuristic with Genetic Local Search for Solving TSP An Evolutionary Multiple Heuriti with Geneti Loal Searh for Solving TSP Peng Gang Ihiro Iimura 2 and Shigeru Nakayama 3 Department of Information and Computer Siene Faulty of Engineering Kagohima Univerity

More information

Course Project: Adders, Subtractors, and Multipliers a

Course Project: Adders, Subtractors, and Multipliers a In the name Allah Department of Computer Engineering 215 Spring emeter Computer Architecture Coure Intructor: Dr. Mahdi Abbai Coure Project: Adder, Subtractor, and Multiplier a a The purpoe of thi p roject

More information

Deterministic Access for DSRC/802.11p Vehicular Safety Communication

Deterministic Access for DSRC/802.11p Vehicular Safety Communication eterminiti Ae for SRC/802.11p Vehiular Safety Communiation Jihene Rezgui, Soumaya Cheraoui, Omar Charoun INTERLAB Reearh Laboratory Univerité de Sherbrooe, Canada {jihene.rezgui, oumaya.heraoui, omar.haroun

More information

9/6/2011. Multiplication. Binary Multipliers The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding

9/6/2011. Multiplication. Binary Multipliers The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding 9/6/2 Multiplication Binary Multipliers The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 4 6 8 2 4 6 8 3 3 6 9 2

More information

Using Bayesian Networks for Cleansing Trauma Data

Using Bayesian Networks for Cleansing Trauma Data Uing Bayeian Network for Cleaning Trauma Data Prahant J. Dohi pdohi@.ui.edu Dept. of Computer Siene Univ of Illinoi, Chiago, IL 60607 Lloyd G. Greenwald lgreenwa@.drexel.edu Dept. of Computer Siene Drexel

More information

Karen L. Collins. Wesleyan University. Middletown, CT and. Mark Hovey MIT. Cambridge, MA Abstract

Karen L. Collins. Wesleyan University. Middletown, CT and. Mark Hovey MIT. Cambridge, MA Abstract Mot Graph are Edge-Cordial Karen L. Collin Dept. of Mathematic Weleyan Univerity Middletown, CT 6457 and Mark Hovey Dept. of Mathematic MIT Cambridge, MA 239 Abtract We extend the definition of edge-cordial

More information

Motion Control (wheeled robots)

Motion Control (wheeled robots) 3 Motion Control (wheeled robot) Requirement for Motion Control Kinematic / dynamic model of the robot Model of the interaction between the wheel and the ground Definition of required motion -> peed control,

More information

arxiv:cs.oh/ v1 7 Mar 2005

arxiv:cs.oh/ v1 7 Mar 2005 A Fat Combined Decimal Adder/Subtractor arxiv:c.oh/0503017 v1 7 Mar 2005 HOOMAN NIKMEHR The Univerity of Adelaide Bu Ali Sina Univerity, Hamedan, Iran and BRADEN PHILLIPS and CHENG-CHEW LIM The Univerity

More information

On - Line Path Delay Fault Testing of Omega MINs M. Bellos 1, E. Kalligeros 1, D. Nikolos 1,2 & H. T. Vergos 1,2

On - Line Path Delay Fault Testing of Omega MINs M. Bellos 1, E. Kalligeros 1, D. Nikolos 1,2 & H. T. Vergos 1,2 On - Line Path Delay Fault Testing of Omega MINs M. Bellos, E. Kalligeros, D. Nikolos,2 & H. T. Vergos,2 Dept. of Computer Engineering and Informatis 2 Computer Tehnology Institute University of Patras,

More information

Laboratory Exercise 6

Laboratory Exercise 6 Laboratory Exercie 6 Adder, Subtractor, and Multiplier a a The purpoe of thi exercie i to examine arithmetic circuit that add, ubtract, and multiply number. Each b c circuit will be decribed in Verilog

More information

(12) Patent Application Publication (10) Pub. No.: US 2003/ A1

(12) Patent Application Publication (10) Pub. No.: US 2003/ A1 US 2003O196031A1 (19) United State (12) Patent Application Publication (10) Pub. No.: US 2003/0196031 A1 Chen (43) Pub. Date: Oct. 16, 2003 (54) STORAGE CONTROLLER WITH THE DISK Related U.S. Application

More information

Dynamically Reconfigurable Neuron Architecture for the Implementation of Self- Organizing Learning Array

Dynamically Reconfigurable Neuron Architecture for the Implementation of Self- Organizing Learning Array Dynamically Reconfigurable Neuron Architecture for the Implementation of Self- Organizing Learning Array Januz A. Starzyk,Yongtao Guo, and Zhineng Zhu School of Electrical Engineering & Computer Science

More information

Background/Review on Numbers and Computers (lecture)

Background/Review on Numbers and Computers (lecture) Bakground/Review on Numbers and Computers (leture) ICS312 Mahine-Level and Systems Programming Henri Casanova (henri@hawaii.edu) Numbers and Computers Throughout this ourse we will use binary and hexadeimal

More information

A note on degenerate and spectrally degenerate graphs

A note on degenerate and spectrally degenerate graphs A note on degenerate and pectrally degenerate graph Noga Alon Abtract A graph G i called pectrally d-degenerate if the larget eigenvalue of each ubgraph of it with maximum degree D i at mot dd. We prove

More information

AN ALGORITHM FOR RESTRICTED NORMAL FORM TO SOLVE DUAL TYPE NON-CANONICAL LINEAR FRACTIONAL PROGRAMMING PROBLEM

AN ALGORITHM FOR RESTRICTED NORMAL FORM TO SOLVE DUAL TYPE NON-CANONICAL LINEAR FRACTIONAL PROGRAMMING PROBLEM RAC Univerity Journal, Vol IV, No, 7, pp 87-9 AN ALGORITHM FOR RESTRICTED NORMAL FORM TO SOLVE DUAL TYPE NON-CANONICAL LINEAR FRACTIONAL PROGRAMMING PROLEM Mozzem Hoain Department of Mathematic Ghior Govt

More information

Self-Contained Automated Construction Deposition System

Self-Contained Automated Construction Deposition System Self-Containe Automate Contrution Depoition Sytem Robert L. William II Ohio Univerity, Athen, Ohio Jame S. Albu an Roger V. Botelman NIST, Gaitherburg, MD Automation in Contrution (an International Reearh

More information

A SIMPLE IMPERATIVE LANGUAGE THE STORE FUNCTION NON-TERMINATING COMMANDS

A SIMPLE IMPERATIVE LANGUAGE THE STORE FUNCTION NON-TERMINATING COMMANDS A SIMPLE IMPERATIVE LANGUAGE Eventually we will preent the emantic of a full-blown language, with declaration, type and looping. However, there are many complication, o we will build up lowly. Our firt

More information

Planning of scooping position and approach path for loading operation by wheel loader

Planning of scooping position and approach path for loading operation by wheel loader 22 nd International Sympoium on Automation and Robotic in Contruction ISARC 25 - September 11-14, 25, Ferrara (Italy) 1 Planning of cooping poition and approach path for loading operation by wheel loader

More information

In-Plane Shear Behavior of SC Composite Walls: Theory vs. Experiment

In-Plane Shear Behavior of SC Composite Walls: Theory vs. Experiment Tranation, MiRT, 6- November,, New Delhi, India Div-VI: Paper ID# 764 In-Plane hear Behavior of C Compoite Wall: Theory v. Experiment Amit H. Varma, ai Zhang, Hoeok Chi 3, Peter Booth 4, Tod Baker 5 Aoiate

More information

An Intro to LP and the Simplex Algorithm. Primal Simplex

An Intro to LP and the Simplex Algorithm. Primal Simplex An Intro to LP and the Simplex Algorithm Primal Simplex Linear programming i contrained minimization of a linear objective over a olution pace defined by linear contraint: min cx Ax b l x u A i an m n

More information

A Boyer-Moore Approach for. Two-Dimensional Matching. Jorma Tarhio. University of California. Berkeley, CA Abstract

A Boyer-Moore Approach for. Two-Dimensional Matching. Jorma Tarhio. University of California. Berkeley, CA Abstract A Boyer-Moore Approach for Two-Dimenional Matching Jorma Tarhio Computer Science Diviion Univerity of California Berkeley, CA 94720 Abtract An imple ublinear algorithm i preented for two-dimenional tring

More information

SIMIT 7. Component Type Editor (CTE) User manual. Siemens Industrial

SIMIT 7. Component Type Editor (CTE) User manual. Siemens Industrial SIMIT 7 Component Type Editor (CTE) Uer manual Siemen Indutrial Edition January 2013 Siemen offer imulation oftware to plan, imulate and optimize plant and machine. The imulation- and optimizationreult

More information

MAT 155: Describing, Exploring, and Comparing Data Page 1 of NotesCh2-3.doc

MAT 155: Describing, Exploring, and Comparing Data Page 1 of NotesCh2-3.doc MAT 155: Decribing, Exploring, and Comparing Data Page 1 of 8 001-oteCh-3.doc ote for Chapter Summarizing and Graphing Data Chapter 3 Decribing, Exploring, and Comparing Data Frequency Ditribution, Graphic

More information

A Radix-10 SRT Divider Based on Alternative BCD Codings

A Radix-10 SRT Divider Based on Alternative BCD Codings A Radix-10 SRT Divider Based on Alternative BCD Codings Alvaro Vázquez, Elisardo Antelo University of Santiago de Compostela Dept. of Electronic and Computer Science 782 Santiago de Compostela, Spain alvaro@dec.usc.es,

More information

Complex Rational Expressions

Complex Rational Expressions Comple ational Epressions What is a Comple ational Epression? A omple rational epression is similar to a omple fration whih has one or more frations in its numerator, denominator, or both The following

More information

Q1:Choose the correct answer:

Q1:Choose the correct answer: Q:Chooe the orret anwer:. Purpoe of an OS i a. Create abtration b. Multiple proee ompete for ue of proeor. Coordination. Sheduler deide a. whih proee get to ue the proeor b. when proee get to ue the proeor.

More information

PROBLEM -1. where S. C basis x. 0, for entering

PROBLEM -1. where S. C basis x. 0, for entering ISSN: 77754 ISO 9:8 Certified Volume 4 Iue 8 February 5 Optimum Solution of Linear Programming Problem by New Method Putta aburao; Supriya N. Khobragade and N.W.Khobragade Department of Mathematic RTM

More information

SPH3UW Unit 7.1 The Ray Model of Light Page 2 of 5. The accepted value for the speed of light inside a vacuum is c m which we usually

SPH3UW Unit 7.1 The Ray Model of Light Page 2 of 5. The accepted value for the speed of light inside a vacuum is c m which we usually SPH3UW Unit 7. The Ray Model of Light Page of 5 Note Phyi Tool box Ray light trael in traight path alled ray. Index of refration (n) i the ratio of the peed of light () in a auu to the peed of light in

More information

A New Approach to Pipeline FFT Processor

A New Approach to Pipeline FFT Processor A ew Approach to Pipeline FFT Proceor Shouheng He and Mat Torkelon Department of Applied Electronic, Lund Univerity S- Lund, SWEDE email: he@tde.lth.e; torkel@tde.lth.e Abtract A new VLSI architecture

More information

View-Based Tree-Language Rewritings

View-Based Tree-Language Rewritings View-Baed Tree-Language Rewriting Lak Lakhmanan, Alex Thomo Univerity of Britih Columbia, Canada Univerity of Vitoria, Canada Importane of tree XML Semi-trutured textual format are very popular.

More information

Advanced Encryption Standard and Modes of Operation

Advanced Encryption Standard and Modes of Operation Advanced Encryption Standard and Mode of Operation G. Bertoni L. Breveglieri Foundation of Cryptography - AES pp. 1 / 50 AES Advanced Encryption Standard (AES) i a ymmetric cryptographic algorithm AES

More information

A METHOD OF REAL-TIME NURBS INTERPOLATION WITH CONFINED CHORD ERROR FOR CNC SYSTEMS

A METHOD OF REAL-TIME NURBS INTERPOLATION WITH CONFINED CHORD ERROR FOR CNC SYSTEMS Vietnam Journal of Science and Technology 55 (5) (017) 650-657 DOI: 10.1565/55-518/55/5/906 A METHOD OF REAL-TIME NURBS INTERPOLATION WITH CONFINED CHORD ERROR FOR CNC SYSTEMS Nguyen Huu Quang *, Banh

More information

Correlation Models for Shadow Fading Simulation

Correlation Models for Shadow Fading Simulation Correlation Model for Shadow Fading Simulation IEEE 80.6 Preentation Submiion Template (Rev. 8.3) Document Number: IEEE S80.6m-07/060 Date Submitted: 007-03-3 Source: I-Kang Fu, Chi-Fang Li, E-mail: IKFu@itri.org.tw

More information

Building a Compact On-line MRF Recognizer for Large Character Set using Structured Dictionary Representation and Vector Quantization Technique

Building a Compact On-line MRF Recognizer for Large Character Set using Structured Dictionary Representation and Vector Quantization Technique 202 International Conference on Frontier in Handwriting Recognition Building a Compact On-line MRF Recognizer for Large Character Set uing Structured Dictionary Repreentation and Vector Quantization Technique

More information

Minimum congestion spanning trees in bipartite and random graphs

Minimum congestion spanning trees in bipartite and random graphs Minimum congetion panning tree in bipartite and random graph M.I. Otrovkii Department of Mathematic and Computer Science St. John Univerity 8000 Utopia Parkway Queen, NY 11439, USA e-mail: otrovm@tjohn.edu

More information

A {k, n}-secret Sharing Scheme for Color Images

A {k, n}-secret Sharing Scheme for Color Images A {k, n}-seret Sharing Sheme for Color Images Rastislav Luka, Konstantinos N. Plataniotis, and Anastasios N. Venetsanopoulos The Edward S. Rogers Sr. Dept. of Eletrial and Computer Engineering, University

More information

Laboratory Exercise 2

Laboratory Exercise 2 Laoratory Exercie Numer and Diplay Thi i an exercie in deigning cominational circuit that can perform inary-to-decimal numer converion and inary-coded-decimal (BCD) addition. Part I We wih to diplay on

More information

DECODING OF ARRAY LDPC CODES USING ON-THE FLY COMPUTATION Kiran Gunnam, Weihuang Wang, Euncheol Kim, Gwan Choi, Mark Yeary *

DECODING OF ARRAY LDPC CODES USING ON-THE FLY COMPUTATION Kiran Gunnam, Weihuang Wang, Euncheol Kim, Gwan Choi, Mark Yeary * DECODING OF ARRAY LDPC CODES USING ON-THE FLY COMPUTATION Kiran Gunnam, Weihuang Wang, Eunheol Kim, Gwan Choi, Mark Yeary * Dept. of Eletrial Engineering, Texas A&M University, College Station, TX-77840

More information

A Specification for Rijndael, the AES Algorithm

A Specification for Rijndael, the AES Algorithm A Speifiation for Rijndael, the AES Algorithm. Notation and Convention. Rijndael Input and Output The input, the output and the ipher key for Rijndael are eah it equene ontaining 28, 92 or 256 it with

More information

Representations and Transformations. Objectives

Representations and Transformations. Objectives Repreentation and Tranformation Objective Derive homogeneou coordinate tranformation matrice Introduce tandard tranformation - Rotation - Tranlation - Scaling - Shear Scalar, Point, Vector Three baic element

More information

Outline: Software Design

Outline: Software Design Outline: Software Design. Goals History of software design ideas Design priniples Design methods Life belt or leg iron? (Budgen) Copyright Nany Leveson, Sept. 1999 A Little History... At first, struggling

More information

A DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR

A DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR Malaysian Journal of Computer Siene, Vol 10 No 1, June 1997, pp 36-41 A DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR Md Rafiqul Islam, Harihodin Selamat and Mohd Noor Md Sap Faulty of Computer Siene and

More information

Algorithms, Mechanisms and Procedures for the Computer-aided Project Generation System

Algorithms, Mechanisms and Procedures for the Computer-aided Project Generation System Algorithms, Mehanisms and Proedures for the Computer-aided Projet Generation System Anton O. Butko 1*, Aleksandr P. Briukhovetskii 2, Dmitry E. Grigoriev 2# and Konstantin S. Kalashnikov 3 1 Department

More information

represent = as a finite deimal" either in base 0 or in base. We an imagine that the omputer first omputes the mathematial = then rounds the result to

represent = as a finite deimal either in base 0 or in base. We an imagine that the omputer first omputes the mathematial = then rounds the result to Sientifi Computing Chapter I Computer Arithmeti Jonathan Goodman Courant Institute of Mathemaial Sienes Last revised January, 00 Introdution One of the many soures of error in sientifi omputing is inexat

More information

Drawing Lines in 2 Dimensions

Drawing Lines in 2 Dimensions Drawing Line in 2 Dimenion Drawing a traight line (or an arc) between two end point when one i limited to dicrete pixel require a bit of thought. Conider the following line uperimpoed on a 2 dimenional

More information

The Minimum Redundancy Maximum Relevance Approach to Building Sparse Support Vector Machines

The Minimum Redundancy Maximum Relevance Approach to Building Sparse Support Vector Machines The Minimum Redundany Maximum Relevane Approah to Building Sparse Support Vetor Mahines Xiaoxing Yang, Ke Tang, and Xin Yao, Nature Inspired Computation and Appliations Laboratory (NICAL), Shool of Computer

More information

Laboratory Exercise 2

Laboratory Exercise 2 Laoratory Exercie Numer and Diplay Thi i an exercie in deigning cominational circuit that can perform inary-to-decimal numer converion and inary-coded-decimal (BCD) addition. Part I We wih to diplay on

More information

A Linear Interpolation-Based Algorithm for Path Planning and Replanning on Girds *

A Linear Interpolation-Based Algorithm for Path Planning and Replanning on Girds * Advance in Linear Algebra & Matrix Theory, 2012, 2, 20-24 http://dx.doi.org/10.4236/alamt.2012.22003 Publihed Online June 2012 (http://www.scirp.org/journal/alamt) A Linear Interpolation-Baed Algorithm

More information

Analysis of input and output configurations for use in four-valued CCD programmable logic arrays

Analysis of input and output configurations for use in four-valued CCD programmable logic arrays nalysis of input and output onfigurations for use in four-valued D programmable logi arrays J.T. utler H.G. Kerkhoff ndexing terms: Logi, iruit theory and design, harge-oupled devies bstrat: s in binary,

More information

[N309] Feedforward Active Noise Control Systems with Online Secondary Path Modeling. Muhammad Tahir Akhtar, Masahide Abe, and Masayuki Kawamata

[N309] Feedforward Active Noise Control Systems with Online Secondary Path Modeling. Muhammad Tahir Akhtar, Masahide Abe, and Masayuki Kawamata he 32nd International Congre and Expoition on Noie Control Engineering Jeju International Convention Center, Seogwipo, Korea, Augut 25-28, 2003 [N309] Feedforward Active Noie Control Sytem with Online

More information

ADAM - A PROBLEM-ORIENTED SYMBOL PROCESSOR

ADAM - A PROBLEM-ORIENTED SYMBOL PROCESSOR ADAM - A PROBLEM-ORIENTED SYMBOL PROCESSOR A. P. Mullery and R. F. Schauer Thoma J. Waton Reearch Center International Buine Machine Corporation Yorktown Height, New York R. Rice International Buine Machine

More information

Multi-Target Tracking In Clutter

Multi-Target Tracking In Clutter Multi-Target Tracking In Clutter John N. Sander-Reed, Mary Jo Duncan, W.B. Boucher, W. Michael Dimmler, Shawn O Keefe ABSTRACT A high frame rate (0 Hz), multi-target, video tracker ha been developed and

More information

Performance of a Robust Filter-based Approach for Contour Detection in Wireless Sensor Networks

Performance of a Robust Filter-based Approach for Contour Detection in Wireless Sensor Networks Performance of a Robut Filter-baed Approach for Contour Detection in Wirele Senor Network Hadi Alati, William A. Armtrong, Jr., and Ai Naipuri Department of Electrical and Computer Engineering The Univerity

More information

Key Terms - MinMin, MaxMin, Sufferage, Task Scheduling, Standard Deviation, Load Balancing.

Key Terms - MinMin, MaxMin, Sufferage, Task Scheduling, Standard Deviation, Load Balancing. Volume 3, Iue 11, November 2013 ISSN: 2277 128X International Journal of Advanced Reearch in Computer Science and Software Engineering Reearch Paper Available online at: www.ijarce.com Tak Aignment in

More information

Lecture 14: Minimum Spanning Tree I

Lecture 14: Minimum Spanning Tree I COMPSCI 0: Deign and Analyi of Algorithm October 4, 07 Lecture 4: Minimum Spanning Tree I Lecturer: Rong Ge Scribe: Fred Zhang Overview Thi lecture we finih our dicuion of the hortet path problem and introduce

More information

SLA Adaptation for Service Overlay Networks

SLA Adaptation for Service Overlay Networks SLA Adaptation for Service Overlay Network Con Tran 1, Zbigniew Dziong 1, and Michal Pióro 2 1 Department of Electrical Engineering, École de Technologie Supérieure, Univerity of Quebec, Montréal, Canada

More information

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Department of Eletrial and Computer Engineering University of Wisonsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2014-2015 Assignment #2 Date Tuesday, September 25, 2014 Due

More information

the data. Structured Principal Component Analysis (SPCA)

the data. Structured Principal Component Analysis (SPCA) Strutured Prinipal Component Analysis Kristin M. Branson and Sameer Agarwal Department of Computer Siene and Engineering University of California, San Diego La Jolla, CA 9193-114 Abstrat Many tasks involving

More information

Topics. Lecture 37: Global Optimization. Issues. A Simple Example: Copy Propagation X := 3 B > 0 Y := 0 X := 4 Y := Z + W A := 2 * 3X

Topics. Lecture 37: Global Optimization. Issues. A Simple Example: Copy Propagation X := 3 B > 0 Y := 0 X := 4 Y := Z + W A := 2 * 3X Lecture 37: Global Optimization [Adapted from note by R. Bodik and G. Necula] Topic Global optimization refer to program optimization that encompa multiple baic block in a function. (I have ued the term

More information

Parallel Block-Layered Nonbinary QC-LDPC Decoding on GPU

Parallel Block-Layered Nonbinary QC-LDPC Decoding on GPU Parallel Blok-Layered Nonbinary QC-LDPC Deoding on GPU Huyen Thi Pham, Sabooh Ajaz and Hanho Lee Department of Information and Communiation Engineering, Inha University, Inheon, 42-751, Korea Abstrat This

More information

Operational Semantics Class notes for a lecture given by Mooly Sagiv Tel Aviv University 24/5/2007 By Roy Ganor and Uri Juhasz

Operational Semantics Class notes for a lecture given by Mooly Sagiv Tel Aviv University 24/5/2007 By Roy Ganor and Uri Juhasz Operational emantic Page Operational emantic Cla note for a lecture given by Mooly agiv Tel Aviv Univerity 4/5/7 By Roy Ganor and Uri Juhaz Reference emantic with Application, H. Nielon and F. Nielon,

More information

A Coarse-to-Fine Classification Scheme for Facial Expression Recognition

A Coarse-to-Fine Classification Scheme for Facial Expression Recognition A Coarse-to-Fine Classifiation Sheme for Faial Expression Reognition Xiaoyi Feng 1,, Abdenour Hadid 1 and Matti Pietikäinen 1 1 Mahine Vision Group Infoteh Oulu and Dept. of Eletrial and Information Engineering

More information

We don t need no generation - a practical approach to sliding window RLNC

We don t need no generation - a practical approach to sliding window RLNC We don t need no generation - a pratial approah to sliding window RLNC Simon Wunderlih, Frank Gabriel, Sreekrishna Pandi, Frank H.P. Fitzek Deutshe Telekom Chair of Communiation Networks, TU Dresden, Dresden,

More information